前瞻网路安全处理器及相关SOC设计与测试技术研发.ppt

前瞻網路安全處理器及相關SOC設計與測試技術研發,分項計畫B 以網路安全處理器為應用之SOC設計平台的系統整合、 晶片規畫與合成之自動化技術之研發,Jenq-Kuen Lee Ting-Ting Hwang,計畫目標,整合清大積體電路設計技術研發中心(DTC)的SOC設計技術與研發人力 研究開發一個前瞻網路安全處理器架構、設計平台 、與晶片原型 研究開發相關的 SOC 設計、自動合成、系統整合、偵錯、驗證、與測試的先進技術 所開發的各項相關技術將可應用於其他 SOC的設計、驗證、與測試並加強其優異性，有助於先進SOC產品之開發 契合矽導國家型計畫目標,計畫架構,分項計畫B-主持人經歷,分項計畫B綜覽,分項計畫B架構,子項計畫1: 網路安全處理器系統整合與晶片規劃技術之研發,子項計畫2: 網路安全處理器的低功率之合成、指令管理與編譯器之設計,子項計畫3: 網路安全處理器電路雜訊分析與消除,自動產生Multi-level Dynamic PLA Layout 於TSMC 0.18u 製程。對於總計劃中網路安全處理器控制單元，延遲將較Standard Cell Design Style 快15%,高效率多階層可程式邏輯陣列的自動佈局產生器,第三年度計畫,能計算出電路最差狀況的電壓降 並修改Power Line Size 使得電壓降的影響能減輕,動態電路的電壓降 (IR Drop) 分析與合成工具,第二年度計畫,受交互雜訊影響的乘積排線總數，能降低至原有的受影響的90%,減輕交互雜訊(Cross Talk)的影響的軟體工具,第一年度計畫,技術指標,產出物,計畫年度,子項計畫4: 網路安全處理器之低功率高效能可變電壓技術,分項計畫B: RoadMap,網路安全處理器的低功率之合成、指令管理與編譯器之設計,網路安全處理器電路雜訊分析與消除,網路安全處理器之低功率高效能可變電壓技術,第一年 2002,第二年 2003,第三年 2004,網路安全處理器平台之系統整合與晶片規劃技術之研發,IP核心元件再使用之方法 與流程,以高階系統規格為主之合 成流程的設計與建構,Multiple-IP模擬器研發,密碼處理器之硬體架構和 指令設計的效能評估,暫存器配置之低功率議題研究,分析交互雜訊效應的電路模型,分析交互雜訊對於不同型態 的動態可程式邏輯陣的列效應,使用乘積行項和輸出入的重 新排序來減輕橫跨影響效應,針對網路安全處理器的特殊系統 加以分析，並訂定此可變電壓 產生器的規格制定與系統分析,快速雛形系統的設計與建構,軟硬體共同模擬/共同驗 證方法與流程之建構,網路安全處理器之編譯器,加密演算法函數庫之建立,多重電壓排程之低功率議題 研究,分析佈局後的潛在電壓降,針對電壓降所需的電路模型,同步電流切換的分析,產生電壓降問題的測試樣本,針對前一年度可變電壓產生器 的分析結果進行電路設計及 硬體製作的研究,以全面同步局部非同步為主 的低功率系統架構之研發,混合同步非同步時序系統之 介面電路設計及系統架構之 合成工具,低功率之編譯器設計,可變電壓之排程,多階可程式輯輯陣列的架構設計,多階可程式輯輯陣列的分割工具,使用Skill語言來完成自動佈局 產生器,針對可變電壓產生器的 電路硬體加以量測及驗證, 並利用所得之數據評估此項 可變電壓技術的效能,分項計畫B-人力配置暨預算分配,子項計畫一：吳中浩教授 2博2碩 子項計畫二：李政崑教授 2博5碩 黃婷婷教授 子項計畫三：張世杰教授 2博2碩 子項計畫四：黃柏鈞教授 2博2碩 博士後研究 1,單位：仟元,Research Progress (-Aug. 1, 2002),System Development Kits For SOC/IP,Simulator Environment,Retargetable Compilers and SDK Kits,Hardware description language,Fast System Software Prototyping,An Example for Simulators and Development Kits for SOC/IP,RF,Baseband,Link Manager,Java Bluetooth API,Applications,SDP,TCS,HCI,L2CAP,Audio,RFComm,Java Processor IP,Bluetooth IP,Embedded SOC Design Methodology Trend?,rapidly exploring and evaluating different architectural and memory configurations using a cycle-accurate simulator and retargetable optimizing compiler to achieve the goal of meeting system-level performance, power, and cost objectives,Shrinking time-to-market cycles,Hardware,Software design in parallel,Architectural Description Language,ADL is a language designed to specify architecture templates for SOCs Features that need to be considered: Natural and concise specification Generality in specification Formal Model of specification Automatic toolkit generation ADL should capture all aspects of SOC design, including ASIC and I/O interfaces,Benefits of ADL,Perform (formal) verification and consistency checking Modify easily the target architecture and memory organization for design space exploration Drive automatically the backend toolkit generation from a single specification Adapt fast prototype of HDL-based high level synthesis by translation from ADL,DSE: Design Space Exploration,The availability of a variety of processor cores, IP libraries (DSP, VLIW, SS/RISC, ASIP), and memory IP libraries (Cache, Buffer, SRAM, DRAM) presents a large exploration space for the choice of a base processor architecture.,Optimizations with Specification in ADL,Timing model information ( instruction execution cycles, memory access cycles) directs compiler optimizations in speed. Power model information ( function unit and memory storage operation power consumption) directs compiler optimizations in low power consumption. Resource model and operation behavior model (pipeline information, data path constraints, ) provide detail compiler optimization issues in instruction selection, resource allocation, scheduling.,ORISAL Features (On-Going Work),An ADL being developed by our R & D efforts. Simulator should be able to be generated directly from the specifications. Power model gives the possibility of compiler optimizations in low power consumption and power estimations with simulators.,Research Progress Power Managements at OS layer,Minimize power consumptions while meet the deadline of real-time tasks To be extended to work with 黃柏鈞教授 on voltage scaling circuits at IP levels.,Intel SpeedStep Technology,Two performance mode Maximum performance mode Battery optimized performance mode Real-time dynamic switching between the two performance modes without resetting the system,Problem Specifications,Fixed Voltage: Average Power (AP) = 1W Shutdown Mechanism: AP = 0.6W Variable Voltage Scheduling: AP = 0.36W,A,B,B,shutdown,5V,5V,3V,5,10,15,15,A,5,Scheduling Algorithm,1. Assume there are n periodic tasks to be scheduled. 2. Sort deadlines in ascending order, namely T1, T2, ., Tn. And put them in a list, called reservation list. Repeat 3-6 when the reservation list is not empty 3. Remove the first task, Ti, from the list. 4. Compute slack time of both low and high voltage schedule, i.e. STL and STH. 5. Compute CTL(Ti) and CTH(Ti). 6. Schedule Ti CTL(Ti) STL, schedule Ti with low voltage if possible. STL CTL(Ti) STH, call decision algorithm. CTL(Ti) STH, CTH(Ti) STH, schedule Ti with high voltage if possible. CTH(Ti) STH, call exception (real-time failures).,Decision Algorithms,Reservation List with RL-FFS (First-come First-serve Scheduling) RL-PTV (Predefined Threshold Value) RL-ACT (Average Computation Time) Comparing the control cycles si RL-APC (Average Power Consumption) Comparing the switching activities i RL-AEC (Average Energy Consumption) Comparing the product of switching activities and control cycles i * si RL-WHS (Weighted Hybrid Scheme) Chose one of the above as a decision-maker by weighted voting.,Simulated System,Dual supply voltages High voltage: 5V at 100MHz Low voltage: 3V at 50.8MHz Threshold voltage: 0.5V Task set CNC (Computerized Numberical Control) machine controller 8 tasks Periodavg = 4575 s Deadlineavg = 3400 s Computation_Time(5V)avg = 305 s Computation_Ti