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浙江工业大学浙西分校信电系系毕业论文(中英文资料)Modeling micro-controller peripheralsfor high-level co-simulation and synthesisMapping a behavior on an embedded system involves hardware-software partitioning and assignment of software and hardware tasks to different components. In particular, software tasks in embedded controllers are mostly assigned to a micro-controller. However, some micro-controller peripherals are implemented with partly programmable components that can be regarded as very simple co-processors with limited instruction sets and capabilities. Embedded system designers are used to mapping some simple software tasks onto these simple co-processors, obtaining overall performances that can be orders of magnitude superior to the ones obtained mapping all software tasks to the micro-controller itself. In this paper, we propose a methodology to specify, simulate, and partition tasks that can be implemented on programmable micro-controller peripherals such as Timing Processing Units P U S ) . Following our general philosophy, we let the designer propose a partition, and we provide an environment 0 to efficiently simulate and evaluate a particular implementation choice 0 to automate downstream synthesis for software, hardware, as well as peripheral programming routines.1 Implementation and Case StudyWe have implemented such a library for the 68hcll family of micro-controllers from Motorola . It includes: 0 The timer unit, implementing input capture and output compare functions, that measure time between input and 0 The ALII convert output events using a 16 bit free running counter. 0 The PWM generators present on a specific family member targeted for automotive applications.Each function of the timer unit and of the PWM generator is described both at the behavioral level, using the simulator timing functions to implement time, and at the Register Transfer level, using a cycle-accurate model of the hardware. The latter is also used for hardware and software synthesis, if the peripheral is not used. C routines are used to interface to the peripheral. The precision of the RTL model can be scaled, by dividing the clock. A single simulation parameter controls this scaling without affecting the overall behavior (apart from the loss of precision).We have specified the functionality of a complete dashboard controller, that uses the 68hcl1 peripherals. Note, with the standard co-design methods, using only fully programmable processors or hardware, all the tasks implemented by the peripherals could be implemented only as software tasks, thus yielding a less performing solution, or as hardware tasks, thus yielding a higher cost and less flexible solution. Hence the method presented here is required in order to obtain a solution quality comparable with manual design.The speed of the behavioral simulation was about 260,000 clock cycles per second. The speed of the RTL simulation ranged almost linearly from 2,000 clock cycles per second to 50,000 clock cycles depending on the clock scaling factor, from 1 to 32. The experiments were performed on a 60MHz ULTRAsparc.At synthesis time, the appropriate U 0 drivers are extracted from the library and customized by the co-design tools. We also synthesized a hardware implementation for the PWM generators of the dashboard controller, because they are not available on all members of the 68hcll family. We analyzed the cost trade-offs of using some small ASIC to implement that function. A hardware implementation, using XILINX FPGAs for rapid prototyping purposes required 374 CLBs (with 203 flip-flops) and 60 U 0 pads, that would fit on a XILINX 4010 chip.2 ConclusionThe proposed solution for high-level specification of micro-controller peripherals retains most of the advantages and flexibility of hardware software co-design (uniform modeling, fast co-simulation, formal verification, flexibility in target implementation,. The limit is that the designer has to decide on whether or not a function is implementable using a particular peripheral, and sometimes such a decision must be made about peripherals that may be only slightly different between different micro-controllers. Further research is still needed to develop mapping techniques from an unbiased specification to partially programmable devices.模拟单片机外设的高级共仿真和综合 映射在一个嵌入系统上的行为包括硬件-软件区分和对于不同成分上硬件和软件的任务。特别的,在嵌入控制上的软件任务由单片机执行。但是,一些单片机外围设备一起实现部分可设计的成分,这些成分被当作限制性的指令组合和能力的非常简单的共处理器。嵌入系统设计者习惯于把一些简单的软件工作映射到这些简单的共处理器,以获得把大规模指令转向获得映射所有软件任务的单片机本身。本文,我们打算一种方法去叙述,仿真,和区分那些可能是被用于可设计的单片机外围设备,比如时间处理单元(TPUs)。通过我们的一般原理,我们让设计者计划分割,且我们提供一个环境去有效仿真和评估一个特殊执行选择。为软件,硬件和外围设备规划常式自动化下游的综合。1、落实和个案研究我们已经实现了来自摩托罗拉的单片机68hcll系列。它包括:定时单元,实现输入摄入输出比较功能,使用16位自由运行计算器的输入和输出两者间的测试时间。 A/D转换器PWM 产生器在一个特定的系列成员上为汽车的申请对准。 我们已经叙述完全的仪表板控制器的功能性,这些控制器使用 68 hcl1 外围设备。注意共设计方法的标准, 使用只有完全可设计的处理器或硬件,所有的被外设实现的工作能仅仅如软件工作那样实现,如此产生一个更高的成本和更少灵活的方法。因此,在这里呈现的方法被要求为了获得一个解决特性相比较手动设计。行为模拟速度大约是260000时钟循环每秒。RTL模拟速度范围从2000时钟循环每秒到5000时钟循环每秒线性变化,依靠时钟计数因素，从1到32。试验在60MHZ的ULTRAsparc上被运行。综合时间,适当的I/O驱动从图书馆和有共设计工具的客户上被修改。我们也为仪表板控制器的 PWM 产生器综合硬