基于DE0的VGA测试.doc

基于DE0的VGA测试作者：齐威王来源：博客园发布时间：2011-01-18 16:31阅读：35 次原文链接 收藏 本次实验用的VGA是HPw17e电脑显示器，其分辨率为144090060，系统时钟106.47MHZ时序如下：同步脉冲FRONT后沿SYNC显示脉冲ACT前沿BACK帧长TOTAL行时序HSYNC1522321440801904列时序VSYNC3289001 932Timequest约束vga.sdc # Generated SDC file vga.sdc# Copyright (C) 1991-2008 Altera Corporation# Your use of Altera Corporations design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Altera Program License # Subscription Agreement, Altera MegaCore Function License # Agreement, or other applicable license agreement, including, # without limitation, that your use is for the sole purpose of # programming logic devices manufactured by Altera and sold by # Altera or its authorized distributors. Please refer to the # applicable agreement for further details.# VENDOR Altera# PROGRAM Quartus II# VERSION Version 8.1 Build 163 10/28/2008 SJ Full Version# DATE Tue Jan 18 15:16:36 2011# DEVICE EP3C16F484C6#*# Time Information#*set_time_format -unit ns -decimal_places 3#*# Create Clock#*create_clock -name clk -period 20.000 -waveform 0.000 10.000 get_ports CLOCK_50#*# Create Generated Clock#*derive_pll_clocks#*# Set Clock Latency#*#*# Set Clock Uncertainty#*derive_clock_uncertainty#*# Set Input Delay#*#*# Set Output Delay#*#*# Set Clock Groups#*#*# Set False Path#*#*# Set Multicycle Path#*#*# Set Maximum Delay#*#*# Set Minimum Delay#*#*# Set Input Transition#*verilog代码文件module vga( input CLOCK_50, input rst_n, output VGA_HS, output VGA_VS, output reg 3:0 VGA_R, output reg 3:0 VGA_G, output reg 3:0 VGA_B);/=/ PARAMETER declarations/=/ Horizontal Parameterparameter H_FRONT = 152;parameter H_SYNC = 232;parameter H_BACK = 80;parameter H_ACT = 1440;parameter H_VALID = H_FRONT+H_SYNC;parameter H_TOTAL = H_FRONT+H_SYNC+H_BACK+H_ACT;/ Vertical Parameterparameter V_FRONT = 3;parameter V_SYNC = 28;parameter V_BACK = 1;parameter V_ACT = 900;parameter V_VALID = V_FRONT+V_SYNC;parameter V_TOTAL = V_FRONT+V_SYNC+V_BACK+V_ACT;/=wire CLK_106;PLL PLL_inst ( .inclk0 ( CLOCK_50 ), .c0 ( CLK_106 ) );assign clk = CLK_106;/-reg10:0 x_cnt; /行坐标reg10:0 y_cnt; /列坐标always (posedge clk or negedge rst_n) if(!rst_n) x_cnt = 11d0; else if(x_cnt = H_TOTAL-1) x_cnt = 11d0; else x_cnt = x_cnt+1b1;always (posedge clk or negedge rst_n) if(!rst_n) y_cnt = 10d0; else if(y_cnt = V_TOTAL-1) y_cnt = 10d0; else if(x_cnt = H_TOTAL-1) y_cnt = H_VALID) & (x_cnt = V_VALID) & (y_cnt = V_VALID+V_ACT); wire10:0 xpos,ypos; /有效显示区坐标assign xpos = x_cnt-H_VALID;assign ypos = y_cnt-V_VALID;/-reg hsync_r,vsync_r; /同步信号产生always (posedge clk or negedge rst_n) if(!rst_n) hsync_r = 1b1; / else if(x_cnt = H_FRONT-1) hsync_r = 1b0; /产生hsync信号 /else if(x_cnt = H_FRONT+H_SYNC-1) hsync_r = 1b1; else if(x_cnt = 0) hsync_r = 1b0; /产生hsync信号 else if(x_cnt = H_FRONT-1) hsync_r = 1b1; always (posedge clk or negedge rst_n) if(!rst_n) vsync_r = 1b1; / else if(y_cnt = V_FRONT-1) vsync_r = 1b0; /产生vsync信号 /else if(y_cnt = V_FRONT+V_SYNC-1) vsync_r = 1b1; else if(y_cnt = 0) vsync_r = 1b0; /产生vsync信号 else if(y_cnt = V_FRONT-1) vsync_r =200) & (xpos=140) & (ypos=580) & (xpos=140) & (ypos=220) & (xpos140) & (ypos=220) & (xpos=440) & (ypos=385)&(xpos=285)&(ypos=315);/- /r,g,b控制液晶屏颜色显示，背景显示蓝色，矩形框显示红蓝色/*assign VGA_R = valid ? 3b000,e_rdy : 4d0;assign VGA_G = valid ? 3b000,(a_dis | b_dis | c_dis | d_dis) : 4d0;assign VGA_B = valid ? 3b000,(a_dis | b_dis | c_dis | d_dis) : 4d0; assign VGA_R = valid ? 4b0000 : 4d0;assign VGA_G = valid ? 4b0000 : 4d0;assign VGA_B = valid ? 4b1111 : 4d0;*/always (posedge clk or negedge rst_n) if(!rst_n) VGA_R3:0,VGA_G3:0,VGA_B3:0 = 12d0; else if(valid) begin VGA_R = 4e_rdy; VGA_G = 4(a_dis | b_dis | c_dis | d_dis); VGA_B = 4(a_dis | b_dis | c_dis | d_dis); end else VGA_R3:0,VGA_G3:0,VGA_B3:0 = 12d0;endmodule基于DE0的VGA显示驱动 显示标准：800*60072HZ，50M时钟频率。器件：cyclone3EP3C16484软件版本：quatus ii9.0代码：顶层模块：module pika(CLOCK_50,VGA_HS,VGA_VS,BUTTON,VGA_G,VGA_R,VGA_B);input CLOCK_50;input 2:0BUTTON;output VGA_HS;output VGA_VS;output 3:0VGA_G;output 3:0VGA_R;output 3:0VGA_B;wire 10:0x_addr;wire 10:0y_addr;wire VGA_HS;wire VGA_VS;wire ready;sync_module u1 (.clk(CLOCK_50),.reset(BUTTON2),.x_addr(x_addr),.y_addr(y_addr),.hsync(VGA_HS),.vsync(VGA_VS),.ready(ready);wire 63:0rom_data;wire 5:0rom_addr;vga_ctrl_module u2 (.clk(CLOCK_50),.reset(BUTTON2),.ready(ready),.x_addr(x_addr),.y_addr(y_addr),.red(VGA_R3),.green(VGA_G3),.blue(VGA_B3),.rom_data(rom_data),.rom_addr(rom_addr);rom u3 (.address(rom_addr),.clock(CLOCK_50),.q(rom_data);endmodule 同步模块：module sync_module(clk,reset,x_addr,y_addr,hsync,vsync,ready);input clk;input reset;output 5:0x_addr;output 5:0y_addr;output hsync;output vsync;output ready;reg 10:0x_count;always(posedge clk or negedge reset)beginif(!reset)x_count=11d0;else if(x_count=11d1040)x_count=11d0;elsex_count=x_count+1d1;endreg 10:0y_count;always(posedge clk or negedge reset)beginif(!reset)y_count=11d0;else if(y_count=11d666)y_count=11d0;else if(x_count=1040)y_count183 & x_count28 & y_count119)?1d1:1d0;assign vsync=(y_count5)?1d1:1d0;endmodule VGA控制模块：module vga_ctrl_module(clk,reset,ready,x_addr,y_addr,red,green,blue,rom_data,rom_addr);input clk;input reset;input ready;input 10:0x_addr;input 10:0y_addr;input 63:0rom_data;output 5:0rom_addr;output red;output green;output blue;reg 5:0rom_adr;always(posedge clk or negedge reset)beginif(!reset)rom_adr300 & y_addr364)rom_adr=y_addr10:0-300;else rom_adr=6d0;endreg 5:0rom_data_bit;always(posedge clk or negedge reset)beginif(!reset)rom_data_bit200 & x_addr264)rom_data_bit=263-x_addr10:0;else rom_data_bit=6d0;endassign rom_addr=rom_adr;assign red=(ready)?rom_datarom_data_bit:1d0;assign green=(ready)?rom_datarom_data_bit:1d0;assign blue=(ready)?rom_datarom_data_bit:1d0;endmodule ROM模块：module rom (address,clock,q);input5:0 address;input clock;output63:0 q;wire 63:0 sub_wire0;wire 63:0 q = sub_wire063:0;altsyncramaltsyncram_component (.clock0 (clock),.address_a (address),.q_a (sub_wire0),.aclr0 (1b0),.aclr1 (1b0),.address_b (1b1),.addressstall_a (1b0),.addressstall_b (1b0),.byteena_a (1b1),.byteena_b (1b1),.clock1 (1b1),.clocken0 (1b1),.clocken1 (1b1),.clocken2 (1b1),.clocken3 (1b1),.data_a (641b1),.data_b (1b1),.eccstatus (),.q_b (),.rden_a (1b1),.rden_b (1b1),.wren_a (1b0),.wren_b (1b0);defparamaltsyncram_component.address_aclr_a = NONE,altsyncram_component.clock_enable_input_a = BYPASS,altsyncram_component.clock_enable_output_a = BYPASS,altsyncram_component.init_file = rom_pic_mif.mif,altsyncram_ended_device_family = Cyclone III,altsyncram_component.lpm_hint = ENABLE_RUNTIME_MOD=NO,altsyncram_component.lpm_type = altsyncram,altsyncram_component.numwords_a = 64,altsyncram_component.operation_mode = ROM,altsyncram_component.outdata_aclr_a = NONE,altsyncram_component.outdata_reg_a = CLOCK0,altsyncram_component.ram_block_type = M9K,altsyncram_component.widthad_a = 6,altsyncram_component.width_a = 64,altsyncram_component.width_byteena_a = 1;endmodule初始化ROM的MIF表的内容（比卡丘）：000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000180000000000000038000000000000003C000000000000007C00000000000000FC00000700000000FE00003F00000000E60001FF00000001860007FF00000001C6000C3E0000000101F8701C000000018FFFE0380000000184078030000000016000006078000001000000C0C8000003000001C0CF000003003803010780000F004C160300C0000D807C1C0300E0000F007C0C060060001720380C060060001A6001060600C000180003820C0180001CFFC7C30C0300001C7707C1B80E00001C3F07C118180000BC1E01F1B0180000EC0003B1D83000018200071BCC3C000181000219C6160000C1000031660E000060000020371C000028000000AC3000003C0001E1F0E0000006001B5BFCC0000003001F03FCE0000003803581FC600000010031807FC00000038030E07F80000001000840F800000001C008C0F000000000C018C3C000000000C01D830000000000600E8C00000