quartus-II-软件做4的位乘法器设计(vhdl-语言).doc

用quartus II 软件设计4位乘法器1. 并行乘法的算法： 下面根据乘法例题来分析这种算法，题中M4，M3，M2，M1是被乘数，用M表示。N4，N3，N2，N1是乘数，用N表示2.乘法模块Library ieee; Use ieee.std_logic_1164.all;Use ieee.std_logic_unsigned.all;Entity and4a isPort(a:in std_logic_vector(3 downto 0); en:in std_logic; r:out std_logic_vector(3 downto 0);End and4a;Architecture behave of and4a isBegin Process(en,a(3 downto 0) Begin If (en=1) then r=a; Else r=0000; End if;End process;End behave;3. 加法模块Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_unsigned.all;Entity ls283 isPort (o1,o2:in std_logic_vector(3 downto 0); res:out std_logic_vector(4 downto 0);End ls283;Architecture behave of ls283 isBegin Process(o1,o2) Begin res=(0&o1)+(0&o2); End process;End behave;4. 主程序Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_unsigned.all;Entity mul4p isPort (op1,op2:in std_logic_vector(3 downto 0); result:out std_logic_vector(7 downto 0);End mul4p;Architecture count of mul4p is component and4a port (a:in std_logic_vector(3 downto 0); en:in std_logic; r:out std_logic_vector(3 downto 0);End component;Component ls283 port (o1,o2:in std_logic_vector(3 downto 0); res:out std_logic_vector(4 downto 0);End component;Signal sa:std_logic_vector(3 downto 0);Signal sb:std_logic_vector(4 downto 0);Signal sc:std_logic_vector(3 downto 0);Signal sd:std_logic_vector(4 downto 0);Signal se:std_logic_vector(3 downto 0);Signal sf:std_logic_vector(3 downto 0);Signal sg:std_logic_vector(3 downto 0);-signal tmp1:std_logic;Begin sg=(0&sf (3 downto 1); -tmp1op2,en=op1(1),r=se); U1:and4a port map(a=op2,en=op1(3),r=sa); U2:ls283 port map(o1=sb(4 downto 1),o2=sa,res=result(7 downto 3); U3:and4a port map(a=op2,en=op1(2),r=sc); U4:ls283 port map(o1=sc,o2=sd(4 downto 1),res=sb); u5:ls283 port map(o1=sg,o2=se,res=sd); u6:and4a port map(a=op2,en=op1(0),r=sf); result(0)=sf(0); result(1)=sd(0); result(2)=sb(0); -result(7 downto 0)=00000000;End count;5.仿真波形图6.引脚分配图7. 硬件下载编程与硬件实