PIE培训课程.doc

PIE培训课程1 為何需要Start Oxide? 3 2 為何需要Zero layer? Laser Mark? 3 3 目前常用的晶片阻值為何? 換算成濃度值多少? 4 4 矽原子的Lattice constant為何? 換算成表面濃度, 體積濃度各是多少? 4 5 Well製程影響那些元件特性? 5 6 從0.5um至0.18um製程, Well部分的製程改變為何? 其原因何在? 5 7 何謂LOCOS? Typical process flow? 6 8 何謂STI? Typical process flow? 6 9 STI對IC製程有何影響? 可控制因子有哪些? 7 10 何謂ODR? 對產品有何影響? 8 11 ODR pattern density對STI CMP有何影響? 8 12 B-Clean的目的為何? 目前共有幾種B-Clean recipe存在FAB內? 個別的目的有何不同? 8 13 何謂Epi-Wafer? 對產品有何影響? 10 14 SiN CVD dep時爐管各部分的溫度別控制在什麼範圍? 為什麼如此? 10 15 STI蝕刻後需檢查什麼地方以確保蝕刻正常? 這些項目在密集區何疏散區有何不同? 11 16 Active PHO (OD PHO)需檢查什麼以確保製程正確無誤? 這些項目和黃光製程的什麼參數有關? 11 17 黃光區曝光機共有幾種機型? 他們各別有什麼任務? 試列表比較其特性? 12 18 line和DUV分別用什麼樣式的光阻? 試列表比較各光阻特性? 14 19 ODR光罩和OD光罩有何關係? 試畫圖解釋之. 15 20 總共有多少種光阻去除方式? 個別適用於何種情況? 16 21 去除Si3N4時, 為何要在熱磷酸之前加50:1 HF蝕刻? 此蝕刻時間太短有何影響? 17 22 熱磷酸對Si3N4, Oxide的蝕刻率分別是多少? 蝕刻率可控制因子為何? 17 23 Sacrificial oxide (SAC oxide) 的目的為何? 17 24 Vt IMP的目的為何? 對產品電性有何影響? 18 25 N-well implant打入P31, 120KeV. 請估計光阻厚度最少應有多厚? 18 26 請畫出Gate oxide程式OGA0070A, 溫度, 氣體流量和時間的關係圖 (請自行查爐管OI) 18 27 Gate oxide對產品影響的參數有哪些? 試描述定量一點 19 28 寫出FN tunneling方程式, 請問0.18um Gate oxide thickness從理論計算應能承受多少MV/cm 1pA 漏電 19 29 Gate oxide 成長有哪些重要考量? 20 30 Gate oxide 前製程B-Clean的目的為何? 其中的APM dip time會影響什麼產品參數? 20 31 Gate oxide厚度如何Monitor? 其量測誤差為何? 線上如何控制厚度保持定值? 22 32 試畫圖說明爐管區測量控片厚度的位置. 距離晶片中心的距離分別是多少? 22 33 說明Gate oxide quality (integrity)如何量度? 解釋不同方法的優缺點 (Vbd, Qbd, Tbd, Do, Yield.) 23 34 解釋名詞, PHO proximity effect, Swing effect, Exposure latitude, Best Focus, Depth of Focus. 24 35 解釋名詞. Lot to lot, within lot wafer to wafer, within wafer, within field, within die uniformity. 請討論其重要次序 26 36 PHO Overlay shift的原因及現象有哪些? 其中有多少種可以經由給機台補償改善? 27 37 PHO recipe的Focus設定值往正+調整後PR profile會有何影響? 往負-調整後PR profile會有何影響? 27 38 請列舉出任何一個產品的Poly光罩EBO logical operation, 並解釋其原因 28 39 Poly CD對產品WAT參數的影響為何? 如何決定最佳的製程CD target? 28 40 何謂ADI, AEI CD bias? 何謂DOS(design on silicon), DOM (design on mask)? 28 41 試列表說明光罩A,B,C,D,E,F,G,H grade之CD target spec, registration spec以及Defect spec 29 42 Poly蝕刻程式分成幾個步驟? 各步驟的目的為何? 29 43 Poly蝕刻步驟如何Monitor? 試說明其Monitor項目及方法 30 44 為何需要在Poly蝕刻後量測產品上的殘留厚度? 此殘留厚度影響什麼產品特性? 30 45 何謂Hot carrier?應如何控制或改善? 30 46 0.25um LOGIC的N+Gate和P+Gate的片電阻值會相差多少? 濃度相差多少? 32 47 何謂Depletion? 何謂Accumulation? 測Po/NW Gate oxide Vbd時Poly和NW何者接到正電位? 為什麼? 33 48 試算出50A gate oxide厚度的電容值大小. 33 49 何謂LDD, DDD, MDD implant? 試比較他們的優缺點 34 50 大斜角度的Implant有何功能? 並解釋Tilt, twist和rotation動作 35 51 試算出A050K300E3T00 implant條件植入 Si substrate的Junction depth以及表面濃度 36 52 降低Device Ioff leakage的方法有哪些? 37 53 S/D implant製程有什麼該注意的特性? 38 54 Sapcer的目的為何? 影響什麼產品特性? 38 55 RPO的目的為何? 影響什麼產品特性? 39 56 Ti silicide C54和C49相的電阻率為何? 兩者之間有何關係? 39 57 試寫出Ti silicide製程流程. 並說明需注意之處 39 58 RTA製程如何監控? Process window如何決定? 40 59 試寫出NMOS在Linear region和Saturation Region時Id和Vd,Vg的關係式 42 60 何謂BPSG, BPTEOS?在製程上有何考量? 42 61 BPSG flow的目的為何? 43 62 為何Flow後在Contact PHO前需作一STD clean? 43 63 何謂Maragonic dry? IPA dry? Spin dry? 43 64 何謂PHO WEE?試寫出0.22um TM8070所有Critical Layer的WEE值 44 65 ILD CMP的目的為何? 需注意什麼問題? 44 66 ILD CMP如何做Post Clean? 44 67 Pre-metal dip的目的為何? 44 68 Contact IMP的目的為何? 44 69 試列表比較CVD和PVD製程的差異 44 70 何謂IMP Ti? Collimated Ti? 其優缺點為何? 44 71 如何定義Step Coverage? 45 72 如何定義Flow angle? 45 73 圖解說明Alignment Mark如何應用R29圖形解決Alignment Mark Missing問題 45 74 何謂CVD-TiN? PVD-TiN? 以及MOCVD-TiN, TiCl4 TiN? 45 75 為何W deposition又分成425C和450C兩種程式? 45 New Integration Engineer Common Questionnaire and Answer collection 1 為何需要Start Oxide? Ans For zero layer PHO process, before PHO PR deposition, there need buffer oxide to isolate PR material on touch with Si. ?Zero layer is designed by ASML stepper system. Prevent the laser mark Si recast being re-deposited onto Si surface directly, because Si is hydrophobic like and these re-depo. Particle is very hard to be rinse off. As the first HIGH temperature cycle for H-L-H denuded zone (oxygen free treatment). Pre-set the surface cleanness condition right after Fab received the new wafer materials. ZERO-START WAFER START (P TYPE、8-12 OHM/SQ) START-OX BCLN1 (22220A) SPM60 / HF180 / APM420 / HPM180 / HF0 START-OX START OX (1100C；350A) ZERO-PHO ZERO PHOTO (ALIGNMENT MASK AT 55 DEG) ZERO-ETCH ZERO FULLY DRY ETCH (OX 350A + SI 1200A) ZERO-ETCH RESIST STRIPPING (PSC) PARTIAL STRIP ZERO-ETCH PR CAROS STRIP (ETCH) SPM+APM 由上表可以很明顯地看出Start OX 的第一個功用，就是不希望為有機成分(C-H bond)的光阻直接碰觸到矽晶圓表面。在電子級的矽晶圓中，氧及碳雜質是無法完全被移除的，一般的含量約為1016 cm-3 左右。除以固溶態(Solid solution)存在外，也會以微析出物(Micro-precipitates)的形式存在於矽晶圓中。這些絕緣的微析出物將會引致在空乏區(Depletion region)的電力場(Field line)彎曲，而造成局部的電場梯度(Field gradient)變大，因此在較低的電壓就有可能造成接面崩潰(Junction breakdown)。另一方面碳氧雜質無論是以插入(Interstitial)或替代(Substitutional)的方式固溶於矽晶圓中也容易變成佈植雜質(Dopant)或缺陷集中的中心。 Start OX的另一個用途則是在WAFER START 刻雷射刻號時高功率雷射入射矽晶圓表面引致的融渣會在START OX REMOVE後被移除，不過FAB5目前是使用Soft-laser來作刻號，並不會有這個問問題。 2 為何需要Zero layer? Laser Mark? Ans Zero layer ASML stepper system requires a zero mark for global alignment purpose. For ASML 300B the overlay spec for single machine is 45nm, for mated 300B machine 75nm and for 300 to 200 machine 3 (empirical number), some PR will collapse under strong rinse recipe. PR integrity: Check if the PHO lithography and track recipe are capable to cope with the minimum OD design rule. No Item Method Remark CD IDOF/EL check CD SEM PR thickness, w/I or w/o ARC, NA, exposure energy, focus, stepper wavelength UDOF/EL check CD SEM WIW uniformity check CD SEM WIF uniformity check CD SEM WID uniformity check CD SEM WIA uniformity check CD SEM CD SEM repeatability check CD SEM Mask DOM check CD SEM PHOTO to reticle bias check CD SEM ETCH to PHOTO bias check CD SEM Cpk and Ppk, Cp and Pp check CD SEM PR Profile PR profile check JEOL DR SEM Standing wave, Swing effect PR footing Scum check JEOL DR SEM Developer recipe, PR/SIN Interface adhesion PR collapse Defect check JEOL DR SEM PR thickness, Developer recipe PR Integrity Resolution check CD SEM NA, Sigma, PR type, PR thickness, Stepper wavelength. Proximity effect check CD SEM Notch check JEOL DR SEM Necking check JEOL DR SEM 17 黃光區曝光機共有幾種機型? 他們各別有什麼任務? 試列表比較其特性? Ans FAB5 PHO area have 8 EQ model (the information should be updated according to E3PHO) as attached table: I- line stepper: Default lithographer I- line scanner: for better uniformity and larger field size DUV stepper: better cd control, critical layer DUV scanner: better resolution and larger field size Stepper & Scanner two groups. Each group can split to DUV & I-line two types. Scanner M/C has the capability of (1)larger field size (26x33mm2) limited only by scan range.(2)better CD control (3) Averaging of aberrations and stage errors by scanning slit. Whats the benefit of using full scanner? Better overlap performance Better resolution performance Better process window Higher throughput: scanner mask can accommodate more dies on one photo shot due to its larger field size (26x33mm2) than stepper (22x22mm2) Able to adopt bigger die: also due to the larger field size TYPE 5500/100 5500/200 5500/200B 5500/22 5500/400 5500/300 5500/550 5500/700 總計 I-line stepper I-line scanner DUV stepper DUV scanner Default lithographer For better uniformity and large field size For critical layer ,better CD control Better resolution For large field size SCAN 5 3 4 12 STEPPER 2 3 11 2 3 21 BPHOEAPHOI APHO1APHO2APHO3 APHOHAPHOFAPHOEAPHODAPHO5APHO6APHO7APHO8APHOCAPHOAAPHOB BPHOFASTP1(off-line) BPHODBPHOBBPHO7BPHO6BPHO3 APHOGAPHO9APHO4 BPHO5BPHO4BPHO1 BPHOCBPHO9BPHO8BPHO2 EQP ID SOURCE TYPE NMBER REMARK EQP ID SOURCE TYPE NMBER REMARK APHO1 I-LINE STEPPER 5500/200 BPHO1 DUV SCAN 5500/550 APHO2 I-LINE STEPPER 5500/200 BPHO2 DUV SCAN 5500/700 APHO3 I-LINE STEPPER 5500/200 BPHO3 I-LINE SCAN 5500/400 APHO4 DUV STEPPER 5500/300 BPHO4 DUV SCAN 5500/550 APHO5 I-LINE STEPPER 5500/200B BPHO5 DUV SCAN 5500/550 APHO6 I-LINE STEPPER 5500/200B BPHO6 I-LINE SCAN 5500/400 APHO7 I-LINE STEPPER 5500/200B BPHO7 I-LINE SCAN 5500/400 APHO8 I-LINE STEPPER 5500/200B BPHO8 DUV SCAN 5500/700 APHO9 DUV STEPPER 5500/300 BPHO9 DUV SCAN 5500/700 APHOA I-LINE STEPPER 5500/200B BPHOA 未裝機 APHOB I-LINE STEPPER 5500/200B BPHOB I-LINE SCAN 5500/400 APHOC I-LINE STEPPER 5500/200B B