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厚度 综合 检测 平台 机构 设计

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滑块厚度综合检测平台分料机构设计,厚度,综合,检测,平台,机构,设计

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南 京 理 工 大 学学生毕业设计（论文）中期检查表学生姓名徐峰学 号0101500131指导教师何云峰选题情况课题名称滑块厚度综合检测平台-检测平台难易程度偏难适中偏易工作量较大合理较小符合规范化的要求任务书有无开题报告有无外文翻译质量优良中差学习态度、出勤情况好一般差工作进度快按计划进行慢中期工作汇报及解答问题情况优良中差中期成绩评定：所在专业意见： 负责人： 年 月 日 南 京 理 工 大 学毕业设计（论文）任务书学 院（系）：机械工程学院专 业：武器系统与工程学 生 姓 名：姜晓波学 号：0101510203设计(论文)题目：滑块厚度综合检测平台分料机构设计起 迄 日 期:2005年3月15日 2005年6月24日设计(论文)地点:南京理工大学指 导 教 师:何云峰专业负责人:发任务书日期: 2005 年 3 月 10 日任务书填写要求1毕业设计（论文）任务书由指导教师根据各课题的具体情况填写，经学生所在专业的负责人审查、学院（系）领导签字后生效。此任务书应在毕业设计（论文）开始前一周内填好并发给学生；2任务书内容必须用黑墨水笔工整书写或按教务处统一设计的电子文档标准格式（可从教务处网页上下载）打印，不得随便涂改或潦草书写，禁止打印在其它纸上后剪贴；3任务书内填写的内容，必须和学生毕业设计（论文）完成的情况相一致，若有变更，应当经过所在专业及学院（系）主管领导审批后方可重新填写；4任务书内有关“学院（系）”、“专业”等名称的填写，应写中文全称，不能写数字代码。学生的“学号”要写全号（2000级为10位数），不能只写最后2位或1位数字；5任务书内“主要参考文献”的填写，应按照国标GB 771487文后参考文献著录规则的要求书写，不能有随意性；6有关年月日等日期的填写，应当按照国标GB/T 740894数据元和交换格式、信息交换、日期和时间表示法规定的要求，一律用阿拉伯数字书写。如“2004年3月15日”或“2004-03-15”。毕 业 设 计（论 文）任 务 书1本毕业设计（论文）课题应达到的目的：为提高空气调节器中的滑块厚度测量精度，本课题拟研制一套自动化程度高、检测效率高的滑块厚度自动综合检测平台。通过本论文的学习，应学会系统所涉及的机械结构设计、分料机构设计、分料机构的控制系统设计。2本毕业设计（论文）课题任务的内容和要求（包括原始数据、技术要求、工作要求等）：该系统由检测平台设计、自动分料机构设计、自动检测系统、自动控制系统等组成。本论文应完成滑块厚度综合检测平台的分料机构总体方案设计及论证、分料机构设计、分料机构的控制系统设计，要求所设计的分料机构应能可靠进行试样的分组。毕 业 设 计（论 文）任 务 书3对本毕业设计（论文）课题成果的要求包括毕业设计论文、图表、实物样品等：1提供本科毕业设计论文，论文应有相应设计的详细说明；2提供系统的测试及控制方案；3机械结构设计的零部件图纸，可附于论文后。4主要参考文献：1 杨渝钦主编.控制电机.第1版.北京：机械工业出版社.19812 安子军.机械原理.第1版.北京：机械工业出版社，19983 柳昌庆,刘庆.测试技术与实验方法.第1版.北京：中国矿业大学出版社.19974 黄继昌.实用机械机构图册.第1版.北京：人民邮电出版社，19965 杨宗豹.电机拖动基础.第1版.北京：冶金工业出版社,19876 西安交通大学理论力学教研室.理论力学.第1版.北京：人民教育出版社，19807 哈尔滨工业大学理论力学教研室.理论力学,第4版.北京：国防工业出版社,19828 黄俊钦.测试系统动力学.第1版.北京：国防工业出版社，199610 童秉枢等.机械CAD技术基础.第1版.北京：清华大学出版社，199611 丁舜年.磁铁与电磁铁的设计.第1版.北京：电工图书出版社，195112 王中发.实用机械设计.第1版.北京：北京理工大学出版社，199813 李正军.计算机测控系统设计与应用.第1版.北京：机械工业出版社，200414 张宝芬，张毅，曹丽.自动检测技术及仪表控制系统. 第1版.北京：化学工业出版社，200015 张冠生,陆俭国.电磁铁与自动电磁元件.第1版.北京：机械工业出版社，1982毕 业 设 计（论 文）任 务 书5本毕业设计（论文）课题工作进度计划：起 迄 日 期工 作 内 容2005年3 月 15 日 3月 25 日3 月 26 日 4 月 15 日4 月 16 日 4 月 30 日5 月 1 日 5 月 15 日5 月 16 日 5 月 30 日6 月 1 日 6 月 20 日论文了解，熟悉，英文翻译资料理解，原理设计，方案论证结构设计、图纸绘制测控系统设计、加工零部件实验、实验方法改进论文撰写、讨论、改进所在专业审查意见：负责人： 年 月 日学院（系）意见：院（系）领导： 年 月 日 毕业设计(论文)外文资料翻译学院（系）： 机械工程学院 专 业： 武器系统与工程 姓 名： 学 号： (用外文写)外文出处： IEEE TRANSACTIONS ON NUCLEAR SCIENCE 附 件： 1.外文资料翻译译文；2.外文原文。 指导教师评语：翻译内容符合毕业设计内容的要求，翻译工作量较大，翻译基本正确、符合科技外语的翻译习惯和用法，较好的完成了翻译工作。 签名： 年 月 日注：请将该封面与附件装订成册。附件1：外文资料翻译译文基于物理实验Simatic PLC运行的实时显示测量摘要：当今，在Forschungszentrum Jlich，大部分适合于物理实验的低速控制系统是由PLC技术和场线系统完成的。在多数情况下，需要通过PLCs 得到确定性的答案。这就提出期望从PLC得到精确的、关于实时性能的问题。Simatic PLCs是主导全球市场的西门子公司制造的。我们将介绍它的响应时间的测量，还将讨论程序结构和硬件配置对PLC运行情况和确定性行为的影响。I. 实验控制系统中的PLC当今，工业自动化技术在物理实验各分系统内得到了很好的应用，例如水或气的供给系统。这导致了PLC的大量应用，尤其是智能自动控制部位已成了工业系统的核心。这其中主要的原因有：1、 大量市场导致的价格低廉；2、 坚固耐用；3、 来自制造商的长期有效的技术支持；4、 专业化（编译器，顺应标准化）；除了单纯的基础设施系统范围，PLC渐渐成为实验控制系统的重要组成部分，代替以VME 或PC为基础的实时系统。这取决于现代PLC系列产品的以下特性：1、 高度可测量性：现代PLC系列产品有大量的CPU类型，不仅性能而且功能和结构都可升级。为满足户外使用或容错要求，还可提供特殊版本。 2、 可扩展性： PLC的标准化设计使其能通过一系列数字或模拟输入/输出模块扩展。并且，集成工艺块可用在不同领域，如：步进电动机控制器，饲服电动机控制器和PID控制器。3、 较强的通信能力：现代PLC至少有一个集成的通信端口，并且针对不同现场和进程总线系统，通过多种通信控制器实现扩展，以实现和其它工业设备的连接。一个重要的应用就是，通过专用场线（如PROFIBUS DP）把中央PLC系统扩展到分散外设间，实现了与非智能的I/O模块间的透明连接。这样一个PLC不仅能进行现场控制，还可以用于远程监控。4、 有利的发展环境：现代PLC系列产品有一个和谐交互的发展环境，支持主要的IEC1311编程语言。典型的，指令表、功能块图和梯形图的表示能动态的转换。发展工具允许半图解式的硬件结构，提供强劲的编译机制，而且，在运行期间允许区段的交换逐渐增加发展。 今天，在FZ Juelich ，全新先进的实验控制系统在很大程度上依赖PLC。如图1中，中子谱仪（分光计）控制系统体系机构所阐明。由于国际市场权威西门子控制着欧洲市场，Simatic S7 PLCs几乎独家占领了 FZ Juelich市场，最流行的是中范围系列S7-300，高端系列S7-400 的目标是应用在有极端表现需求和支持多处理器配置的场合。微型PLC系列S7200 很少用，他被称作S7系列纯粹是市场的原因，并且，他的执行环境与其他S7系列产品不兼容。IM151/CPU 可代替S7-200 作为微型PLC使用。IM151/CPU 是一适用于分散外围设备ET200S 系列的智能控制器。同样，分散外围设备系统ET200L 和ET200M 在Jlich的使用也很普遍。迄今为止，仅SoftPLC WinAC 这一软件在实验室得到测试。以PLC为基础的控制系统的可靠设计需要他们实时特征方面的知识。1、 取决于PLC的类型，PLC响应时间的数量级是多少？2、 能保证截止期限吗？3、 必须遵守的设计规则是什么？通过对Simatic S7系列不同类型PLC作测试，本论文对这些问题发表观点。标准IEC 1311 对PLC功能和程序设计语言定义了参考标准，专业的PLC制造商必须遵守。如此普遍的结果也能推广到他们的PLC系列产品中。II. SIMATIC S7设计模型正如在POSIX中有详细说明的，传统的实时应用研究是通过实时核心（如OS9或Vx Works），伴随异步并行的程序设计方法完成的。软件开发者依据要解决问题的逻辑结构来组织它的程序结构。这些任务被操作系统准并行执行，并且，这些执行基本上是事件触发的。程序员对各任务分配优先权的同时，把待执行命令的指针送给操作系统。因此，程序员没必要规划程序执行顺序的细节。另一方面，很难理解执行顺序以及判断一个特定的任务是否能赶上它的截止期限。PLC系统中的程序机制就完全不同了，他们采用同步的命令方式。在这里，任务的执行完全是时间触发的，当一个任务需要执行时，程序员必须依照时序把它组织到原任务中去。因此，他必须亲自安排执行顺序，这不仅增大了复杂度而且有了更多的限制。如IEC1131中定义的S7的发展环境，在Step7中 ，所有的代码存在块中。由组织块送出各任务。OBs是预设的操作，在出现特定事件（如定时器溢出或出现错误）时，PLC操作系统访问这些OBs。这样，OBs就成为了操作系统对项目使用者的接口。如图2指出，OBs能调用函数（符合程序语言功能的函数块）。OBs可以调用其它函数，或在POSIX环境中符合操作系统要求的系统函数。功能块/系统功能块是为静态函数分配了数据块的函数类/系统函数类。如图3所示，一个“标准”的PLC程序储于OB1中，被操作系统循环调用。在调用OB1前，操作系统把数据从输入模块调入存储区（过程映象区）。调用OB1后，数据从过程映象区复制到输出模块。这种经过程映象区而间接存取的输入/输出模块减少了存取时间，增加了协调性。监控OBs的执行时间，一旦超出了提前设定的最大时间，将调用时间错误函数命令OB80。对于S7-400 和WinAC，也可以设定OB1的最小周期时间。如果OB1的执行时间少于最小时间，将调用优先级最低的后台命令OB90，其余所有OBs的优先级依次加1。只有对于S7-400 和WinAC，可改动这个默认的优先级。每个OB都能被优先级更高的OB中断。表I列出了有可能的OBs。OBs的有效性取决于CPU类型。如需要较多类型的OBs，必须买个更好的CPU。中断命令OBs在预定时间启动，例如：一次移动结束，尽管时间延迟，中断命令在点计时器结束时启动。定时中断按周期时间反复执行。（循环中断命令OBs以固定的频率启动）。间隔时间和偏移相位可以设成1 ms。硬件中断命令由一个输入事件或功能模块引起。例如：探测到一个数字信号的上升沿。这种功能仅对所谓的“高性能”输入模块有效。异步错误由PLC的错误引起，反之同步错误由用户程序出错引起， 如电源失效，模块失效，或时基出错。当OB无法满足他的计划启动时间，就发生了时间错误，并且是PLCs的一个特点。III. 实时性能测定A. 性能评估目的实时性能的关键是它对外部事件的反应时间。PLC系统基本上遵循同步编程模型，这是由周期时间Tc直接决定的，空运行周期和循环中断（如OB35）必须分析Tc。为确定不同种类PLC的应用范围，必须测定不同类型PLC的Tc最小值。当然，在特定应用场合中Tc的实际值取决于循环块中的代码数量。Tc的波动是循环中断的主要影响因素，它决定了PLC的确定表现。虽有高性能的输入模块，也可能发生硬件中断。必须测量最小的响应时间Tr，即激活OB40的时间，以及它的波动。为了得到一完整图片，必须对微型、中型、高端PLC分别进行测量。表II显示的是本论文中为测量选用的CPU。为了表现出它们的相关性，对变化显著的浮点增量重复测量106次。鉴于以PLC为核心的系统的分布式特性，PROFIBUS 通讯对响应时间的影响非常重要。因此必须分析由于通信导致的额外延迟及波动。但是，与通信相关的测试内容不在本论文讨论范围内，将在以后文章中予以讨论。在像POSIX一样的传统的实时系统中，由硬盘启动、通信及后台运算引起系统运行响应时间，对分析非常关键。由于PLC系统是同步循环操作，所以无需对响应时间做特殊分析。甚至，像PROFIBUS DP V0 or ASinterface这样场线的循环通信也只是引起恒负载。对于异步通信，如TCP/IP，使用智能通信控制器，可以不使用CPU。CPU集成内置的场线MPI（多点接口，专有场线）是一个例外。但在Jlich MPI仅用于编程。B. 测试方案根据图4，待测PLCs的输入端连接到一个脉冲发生器。一个输入信号的上升沿来到时，OB40起作用，输出信号被锁住。脉冲发生器和待测PLCs的输出端接到NI6062E的电压输入端。以100KHz的频率对这些信号采样。Matlab代码已发展到能探测到采样信号的上升沿，计算所需的时差，并据测量数据输出柱状图。这样就可以测量PLC响应时间Tr的分布情况。周期时间Tc的分布可通过类似方法测量。可选择的，信号也可以从系统连接到TDC模块SIS3400。这样，测量数据的正确性和精确度可以得到验证。C. 主程序扫描周期块的测量图57是对表I中前三个PLC 测量得到的OB1的Tc分布情况。模块OB1包含锁住不使用过程映象区而直接数字输出的代码，并且除了OB1没有其它模块起作用。Tc的最小值和它的波动由操作系统的激活引起并随待测PLC运行时间的增加而趋于稳定。尽管S7-300 的Tc值和变化好于IM151/CPU的，最坏的情况是可比拟的。CPU412-2几乎是决定性的（determistic），基本上有两个离散值。这不是CPU行为引起的必要反应，因为在这样的频率，数字输出行为的影响也变得重要。这导致了CPU414-1的典型后果。在测量到0.2ms的最小周期时，在两种输出状态之间的时间有几毫秒的变化，并且伴随着极高的波动。当我们增加CPU414-1中OB1的最小期间值到1ms时，在输出之间变化的时间将大幅降低，并CPU的周期与输出速度一致。这个例子表明必须精心选择I/O模块。为了保护电路，增加电流以减少电磁噪音，过滤以稳定开关读取等，标准模块有几毫秒的次序的延迟。 如预计的，图8是对CPU412-2测量时得到的OB1中Tc的波动情况，每毫秒调用一次OB35引起后台负荷，Tc随后台负荷的持续而增加。Tc的分布几乎是离散的也表示一定存在约0.2ms的内循环。由于PLC是同步操作的，只要知道了每个模块的持续时间就可估计Tc的最大值。结果显示,OB1需要一固定的扫描速率，不足以满足所有应用，例如在操纵系统中.IIID检验循环中断块OB是否能满足这些需求。D. 循环中断块OB35的测量图9、图10表明：和OB1相比，循环中断块OB35的波动是非常小的。同样，CPU412-2表现出几乎离散分布的Tc。任务以1KHz的频率被循环激活，它的精度要好于0.1ms，PLCs的这个特点甚至是基于Pentium II平台的Lynx操作系统不可能实现的。IMI151/CPU的低性能决定它可能的最小的OB35周期是2ms。E. 硬件响应时间测量图11、12是分别使用CPU314C-2DP和IMI151/CPU测量时得到的Tr，Tr是输入上升沿引起的OB40的激活时间，其中包含所有相关硬件时间部分。因为没有符合S7-400 的高性能输入，所以无法对S7-400 系列测量。即使对低档PLC，在IMI151/CPU中测得的Tr平均值和方差值都不能令人满意。虽然在CPU314C-2DP 上测得的Tr值比基于Pentium II 的Lynx操作系统的差五倍，但对于典型的PLC应用场合已经足够了。IV. 结论如上所述，在物理实验中，PLCs的使用提供了众多有利条件。它们以同步循环方式工作并具有高度可预测性。结合它们的实时特性，它们完全能够应用在需要达到毫秒级的确定响应时间的场合。1ms甚至更短的响应时间要求我们在选择硬件时必须非常认真。PLCs不适合用在需要0.5ms或更短的响应时间时。 由于它们的低波动性，循环中断块OBs最适合需要固定扫描速率的场合，然而可以通过硬件中断块来减少响应时间。主循环块OB1不适用于RT操作。以后的工作将关注SoftPLC WinAC ，它不仅可应用在基于PC平台的WindowsNT 系统，Venturecom RTX 实时扩展，同样也可用在MIPS 平台的WindowsCE 系统。另外一个焦点是全新的S7-400 基于循环同步的等时机制。这一特性将允许在分散外围系统中，与CPU周期同步的对I/O端口进行读写操作。附件2：外文原文（复印件）IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 51, NO. 3, JUNE 2004489Measurement of Real-Time Aspects of SimaticPLCOperation in the Context of Physics ExperimentsHarald Kleines, Janos Sarkadi, Frank Suxdorf, and Klaus ZwollAbstractToday, most slow control systems for physics ex-periments at Forschungszentrum Jlich are implemented withProgrammable Logic Controller (PLC) technology and fieldbussystems. In many cases, even deterministic response is requiredfrom the PLCs. This raises the question about the real-timeperformance that can be expected from a PLC. Response-timemeasurements of SimaticPLCsmanufactured by the worldmarket leader Siemensare presented. Influence of programstructure and hardware configuration on performance anddeterministic behavior of a PLC is discussed.I. PROGRAMMABLELOGICCONTROLLERS(PLCS)INEXPERIMENTCONTROLSYSTEMSTODAY, industrial automation technology is well estab-lished in infrastructure systems for physics experiments,e.g., in water or gas supply systems. This leads to the heavy useof Programmable Logic Controllers (PLCs), which typicallyare the intelligent automation stations forming the core ofindustrial systems 1. Main reasons include low prices induced by mass market; robustness; long term availability and support from manufacturer; professionality(connectors,conformancetostandards,)Beyondthescopeofpureinfrastructuresystems,PLCsarein-creasingly becoming central components of experiment controlsystems, replacing VME- or PC-based real-time systems 2,3. This is caused by the following features of modern PLCfamilies. High degree of scalability: Modern PLC families have awide spectrumofCPUtypes,thatis scalablenotonlywithregard to performance, but also with regard to function-ality and form factor. For outdoor or fault tolerant appli-cations special versions are available. Extensibility: The modular design of PLCs enablesthe extension with a wide range of digital and analogI/O modules. Additionally, integrated technology mod-ules are available for different application areas, e.g.,stepper motor controllers, servo motor controllers, or PIDcontrollers. Extensive communication capabilities: Modern PLCshave at least one integrated communication port and canbe extended by a variety of communication controllersManuscript received May 16, 2003; revised October 1, 2003.The authors are with Zentrallabor fr Elektronik, Forschungszentrum Jlich,D-52425 Jlich, Germany (e-mail: h.kleinesfz-juelich.de).Digital Object Identifier 10.1109/TNS.2004.828504for different field and process bus systems, thus enablingconnection of other industrial devices. A key issue isthe extension of a central PLC system with decentralperiphery via special fieldbusses (e.g., PROFIBUS DP),that allows the transparent connection of “unintelligent”I/O-modules. Thus a PLC program can access this decen-tral periphery in the same way as central PLC periphery. Powerful development environment: Modern PLC fami-lies come with a homogeneous cross development envi-ronment, that supports all the major IEC 1131 program-ming languages 4. Typically, representations in instruc-tion list (IL), function block diagram (FBD) or ladderdiagram (LD) can be switched dynamically. The develop-ment tools allow semigraphical hardware configuration,offerstrongdebuggingmechanismsandallowincrementaldevelopment by the exchange of blocks during runtime.Today, in FZ Juelich, all new and advanced experiment con-trol systems are heavily PLC-based 3, as illustrated by the ar-chitecture of a neutron spectrometer control system shown inFig. 1.Because the world market leader Siemens dominates theEuropean market, SimaticS7 PLCs are used in FZ Juelich,almost exclusively. The midrange series S7-300is mostpopular. The high-end series S7-400is targeted at applicationswith extreme performance requirements and supports alsomultiprocessor configurations. The mini PLC series S7-200is rarely used, because it got the name S7 by pure marketingreasons and its programming environment is incompatible tothe other S7 devices. Instead of the S7-200, the IM151/CPUserves as a mini PLC. The IM151/CPU is an intelligentcontroller for the decentral periphery family ET200S. Alsothe decentral periphery systems ET200Land ET200Mareused commonly in Jlich. The SoftPLC WinAChas only beentested in the Lab, so far.The responsible planning of PLC-based control systems re-quires knowledge on their real-time features. What is the magnitude of PLC response time, dependingon PLC type? Can deadlines be guaranteed? What programming rules have to be followed?The paper addresses these issues by measurements at dif-ferent PLC types of the SimaticS7 family. The standard IEC1131 defines a common framework for PLC functionality andprogramming languages 4, which all the major PLC manufac-turers conform to. Thus general results can be generalized alsoto their PLC families.0018-9499/04$20.00 2004 IEEE490IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 51, NO. 3, JUNE 2004Fig. 1.Control system architecture of the neutron spectrometer KWS3.Fig. 2.Block calling hierarchy.II. SIMATICS7 PROGRAMMINGMODELClassical real-time applications in research are implementedwith real-time kernels like OS-9 or VxWorks, that follow anasynchronous parallel programming approach, as defined inPOSIX 5, for example. The software developer structureshis program in tasks according to the logical structure of theproblem to solve. These tasks are executed quasiparallel by theoperatingsystem,andtheexecutionisbasicallyevent-triggered.By assigning priorities to the tasks the programmer gives hintsto the operating system about the desired execution order. Thusthe programmer does not have to plan the scheduling details.On the other hand it is difficult to understand the executionorder and to decide, if a specific task can meet its deadlines.The programming mechanisms in PLC systems are totallydifferent, because they follow the older approach of syn-chronous programming 6. Here, the execution of tasks iscompletely time-triggered, and the programmer has to organizehis program into tasks according to the time, when a task hasto run. So he must plan the execution order himself, which ismore complicated but also gives more control.In Step7, the development environment of the S7, all codeexists in blocks, as defined in IEC1131. Tasks are representedby Organization Blocks (OBs). OBs are the schedulable items,that are called by the operating system of the PLC at certainevents, e.g., when a timer expires or an error occurs. Thus, theOBs are the interface of the operating system to the user pro-gram. As indicated in Fig. 2, OBs can call Functions (FCs),which are blocks that correspond to functions in a procedurallanguage. FCs can call other FCs or system functions (SFCs),whichcorrespondtooperatingsystemcallsinaPOSIXenviron-ment. Function Blocks (FBs)/System Function Blocks (SFCs)are FCs/SFCs with an assigned data block for static functiondata.A “normal” PLC program is contained in OB1, which iscalled cyclically by the operating system, as indicated in Fig. 3.Before OB1 is called the operating system transfers data fromthe input modules to a memory area called process imagetable. After OB1 has been called, data from the process imagetable is copied to the output modules. The indirect access toI/O-modules via the process image table reduces access timeand increases consistency.KLEINES et al.: SIMATICPLC OPERATION491Fig. 3.Execution of main program scan cycle OB1.The execution time of OB1 is monitored, and if a preconfig-uredmaximumis exceeded,thetimeerror OB80 is called.On S7-400and WinACalso a minimumfor the cycletime of OB1 can be configured. If the execution timeforOB1 is less then, the background OB90 is called, whichhas the lowest priority. The priority of all other OBs increaseswith its number. Only on S7-400and WinACthis default pri-ority can be changed. Each OB can be interrupted by OBs witha higher priority. Table I lists the possible OBs. Availability ofOBs depends on the CPU type. If more OBs of a certain typeare required, a more expensive CPU has to be bought.Time-of-day interrupt OBs are started at a preconfiguredtime, e.g., end of a shift, whereas time delays interrupt OBs arestarted at the expiration of a one-shot-timer. Cyclic interruptOBs are started with a fixed frequency. The time interval andthe phase offset can be configured with a granularity of 1 ms.Hardware interrupts OBs are started by a an event at an input orfunction module, e.g., detection of the rising edge of a digitalsignal. This functionality is only available with so-called “HighFeature” input modules. Synchronous error OBs are startedby errors in the user program, whereas asynchronous errorinterrupt OBs are started by PLC faults, like power failure,module failure or time errors. A time error occurs, when an OBcannot meet its scheduled start time, and is an unique featureof PLCs.III. REAL-TIMEPERFORMANCEMEASUREMENTSA. Performance Evaluation GoalsA key issue of real-time performance is the reaction time toexternal events. Because PLC systems basically conform to asynchronousprogrammingmodel,thisisdirectlydeterminedbythe cycle time, which has to be analyzed for the free runningcycle OB1 and cyclic interrupts; e.g., OB35. To determine theapplication area of PLC classes, the minimum ofhas to bemeasured for different PLC types. The actual value ofin aspecific application depends on the amount of code in the cyclicOB, of course.TABLE IOB TYPES OF ASIMATICS7TABLE IIPLCSUNDERTESTDeterministic behavior of a PLC is determined by the jitter of, which is of primary interest for cyclic interrupts.With “High Feature” input modules, also hardware interruptsare possible. Here the minimum response time, which isdefined as the time to activate OB 40, and its jitter has to bemeasured.In order to get a complete picture, the measurements have tobe conducted for a mini PLC, a midrange PLC and a high-endPLC. Table II shows the CPUs, that have been selected for themeasurements in this paper. The time for a floating point addi-tion has been measured by repeating ittimes, in order toconvey an impression of their relative performance, which dif-fers considerably.Because of the distributed nature of PLC-based systems, theimpactofPROFIBUScommunicationtoresponsetimeisanim-492IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 51, NO. 3, JUNE 2004Fig. 4.Experiment setup.Fig. 5.Histogram of OB1 cycle time at IM151/CPU.portant issue. Thus the additional delays introduced by commu-nication as well as the additional jitter have to be analyzed. Butpresentation ofcommunication-relatedmeasurementswouldgobeyond the scope of this paper and will be covered by a futurepublication.The analysis of the response time as a function of the systemload,e.g.,inducedbyharddiskactivity,communicationorback-ground computing, is a key issue on conventional POSIX-likereal-time systems. This is not an issue on PLC systems be-cause of their synchronous cyclic operation. Even the commu-nication on fieldbusses like PROFIBUS DP V0 or AS-Interfaceis cyclically, thus inducing a constant load. For asynchronoustype of communication, e.g., TCP/IP, intelligent communica-tioncontrollersareused,thusoffloadingtheCPU.Anexceptionfrom this rule is the MPI (Multipoint Interface, a proprietaryfieldbus), that is integrated in each CPU. But in Jlich MPI isonly used for programming.B. Measurement ScenarioAccording to Fig. 4 the inputs of the PLCs under test (listedin Table II) are connected to a pulse generator. OB40 is acti-vated by a rising edge of the input signal and toggles a outputsignal. The output of the pulse generator and outputs of thePLCundertestareconnectedtotheNationalInstrumentsanaloginput module NI6062 E. The signals are sampled with a fre-Fig. 6.Histogram of OB1 cycle time at CPU314C-2DP.quency of 100 kHz. Matlab code has been developed that de-tects rising edges in the sampled signals, computes the requiredtime differences and forms an histogram of the measured data.Thus the distribution of the response timeof the PLC can bemeasured. The distribution of the cycle timeis measured inananalogousway.Alternatively,thesignalsareconnectedtotheTDC module SIS 3400 from Struck Innovative Systems. Thusthe correctness and the sufficient precision of the measured datacould be verified.C. Measurements of the Main Program Scan Cycle OB1Figs. 57 show the distribution offor OB1 measured onthe first three PLC in Table I. There was no other activity onthe system than OB1, which only contained code for toggling adigital output directly without using the process image table.The minimum forand its jitter are caused by operatingsystem activities and get better with increasing performance ofthe PLC under test. Although me value and variance offorthe S7-300are much better than for IM151/CPU the worstcase is comparable. CPU412-2 is almost determistic, basicallytaking two discrete values. This is not necessarily caused byCPU behavior, because at these frequencies the behavior of thedigital outputs gets significant, too. This caused artifacts onthe CPU414-1 where we measured a minimum cycle time of0.2 ms. But in this situation the time between two state changesKLEINES et al.: SIMATICPLC OPERATION493Fig. 7.Histogram of OB1 cycle time at CPU412-2.Fig. 8.Histogram of OB1 cycle time at CPU412-2 with background load.of the output was several milliseconds with a extremely highjitter. When we increased the minimum duration of OB1 at theCPU414-1 to 1 ms, the time between output changes becamemuch lower, and cycle time on the CPU was consistent with thespeed of the outputs. This illustrates, that I/O modules have tobe selected carefully. Standard modules havedelays in the orderof milliseconds, because of protection circuits, additional elec-tronics to reduce electromagnetic noise, filters for stable read ofswitches, etc.As expected, Fig. 8 shows that the jitter offor OB1 mea-sured at CPU412-2 increases with constant background load in-duced by OB35 (called every ms). Again the distribution ofis almost discrete, which indicates that there must be some in-ternal cycle of about 0.2 ms. Because of the synchronous oper-ation of a PLC, the maximum ofcan be estimated when theduration of each OB is known. The results show that OB1 is notadequate for applications, which require a fixed scan rate, e.g.,in a control loop. Section III-D examines if a cyclic interruptOB can meet these requirements.Fig. 9.Histogram of OB35 cycle time at CPU314C-2DP.Fig. 10.Histogram of OB35 cycle time at CPU412-2.D. Measurements of the Cyclic Interrupt OB35Figs. 9 and 10 illustrate that the cyclic interrupt OB35 hasan extremely low jitter, compared to OB1. Again CPU412-2exhibits an almost discrete distribution of. Cyclic activationof tasks with a frequency of 1 kHz at a precision better than0.1 ms is a unique feature of PLCs, that is even not possiblewithLynxOSonaPentiumIIplatform7.ThesmallestpossibleOB35 cycle time of IM151/CPU is 2 ms, because of the lowperformance of this CPU.E. Hardware Response-Time MeasurementsFigs. 11 and 12 show, the activation time of OB40with a rising edge of the input, including all hardware-relatedtime fractions, measured at CPU314C-2DP and IM151/CPU.Because we had no “High feature” input for the S7-400,we could not measure this metric for the S7-400series. Themean value ofand its variance measured at IM151/CPUare un