关 键 词：

步进 电机 调速 控制系统 设计 资料

资源描述：

步进电机调速控制系统设计资料,步进,电机,调速,控制系统,设计,资料

内容简介：

1Rectifier Device Data? ? ? ?This data sheet provides information on subminiature size, axial leadmounted rectifiers for generalpurpose lowpower applications.Mechanical CharacteristicsCase: Epoxy, MoldedWeight: 0.4 gram (approximately)Finish: All External Surfaces Corrosion Resistant and Terminal Leads areReadily SolderableLead and Mounting Surface Temperature for Soldering Purposes:220C Max. for 10 Seconds, 1/16 from caseShipped in plastic bags, 1000 per bag.Available Tape and Reeled, 5000 per reel, by adding a “RL” suffix to thepart numberPolarity: Cathode Indicated by Polarity BandMarking: 1N4001, 1N4002, 1N4003, 1N4004, 1N4005, 1N4006, 1N4007MAXIMUM RATINGSRatingSymbol1N40011N40021N40031N40041N40051N40061N4007Unit*Peak Repetitive Reverse VoltageWorking Peak Reverse VoltageDC Blocking VoltageVRRMVRWMVR501002004006008001000Volts*NonRepetitive Peak Reverse Voltage(halfwave, single phase, 60 Hz)VRSM6012024048072010001200Volts*RMS Reverse VoltageVR(RMS)3570140280420560700Volts*Average Rectified Forward Current(single phase, resistive load,60 Hz, see Figure 8, TA = 75C)IO1.0Amp*NonRepetitive Peak Surge Current(surge applied at rated loadconditions, see Figure 2)IFSM30 (for 1 cycle)AmpOperating and Storage JunctionTemperature RangeTJTstg 65 to +175CELECTRICAL CHARACTERISTICS*RatingSymbolTypMaxUnitMaximum Instantaneous Forward Voltage Drop(iF = 1.0 Amp, TJ = 25C) Figure 1vF0.931.1VoltsMaximum FullCycle Average Forward Voltage Drop(IO = 1.0 Amp, TL = 75C, 1 inch leads)VF(AV)0.8VoltsMaximum Reverse Current (rated dc voltage)(TJ = 25C)(TJ = 100C)IR0.051.01050AMaximum FullCycle Average Reverse Current(IO = 1.0 Amp, TL = 75C, 1 inch leads)IR(AV)30A*Indicates JEDEC Registered DataPreferred devices are Motorola recommended choices for future use and best overall value. Motorola, Inc. 1996Order this documentby 1N4001/D?SEMICONDUCTOR TECHNICAL DATA?LEAD MOUNTEDRECTIFIERS501000 VOLTSDIFFUSED JUNCTIONCASE 5903DO411N4004 and 1N4007 areMotorola Preferred DevicesRev 5? ? ?2Rectifier Device DataPACKAGE DIMENSIONSCASE 5903(DO41)ISSUE MBDKKFFADIMMINMAXMINMAXINCHESMILLIMETERSA4.075.200.1600.205B2.042.710.0800.107D0.710.860.0280.034F1.270.050K27.941.100NOTES:1. ALL RULES AND NOTES ASSOCIATED WITHJEDEC DO41 OUTLINE SHALL APPLY.2. POLARITY DENOTED BY CATHODE BAND.3. LEAD DIAMETER NOT CONTROLLED WITHIN FDIMENSION.Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, andspecifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motoroladata sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”must be validated for each customer application by customers technical experts. Motorola does not convey any license under its patent rights nor the rights ofothers. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or otherapplications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injuryor death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorolaand its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney feesarising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges thatMotorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an EqualOpportunity/Affirmative Action Employer.Mfax is a trademark of Motorola, Inc.How to reach us:USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 4321,P.O. Box 5405, Denver, Colorado 80217. 3036752140 or 18004412447NishiGotanda, Shinagawaku, Tokyo 141, Japan. 81354878488Mfax: RMFAX0 TOUCHTONE 6022446609ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, US & Canada ONLY 1800774184851 Ting Kok Road, Tai Po, N.T., Hong Kong. 85226629298INTERNET: /sps1N4001/D主要性能l 与MCS-51单片机产品兼容l 8K字节在线系统可编程Flash存储器l 1000次擦写周期l 4.0V-5.5V工作电压l 全静态操作：0Hz33Hzl 三级加密程序存储器l 256*8字节的内部数据存储器l 32个可编程I/O口线l 三个16位定时器/计数器l 八个中断源l 全双工UART串行通道l 低功耗空闲和掉电模式l 掉电后中断可唤醒l 看门狗定时器l 双数据指针l 掉电标识符l 快速编程周期l 灵活ISP编程（字节和 模式）l 绿色（-免费）工作包操作1功能特性描述AT89S52是一种低功耗、高性能CMOS8位微控制器，具有8K 在线系统可编程Flash 存储器。使用Atmel 公司高密度非易失性存储器技术制造，与工业80C51 产品指令和引脚完全兼容。片上Flash允许程序存储器在系统可编程，亦适于常规编程器。在单芯片上，拥有灵巧的8 位CPU 和在系统可编程Flash，使得AT89S52为众多嵌入式控制应用系统提供高灵活、超有效的解决方案。AT89S52具有以下标准功能： 8k字节Flash，256字节RAM，32 位I/O 口线，看门狗定时器，2 个数据指针，三个16 位定时器/计数器，一个6向量2级中断结构，全双工串行口，片内晶振及时钟电路。另外，AT89S52 可降至0Hz 静态逻辑操作，支持2种软件可选择节电模式。空闲模式下，CPU停止工作，允许RAM、定时器/计数器、串口、中断继续工作。掉电保护方式下，RAM内容被保存，振荡器被冻结，单片机一切工作停止，直到下一个中断或硬件复位为止。2. 引脚结构3. 引脚描述31 VCC : 电源32 GND: 地33 P0 口：P0口是一个8位漏极开路的双向I/O口。作为输出口，每位能驱动8个TTL逻辑电平。对P0端口写“1”时，引脚用作高阻抗输入。当访问外部程序和数据存储器时，P0口也被作为低8位地址/数据复用。在这种模式下，P0具有内部上拉电阻。在flash编程时，P0口也用来接收指令字节；在程序校验时，输出指令字节。程序校验时，需要外部上拉电阻。3P1 口：P1 口是一个具有内部上拉电阻的8 位双向I/O 口。P1 输出缓冲器能驱动4 个TTL 逻辑电平。对P1 端口写“1”时，内部上拉电阻把端口拉高，此时可以作为输入口使用。作为输入使用时，被外部拉低的引脚由于内部电阻的原因，将输出电流（IIL）。此外，P1.0和P1.2分别作定时器/计数器2的外部计数输入（P1.0/T2）和时器/计数器2的触发输入（P1.1/T2EX）。在flash编程和校验时，P1口接收低8位地址字节。引脚号第二功能P1.0T2（定时器/计数器T2的外部计数输入），时钟输出P1.1T2EX（定时器/计数器T2的捕捉/重载触发信号和方向控制）P1.2MOSI（在系统编程用）P1.6MISO（在系统编程用）P1.7SCK（在系统编程用）3.5 P2 口：P2 口是一个具有内部上拉电阻的8 位双向I/O 口，P2 输出缓冲器能驱动4 个TTL 逻辑电平。对P2 端口写“1”时，内部上拉电阻把端口拉高，此时可以作为输入口使用。作为输入使用时，被外部拉低的引脚由于内部电阻的原因，将输出电流（IIL）。在访问外部程序存储器或用16位地址读取外部数据存储器（例如执行MOVX DPTR）时，P2 口送出高八位地址。在这种应用中，P2 口使用很强的内部上拉发送1。在使用8位地址（如MOVX RI）访问外部数据存储器时，P2口输出P2锁存器的内容。在flash编程和校验时，P2口也接收高8位地址字节和一些控制信号。3.6 P3 口：P3 口是一个具有内部上拉电阻的8 位双向I/O 口，p2 输出缓冲器能驱动4 个TTL 逻辑电平。对P3 端口写“1”时，内部上拉电阻把端口拉高，此时可以作为输入口使用。作为输入使用时，被外部拉低的引脚由于内部电阻的原因，将输出电流（IIL）。在flash编程和校验时，P3口也接收一些控制信号。P3口亦作为AT89S52特殊功能（第二功能）使用，如下表所示。Port PinAlternate FunctionsP3.0RXD (serial input port)P3.1TXD (serial output port)P3.2INT0 (external interrupt 0)P3.3INT1 (external interrupt 1)P3.4T0 (timer 0 external input)P3.5T1 (timer 1 external input)P3.6WR (external data memory write strobe)P3.7RD (external data memory read strobe)3.7 RST: 复位输入。晶振工作时，RST脚持续2 个机器周期高电平将使单片机复位。看门狗计时完成后，RST 脚输出96 个晶振周期的高电平。特殊寄存器AUXR(地址8EH)上的DISRTO位可以使此功能无效。DISRTO默认状态下，复位高电平有效。3.8 ALE/PROG：地址锁存控制信号（ALE）是访问外部程序存储器时，锁存低8 位地址的输出脉冲。在flash编程时，此引脚（PROG）也用作编程输入脉冲。在一般情况下，ALE 以晶振六分之一的固定频率输出脉冲，可用来作为外部定时器或时钟使用。然而，特别强调，在每次访问外部数据存储器时，ALE脉冲将会跳过。如果需要，通过将地址为8EH的SFR的第0位置 “1”，ALE操作将无效。这一位置 “1”，ALE 仅在执行MOVX 或MOVC指令时有效。否则，ALE 将被微弱拉高。这个ALE 使能标志位（地址为8EH的SFR的第0位）的设置对微控制器处于外部执行模式下无效。3.9 PSEN:外部程序存储器选通信号（PSEN）是外部程序存储器选通信号。当AT89S52从外部程序存储器执行外部代码时，PSEN在每个机器周期被激活两次，而在访问外部数据存储器时，PSEN将不被激活。3.10 EA/VPP:访问外部程序存储器控制信号。为使能从0000H 到FFFFH的外部程序存储器读取指令，EA必须接GND。为了执行内部程序指令，EA应该接VCC。在flash编程期间，EA也接收12伏VPP电压。3.11 XTAL1:振荡器反相放大器和内部时钟发生电路的输入端。3.12 XTAL2:振荡器反相放大器的输出端。4 特殊功能寄存器特殊功能寄存器(SFR)的地址空间映象如表1所示。并不是所有的地址都被定义了。片上没有定义的地址是不能用的。读这些地址，一般将得到一个随机数据；写入的数据将会无效。用户不应该给这些未定义的地址写入数据“1”。由于这些寄存器在将来可能被赋予新的功能，复位后，这些位都为“0”。定时器2 寄存器：寄存器T2CON 和T2MOD 包含定时器2 的控制位和状态位（如表2和表3所示），寄存器对RCAP2H和RCAP2L是定时器2的捕捉/自动重载寄存器。中断寄存器：各中断允许位在IE寄存器中，六个中断源的两个优先级也可在IE中设置。双数据指针寄存器：为了更有利于访问内部和外部数据存储器，系统提供了两路16位数据指针寄存器：位于SFR中82H83H的DP0和位于84H85。特殊寄存器AUXR1中DPS0 选择DP0；DPS=1 选择DP1。用户应该在访问数据指针寄存器前先初始化DPS至合理的值。掉电标志位：掉电标志位（POF）位于特殊寄存器PCON的第四位（PCON.4）。上电期间POF置“1”。POF可以软件控制使用与否，但不受复位影响。5 存储器结构MCS-51器件有单独的程序存储器和数据存储器。外部程序存储器和数据存储器都可以64K寻址。5.1 程序存储器：如果EA引脚接地，程序读取只从外部存储器开始。对于89S52，如果EA 接VCC，程序读写先从内部存储器（地址为0000H1FFFH）开始，接着从外部寻址，寻址地址为：2000HFFFFH。5.2 数据存储器：AT89S52 有256 字节片内数据存储器。高128 字节与特殊功能寄存器重叠。也就是说高128字节与特殊功能寄存器有相同的地址，而物理上是分开的。当一条指令访问高于7FH 的地址时，寻址方式决定CPU 访问高128 字节RAM 还是特殊功能寄存器空间。直接寻址方式访问特殊功能寄存器（SFR）。例如，下面的直接寻址指令访问0A0H（P2口）存储单元MOV 0A0H , #data使用间接寻址方式访问高128 字节RAM。例如，下面的间接寻址方式中，R0 内容为0A0H，访问的是地址0A0H的寄存器，而不是P2口（它的地址也是0A0H）。MOV R0 , #data堆栈操作也是简介寻址方式。因此，高128字节数据RAM也可用于堆栈空间。6 看门狗定时器WDT是一种需要软件控制的复位方式。WDT 由13位计数器和特殊功能寄存器中的看门狗定时器复位存储器（WDTRST）构成。WDT 在默认情况下无法工作；为了激活WDT，户用必须往WDTRST 寄存器（地址：0A6H）中依次写入01EH 和0E1H。当WDT激活后，晶振工作，WDT在每个机器周期都会增加。WDT计时周期依赖于外部时钟频率。除了复位（硬件复位或WDT溢出复位），没有办法停止WDT工作。当WDT溢出，它将驱动RSR引脚一个高个电平输出。6.1 NWDT的使用为了激活WDT，用户必须向WDTRST寄存器（地址为0A6H的SFR）依次写入0E1H和0E1H。当WDT激活后，用户必须向WDTRST写入01EH和0E1H喂狗来避免WDT溢出。当计数达到8191(1FFFH)时，13 位计数器将会溢出，这将会复位器件。晶振正常工作、WDT激活后，每一个机器周期WDT 都会增加。为了复位WDT，用户必须向WDTRST 写入01EH 和0E1H（WDTRST 是只读寄存器）。WDT 计数器不能读或写。当WDT 计数器溢出时，将给RST 引脚产生一个复位脉冲输出，这个复位脉冲持续96个晶振周期（TOSC），其中TOSC=1/FOSC。为了很好地使用WDT，应该在一定时间内周期性写入那部分代码，以避免WDT复位。6.2 掉电和空闲方式下的WDT在掉电模式下，晶振停止工作，这意味这WDT也停止了工作。在这种方式下，用户不必喂狗。有两种方式可以离开掉电模式：硬件复位或通过一个激活的外部中断。通过硬件复位退出掉电模式后，用户就应该给WDT 喂狗，就如同通常AT89S52 复位一样。通过中断退出掉电模式的情形有很大的不同。中断应持续拉低很长一段时间，使得晶振稳定。当中断拉高后，执行中断服务程序。为了防止WDT在中断保持低电平的时候复位器件，WDT 直到中断拉低后才开始工作。这就意味着WDT 应该在中断服务程序中复位。为了确保在离开掉电模式最初的几个状态WDT不被溢出，最好在进入掉电模式前就复位WDT。在进入待机模式前，特殊寄存器AUXR的WDIDLE位用来决定WDT是否继续计数。默认状态下，在待机模式下，WDIDLE0，WDT继续计数。为了防止WDT在待机模式下复位AT89S52，用户应该建立一个定时器，定时离开待机模式，喂狗，再重新进入待机模式。7 UART在AT89S52 中，UART 的操作与AT89C51 和AT89C52 一样。为了获得更深入的关于UART 的信息，可参考ATMEL 网站（）。从这个主页，选择“Products”，然后选择“8051-Architech Flash Microcontroller”，再选择“ProductOverview”即可。8 定时器0 和定时器1在AT89S52 中，定时器0 和定时器1 的操作与AT89C51 和AT89C52 一样。为了获得更深入的关于UART 的信息，可参考ATMEL 网站（）。从这个主页，选择“Products”，然后选择“8051-Architech Flash Microcontroller”，再选择“ProductOverview”即可。9 定时器2定时器2是一个16位定时/计数器，它既可以做定时器，又可以做事件计数器。其工作方式由特殊寄存器T2CON中的C/T2位选择（如表2所示）。定时器2有三种工作模式：捕捉方式、自动重载（向下或向上计数）和波特率发生器。如表3 所示，工作模式由T2CON中的相关位选择。定时器2 有2 个8位寄存器：TH2和TL2。在定时工作方式中，每个机器周期，TL2 寄存器都会加1。由于一个机器周期由12 个晶振周期构成，因此，计数频率就是晶振频率的1/12。在计数工作方式下，寄存器在相关外部输入角T2 发生1 至0 的下降沿时增加1。在这种方式下，每个机器周期的S5P2期间采样外部输入。一个机器周期采样到高电平，而下一个周期采样到低电平，计数器将加1。在检测到跳变的这个周期的S3P1 期间，新的计数值出现在寄存器中。因为识别10的跳变需要2个机器周期（24个晶振周期），所以，最大的计数频率不高于晶振频率的1/24。为了确保给定的电平在改变前采样到一次，电平应该至少在一个完整的机器周期内保持不变。9.1捕捉方式在捕捉模式下，通过T2CON中的EXEN2来选择两种方式。如果EXEN2=0，定时器2时一个16位定时/计数器，溢出时，对T2CON 的TF2标志置位，TF2引起中断。如果EXEN2=1，定时器2做相同的操作。除上述功能外，外部输入T2EX引脚（P1.1）1至0的下跳变也会使得TH2和TL2中的值分别捕捉到RCAP2H和RCAP2L中。除此之外，T2EX 的跳变会引起T2CON 中的EXF2 置位。像TF2 一样，T2EX 也会引起中断。9.2 自动重载当定时器2 工作于16 位自动重载模式，可对其编程实现向上计数或向下计数。这一功能可以通过特殊寄存器T2MOD（见表4）中的DCEN（向下计数允许位）来实现。通过复位，DCEN 被置为0，因此，定时器2 默认为向上计数。DCEN 设置后，定时器2就可以取决于T2EX向上、向下计数。DCEN=0 时，定时器2 自动计数。通过T2CON 中的EXEN2 位可以选择两种方式。如果EXEN2=0，定时器2计数，计到0FFFFH后置位TF2溢出标志。计数溢出也使得定时器寄存器重新从RCAP2H 和RCAP2L 中加载16 位值。定时器工作于捕捉模式，RCAP2H和RCAP2L的值可以由软件预设。如果EXEN2=1，计数溢出或在外部T2EX（P1.1）引脚上的1到0的下跳变都会触发16位重载。这个跳变也置位EXF2中断标志位。如图6所示，置位DCEN，允许定时器2向上或向下计数。在这种模式下，T2EX引脚控制着计数的方向。T2EX上的一个逻辑1使得定时器2向上计数。定时器计到0FFFFH溢出，并置位TF2。定时器的溢出也使得RCAP2H和RCAP2L中的16位值分别加载到定时器存储器TH2和TL2中。T2EX 上的一个逻辑0 使得定时器2 向下计数。当TH2 和TL2 分别等于RCAP2H 和RCAP2L中的值的时候，计数器下溢。计数器下溢，置位TF2，并将0FFFFH加载到定时器存储器中。定时器2上溢或下溢，外部中断标志位EXF2 被锁死。在这种工作模式下，EXF2不能触发中断。10 波特率发生器通过设置T2CON（见表2）中的TCLK或RCLK可选择定时器2 作为波特率发生器。如果定时器2作为发送或接收波特率发生器，定时器1可用作它用，发送和接收的波特率可以不同。如图8 所示，设置RCLK 和（或）TCLK 可以使定时器2 工作于波特率产生模式。波特率产生工作模式与自动重载模式相似，因此，TH2 的翻转使得定时器2 寄存器重载被软件预置16位值的RCAP2H和RCAP2L中的值。模式1和模式3的波特率由定时器2溢出速率决定，具体如下公式：模式1和模式3波特率晶振频率32 x 65536-(RCAP2H,RCAP2L),其中（RCAP2H,RCAP2L）是RCAP2H和RCAP2L组成的16位无符号整数。16定时器2溢出率定时器可设置成定时器，也可为计数器。在多数应用情况下，一般配置成定时方式（CP/T2=0）。定时器2 用于定时器操作与波特率发生器有所不同，它在每一机器周期（1/12晶振周期）都会增加；然而，作为波特率发生器，它在每一机器状态（1/2晶振周期）都会增加。定时器2 作为波特率发生器，如图8 所示。图中仅仅在T2CON 中RCLK 或TCLK1才有效。特别强调，TH2的翻转并不置位TF2，也不产生中断； EXEN2置位后，T2EX引脚上10的下跳变不会使（RCAP2H，RCAP2L）重载到（TH2，TL2）中。因此，定时器2作为波特率发生器，T2EX也还可以作为一个额外的外部中断。定时器2处于波特率产生模式，TR2=1，定时器2正常工作。TH2或TL2不应该读写。在这种模式下，定时器在每一状态都会增加，读或写就不会准确。寄存器RCAP2可以读，但不能写，因为写可能和重载交迭，造成写和重载错误。在读写定时器2 或RCAP2寄存器时，应该关闭定时器（TR2清0）。11 可编程时钟输出如图9 所示，可以通过编程在P1.0 引脚输出一个占空比为50%的时钟信号。这个引脚除了常规的I/O 角外，还有两种可选择功能。它可以通过编程作为定时器/计数器2 的外部时钟输入或占空比为50%的时钟输出。当工作频率为16MHZ时，时钟输出频率范围为61HZ到4HZ。为了把定时器2配置成时钟发生器，位C/T2（T2CON.1）必须清0，位T2OE（T2MOD.1）必须置1。位TR2（T2CON.2）启动、停止定时器。时钟输出频率取决于晶振频率和定时器2捕捉寄存器（RCAP2H，RCAP2L）的重载值，如公式所示：时钟输出频率4 65536（ 2 , 2 ）晶振频率 RCAP H RCAP L在时钟输出模式下，定时器2不会产生中断，这和定时器2用作波特率发生器一样。定时器2也可以同时用作波特率发生器和时钟产生。不过，波特率和输出时钟频率相互并不独立，它们都依赖于RCAP2H和RCAP2L12 中断AT89S52 有6个中断源：两个外部中断（INT0 和INT1），三个定时中断（定时器0、1、2）和一个串行中断。每个中断源都可以通过置位或清除特殊寄存器IE 中的相关中断允许控制位分别使得中断源有效或无效。IE还包括一个中断允许总控制位EA，它能一次禁止所有中断。IE.6位是不可用的。对于AT89S52，IE.5位也是不能用的。用户软件不应给这些位写1。它们为AT89系列新产品预留。定时器2可以被寄存器T2CON中的TF2和EXF2的或逻辑触发。程序进入中断服务后，这些标志位都可以由硬件清0。实际上，中断服务程序必须判定是否是TF2 或EXF2激活中断，标志位也必须由软件清0。定时器0和定时器1标志位TF0 和TF1在计数溢出的那个周期的S5P2被置位。它们的值一直到下一个周期被电路捕捉下来。然而，定时器2 的标志位TF2 在计数溢出的那个周期的S2P2被置位，在同一个周期被电路捕捉下来。13 晶振特性AT89S52 单片机有一个用于构成内部振荡器的反相放大器，XTAL1 和XTAL2 分别是放大器的输入、输出端。石英晶体和陶瓷谐振器都可以用来一起构成自激振荡器。从外部时钟源驱动器件的话，XTAL2 可以不接，而从XTAL1 接入。由于外部时钟信号经过二分频触发后作为外部时钟电路输入的，所以对外部时钟信号的占空比没有其它要求，最长低电平持续时间和最少高电平持续时间等还是要符合要求的。14 空闲模式在空闲工作模式下，CPU 处于睡眠状态，而所有片上外部设备保持激活状态。这种状态可以通过软件产生。在这种状态下，片上RAM和特殊功能寄存器的内容保持不变。空闲模式可以被任一个中断或硬件复位终止。由硬件复位终止空闲模式只需两个机器周期有效复位信号，在这种情况下，片上硬件禁止访问内部RAM，而可以访问端口引脚。空闲模式被硬件复位终止后，为了防止预想不到的写端口，激活空闲模式的那一条指令的下一条指令不应该是写端口或外部存储器。15 掉电模式在掉电模式下，晶振停止工作，激活掉电模式的指令是最后一条执行指令。片上RAM和特殊功能寄存器保持原值，直到掉电模式终止。掉电模式可以通过硬件复位和外部中断退出。复位重新定义了SFR 的值，但不改变片上RAM 的值。在VCC未恢复到正常工作电压时，硬件复位不能无效，并且应保持足够长的时间以使晶振重新工作和初始化。16 程序存储器的加密位AT89S52有三个加密位不可编程（U）和可编程获得下表所示的功能。加密位1（LB1）编程后，EA 引脚的逻辑值被采样，并在复位期间加密位1（LB1）编程后，EA 引脚的逻辑值被采样，并在复位期间锁存。如果器件复位，而没有复位，将锁存一个随机值，直到复位为止。为了器件功能正常，锁存到的EA值必须和这个引脚的当前逻辑电平一致。17 Flash编程并行模式AT89S52 带有用作编程的片上Flash 存储器阵列。编程接口需要一个高电压（12V）编程使能信号，并且兼容常规的第三方*（原文：third-party，不知道对不对）Flash或EPROM编程器。AT89S52程序存储阵列采用字节式编程。1FeaturesCompatible with MCS-51 Products8K Bytes of In-System Programmable (ISP) Flash Memory Endurance: 1000 Write/Erase Cycles4.0V to 5.5V Operating RangeFully Static Operation: 0 Hz to 33 MHzThree-level Program Memory Lock256 x 8-bit Internal RAM32 Programmable I/O LinesThree 16-bit Timer/CountersEight Interrupt SourcesFull Duplex UART Serial ChannelLow-power Idle and Power-down ModesInterrupt Recovery from Power-down ModeWatchdog TimerDual Data PointerPower-off FlagDescriptionThe AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8Kbytes of in-system programmable Flash memory. The device is manufactured usingAtmels high-density nonvolatile memory technology and is compatible with the indus-try-standard 80C51 instruction set and pinout. The on-chip Flash allows the programmemory to be reprogrammed in-system or by a conventional nonvolatile memory pro-grammer. By combining a versatile 8-bit CPU with in-system programmable Flash ona monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides ahighly-flexible and cost-effective solution to many embedded control applications.The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytesof RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, asix-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator,and clock circuitry. In addition, the AT89S52 is designed with static logic for operationdown to zero frequency and supports two software selectable power saving modes.The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, andinterrupt system to continue functioning. The Power-down mode saves the RAM con-tents but freezes the oscillator, disabling all other chip functions until the next interruptor hardware reset.Rev. 1919A-07/018-bit Microcontroller with 8K Bytes In-System Programmable FlashAT89S52AT89S522TQFP1234567891011333231302928272625242344434241403938373635341213141516171819202122(MOSI) P1.5(MISO) P1.6(SCK) P1.7RST(RXD) P3.0NC(TXD) P3.1(INT0) P3.2(INT1) P3.3(T0) P3.4(T1) P3.5P0.4 (AD4)P0.5 (AD5)P0.6 (AD6)P0.7 (AD7)EA/VPPNCALE/PROGPSENP2.7 (A15)P2.6 (A14)P2.5 (A13)P1.4P1.3P1.2P1.1 (T2 EX)P1.0 (T2)NCVCCP0.0 (AD0)P0.1 (AD1)P0.2 (AD2)P0.3 (AD3)(WR) P3.6(RD) P3.7XTAL2XTAL1GNDGND(A8) P2.0(A9) P2.1(A10) P2.2(A11) P2.3(A12) P2.4PLCC78910111213141516173938373635343332313029(MOSI) P1.5(MISO) P1.6(SCK) P1.7RST(RXD) P3.0NC(TXD) P3.1(INT0) P3.2(INT1) P3.3(T0) P3.4(T1) P3.5P0.4 (AD4)P0.5 (AD5)P0.6 (AD6)P0.7 (AD7)EA/VPPNCALE/PROGPSENP2.7 (A15)P2.6 (A14)P2.5 (A13)65432144434241401819202122232425262728(WR) P3.6(RD) P3.7XTAL2XTAL1GNDNC(A8) P2.0(A9) P2.1(A10) P2.2(A11) P2.3(A12) P2.4P1.4 P1.3P1.2P1.1 (T2 EX)P1.0 (T2)NCVCCP0.0 (AD0)P0.1 (AD1)P0.2 (AD2)P0.3 (AD3)Pin ConfigurationsPDIP12345678910111213141516171819204039383736353433323130292827262524232221(T2) P1.0(T2 EX) P1.1P1.2P1.3P1.4(MOSI) P1.5(MISO) P1.6(SCK) P1.7RST(RXD) P3.0(TXD) P3.1(INT0) P3.2(INT1) P3.3(T0) P3.4(T1) P3.5(WR) P3.6(RD) P3.7XTAL2XTAL1GNDVCCP0.0 (AD0)P0.1 (AD1)P0.2 (AD2)P0.3 (AD3)P0.4 (AD4)P0.5 (AD5)P0.6 (AD6)P0.7 (AD7)EA/VPPALE/PROGPSENP2.7 (A15)P2.6 (A14)P2.5 (A13)P2.4 (A12)P2.3 (A11)P2.2 (A10)P2.1 (A9)P2.0 (A8)AT89S523Block DiagramPORT 2 DRIVERSPORT 2LATCHP2.0 - P2.7FLASHPORT 0LATCHRAMPROGRAMADDRESSREGISTERBUFFERPCINCREMENTERPROGRAMCOUNTERDUAL DPTRINSTRUCTIONREGISTERBREGISTERINTERRUPT, SERIAL PORT,AND TIMER BLOCKSSTACKPOINTERACCTMP2TMP1ALUPSWTIMINGANDCONTROLPORT 1 DRIVERSP1.0 - P1.7PORT 3LATCHPORT 3 DRIVERSP3.0 - P3.7OSCGNDVCCPSENALE/PROGEA / VPPRSTRAM ADDR.REGISTERPORT 0 DRIVERSP0.0 - P0.7PORT 1LATCHWATCHDOGISPPORTPROGRAMLOGICAT89S524Pin DescriptionVCCSupply voltage.GNDGround.Port 0Port 0 is an 8-bit open drain bidirectional I/O port. As anoutput port, each pin can sink eight TTL inputs. When 1sare written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to externalprogram and data memory. In this mode, P0 has internalpullups.Port 0 also receives the code bytes during Flash program-ming and outputs the code bytes during program verifica-tion. External pullups are required during programverification. Port 1Port 1 is an 8-bit bidirectional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins, they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will sourcecurrent (IIL) because of the internal pullups. In addition, P1.0 and P1.1 can be configured to be thetimer/counter 2 external count input (P1.0/T2) and thetimer/counter 2 trigger input (P1.1/T2EX), respectively, asshown in the following table.Port 1 also receives the low-order address bytes duringFlash programming and verification.Port 2Port 2 is an 8-bit bidirectional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins, they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 2 pins that are externally being pulled low will sourcecurrent (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetchesfrom external program memory and during accesses toexternal data memory that use 16-bit addresses (MOVX DPTR). In this application, Port 2 uses strong internal pul-lups when emitting 1s. During accesses to external datamemory that use 8-bit addresses (MOVX RI), Port 2emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and somecontrol signals during Flash programming and verification.Port 3Port 3 is an 8-bit bidirectional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins, they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will sourcecurrent (IIL) because of the pullups.Port 3 also serves the functions of various special featuresof the AT89S52, as shown in the following table.Port 3 also receives some control signals for Flash pro-gramming and verification.RSTReset input. A high on this pin for two machine cycles whilethe oscillator is running resets the device. This pin drivesHigh for 96 oscillator periods after the Watchdog times out.The DISRTO bit in SFR AUXR (address 8EH) can be usedto disable this feature. In the default state of bit DISRTO,the RESET HIGH out feature is enabled.ALE/PROGAddress Latch Enable (ALE) is an output pulse for latchingthe low byte of the address during accesses to externalmemory. This pin is also the program pulse input (PROG)during Flash programming. In normal operation, ALE is emitted at a constant rate of1/6 the oscillator frequency and may be used for externaltiming or clocking purposes. Note, however, that oneALE pulse is skipped during each access to external datamemory. If desired, ALE operation can be disabled by setting bit 0 ofSFR location 8EH. With the bit set, ALE is active only dur-ing a MOVX or MOVC instruction. Otherwise, the pin isPort PinAlternate FunctionsP1.0T2 (external count input to Timer/Counter 2), clock-outP1.1T2EX (Timer/Counter 2 capture/reload trigger and direction control)P1.5MOSI (used for In-System Programming)P1.6MISO (used for In-System Programming)P1.7SCK (used for In-System Programming)Port PinAlternate FunctionsP3.0RXD (serial input port)P3.1TXD (serial output port)P3.2INT0 (external interrupt 0)P3.3INT1 (external interrupt 1)P3.4T0 (timer 0 external input)P3.5T1 (timer 1 external input)P3.6WR (external data memory write strobe)P3.7RD (external data memory read strobe)AT89S525weakly pulled high. Setting the ALE-disable bit has noeffect if the microcontroller is in external execution mode.PSENProgram Store Enable (PSEN) is the read strobe to exter-nal program memory. When the AT89S52 is executing code from external pro-gram memory, PSEN is activated twice each machinecycle, except that two PSEN activations are skipped duringeach access to external data memory. EA/VPPExternal Access Enable. EA must be strapped to GND inorder to enable the device to fetch code from external pro-gram memory locations starting at 0000H up to FFFFH.Note, however, that if lock bit 1 is programmed, EA will beinternally latched on reset. EA should be strapped to VCC for internal program execu-tions.This pin also receives the 12-volt programming enable volt-age (VPP) during Flash programming.XTAL1Input to the inverting oscillator amplifier and input to theinternal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Table 1. AT89S52 SFR Map and Reset Values0F8H0FFH0F0HB000000000F7H0E8H0EFH0E0HACC000000000E7H0D8H0DFH0D0HPSW000000000D7H0C8HT2CON00000000T2MODXXXXXX00RCAP2L00000000RCAP2H00000000TL200000000TH2000000000CFH0C0H0C7H0B8HIPXX0000000BFH0B0HP3111111110B7H0A8HIE0X0000000AFH0A0HP211111111AUXR1XXXXXXX0WDTRSTXXXXXXXX0A7H98HSCON00000000SBUFXXXXXXXX9FH90HP11111111197H88HTCON00000000TMOD00000000TL000000000TL100000000TH000000000TH100000000AUXRXXX00XX08FH80HP011111111SP00000111DP0L00000000DP0H00000000DP1L00000000DP1H00000000PCON0XXX000087HAT89S526Special Function RegistersA map of the on-chip memory area called the Special Func-tion Register (SFR) space is shown in Table 1.Note that not all of the addresses are occupied, and unoc-cupied addresses may not be implemented on the chip.Read accesses to these addresses will in general returnrandom data, and write accesses will have an indetermi-nate effect.User software should not write 1s to these unlisted loca-tions, since they may be used in future products to invokenew features. In that case, the reset or inactive values ofthe new bits will always be 0.Timer 2 Registers: Control and status bits are contained inregisters T2CON (shown in Table 2) and T2MOD (shown inTable 3) for Timer 2. The register pair (RCAP2H, RCAP2L)are the Capture/Reload registers for Timer 2 in 16-bit cap-ture mode or 16-bit auto-reload mode.Interrupt Registers: The individual interrupt enable bitsare in the IE register. Two priorities can be set for each ofthe six interrupt sources in the IP register.Table 2. T2CON Timer/Counter 2 Control RegisterT2CON Address = 0C8HReset Value = 0000 0000BBit AddressableBitTF2EXF2RCLKTCLKEXEN2TR2C/T2CP/RL276543210SymbolFunctionTF2Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK = 1 or TCLK = 1.EXF2Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).RCLKReceive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.TCLKTransmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.EXEN2Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.TR2Start/Stop control for Timer 2. TR2 = 1 starts the timer.C/T2Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge triggered).CP/RL2Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.AT89S527Dual Data Pointer Registers: To facilitate accessing bothinternal and external data memory, two banks of 16-bitData Pointer Registers are provided: DP0 at SFR addresslocations 82H-83H and DP1 at 84H-85H. Bit DPS = 0in SFR AUXR1 selects DP0 and DPS = 1 selects DP1.The user should always initialize the DPS bit to theappropriate value before accessing the respective DataPointer Register.Power Off Flag: The Power Off Flag (POF) is located at bit4 (PCON.4) in the PCON SFR. POF is set to “1” duringpower up. It can be set and rest under software control andis not affected by reset.Table 3a. AUXR: Auxiliary RegisterAUXRAddress = 8EHReset Value = XXX00XX0BNot Bit AddressableWDIDLEDISRTODISALEBit76543210Reserved for future expansionDISALEDisable/Enable ALEDISALEOperating Mode0ALE is emitted at a constant rate of 1/6 the oscillator frequency1ALE is active only during a MOVX or MOVC instructionDISRTODisable/Enable Reset outDISRTO0Reset pin is driven High after WDT times out1Reset pin is input onlyWDIDLEDisable/Enable WDT in IDLE modeWDIDLE0WDT continues to count in IDLE mode1WDT halts counting in IDLE modeTable 3b. AUXR1: Auxiliary Register 1AUXR1Address = A2HReset Value = XXXXXXX0BNot Bit AddressableDPSBit76543210Reserved for future expansionDPSData Pointer Register SelectDPS0Selects DPTR Registers DP0L, DP0H1Selects DPTR Registers DP1L, DP1HAT89S528Memory OrganizationMCS-51 devices have a separate address space for Pro-gram and Data Memory. Up to 64K bytes each of externalProgram and Data Memory can be addressed.Program MemoryIf the EA pin is connected to GND, all program fetches aredirected to external memory.On the AT89S52, if EA is connected to VCC, programfetches to addresses 0000H through 1FFFH are directed tointernal memory and fetches to addresses 2000H throughFFFFH are to external memory.Data MemoryThe AT89S52 implements 256 bytes of on-chip RAM. Theupper 128 bytes occupy a parallel address space to theSpecial Function Registers. This means that the upper 128bytes have the same addresses as the SFR space but arephysically separate from SFR space.When an instruction accesses an internal location aboveaddress 7FH, the address mode used in the instructionspecifies whether the CPU accesses the upper 128 bytesof RAM or the SFR space. Instructions which use directaddressing access of the SFR space.For example, the following direct addressing instructionaccesses the SFR at location 0A0H (which is P2).MOV 0A0H, #dataInstructions that use indirect addressing access the upper128 bytes of RAM. For example, the following indirectaddressing instruction, where R0 contains 0A0H, accessesthe data byte at address 0A0H, rather than P2 (whoseaddress is 0A0H).MOV R0, #dataNote that stack operations are examples of indirectaddressing, so the upper 128 bytes of data RAM are avail-able as stack space.AT89S529Watchdog Timer (One-time Enabled with Reset-out)The WDT is intended as a recovery method in situationswhere the CPU may be subjected to software upsets. TheWDT consists of a 13-bit counter and the Watchdog TimerReset (WDTRST) SFR. The WDT is defaulted to disablefrom exiting reset. To enable the WDT, a user must write01EH and 0E1H in sequence to the WDTRST register(SFR location 0A6H). When the WDT is enabled, it willincrement every machine cycle while the oscillator is run-ning. The WDT timeout period is dependent on the externalclock frequency. There is no way to disable the WDTexcept through reset (either hardware reset or WDT over-flow reset). When WDT overflows, it will drive an outputRESET HIGH pulse at the RST pin.Using the WDTTo enable the WDT, a user must write 01EH and 0E1H insequence to the WDTRST register (SFR location 0A6H).When the WDT is enabled, the user needs to service it bywriting 01EH and 0E1H to WDTRST to avoid a WDT over-flow. The 13-bit counter overflows when it reaches 8191(1FFFH), and this will reset the device. When the WDT isenabled, it will increment every machine cycle while theoscillator is running. This means the user must reset theWDT at least every 8191 machine cycles. To reset theWDT the user must write 01EH and 0E1H to WDTRST.WDTRST is a write-only register. The WDT counter cannotbe read or written. When WDT overflows, it will generate anoutput RESET pulse at the RST pin. The RESET pulseduration is 96xTOSC, where TOSC=1/FOSC. To make thebest use of the WDT, it should be serviced in those sec-tions of code that will periodically be executed within thetime required to prevent a WDT reset.WDT During Power-down and IdleIn Power-down mode the oscillator stops, which means theWDT also stops. While in Power-down mode, the userdoes not need to service the WDT. There are two methodsof exiting Power-down mode: by a hardware reset or via alevel-activated external interrupt which is enabled prior toentering Power-down mode. When Power-down is exitedwith hardware reset, servicing the WDT should occur as itnormally does whenever the AT89S52 is reset. ExitingPower-down with an interrupt is significantly different. Theinterrupt is held low long enough for the oscillator to stabi-lize. When the interrupt is brought high, the interrupt isserviced. To prevent the WDT from resetting the devicewhile the interrupt pin is held low, the WDT is not starteduntil the interrupt is pulled high. It is suggested that theWDT be reset during the interrupt service for the interruptused to exit Power-down mode.To ensure that the WDT does not overflow within a fewstates of exiting Power-down, it is best to reset the WDTjust before entering Power-down mode.Before going into the IDLE mode, the WDIDLE bit in SFRAUXR is used to determine whether the WDT continues tocount if enabled. The WDT keeps counting during IDLE(WDIDLE bit = 0) as the default state. To prevent the WDTfrom resetting the AT89S52 while in IDLE mode, the usershould always set up a timer that will periodically exit IDLE,service the WDT, and reenter IDLE mode.With WDIDLE bit enabled, the WDT will stop to count inIDLE mode and resumes the count upon exit from IDLE.UARTThe UART in the AT89S52 operates the same way as theUART in the AT89C51 and AT89C52. For further informa-tion on the UART operation, refer to the ATMEL Web site(). From the home page, select Prod-ucts, then 8051-Architecture Flash Microcontroller, thenProduct Overview. Timer 0 and 1Timer 0 and Timer 1 in the AT89S52 operate the same wayas Timer 0 and Timer 1 in the AT89C51 and AT89C52. Forfurther information on the timers operation, refer to theATMEL Web site (). From the homepage, select Products, then 8051-Architecture FlashMicrocontroller, then Product Overview. Timer 2Timer 2 is a 16-bit Timer/Counter that can operate as eithera timer or an event counter. The type of operation isselected by bit C/T2 in the SFR T2CON (shown in Table 2).Timer 2 has three operating modes: capture, auto-reload(up or down counting), and baud rate generator. Themodes are selected by bits in T2CON, as shown in Table 3.Timer 2 consists of two 8-bit registers, TH2 and TL2. In theTimer function, the TL2 register is incremented everymachine cycle. Since a machine cycle consists of 12 oscil-lator periods, the count rate is 1/12 of the oscillatorfrequency.Table 3. Timer 2 Operating ModesRCLK +TCLKCP/RL2TR2MODE00116-bit Auto-reload01116-bit Capture1X1Baud Rate GeneratorXX0(Off)AT89S5210In the Counter function, the register is incremented inresponse to a 1-to-0 transition at its corresponding externalinput pin, T2. In this function, the external input is sampledduring S5P2 of every machine cycle. When the samplesshow a high in one cycle and a low in the next cycle, thecount is incremented. The new count value appears in theregister during S3P1 of the cycle following the one in whichthe transition was detected. Since two machine cycles (24oscillator periods) are required to recognize a 1-to-0 transi-tion, the maximum count rate is 1/24 of the oscillator fre-quency. To ensure that a given level is sampled at leastonce before it changes, the level should be held for at leastone full machine cycle.Capture ModeIn the capture mode, two options are selected by bitEXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timeror counter which upon overflow sets bit TF2 in T2CON.This bit can then be used to generate an interrupt. IfEXEN2 = 1, Timer 2 performs the same operation, but a 1-to-0 transition at external input T2EX also causes thecurrent value in TH2 and TL2 to be captured into RCAP2Hand RCAP2L, respectively. In addition, the transition atT2EX causes bit EXF2 in T2CON to be set. The EXF2 bit,like TF2, can generate an interrupt. The capture mode isillustrated in Figure 5.Auto-reload (Up or Down Counter)Timer 2 can be programmed to count up or down whenconfigured in its 16-bit auto-reload mode. This feature isinvoked by the DCEN (Down Counter Enable) bit located inthe SFR T2MOD (see Table 4). Upon reset, the DCEN bitis set to 0 so that timer 2 will default to count up. WhenDCEN is set, Timer 2 can count up or down, depending onthe value of the T2EX pin.Figure 5. Timer in Capture ModeFigure 6 shows Timer 2 automatically counting up whenDCEN=0. In this mode, two options are selected by bitEXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to0FFFFH and then sets the TF2 bit upon overflow. Theoverflow also causes the timer registers to be reloaded withthe 16-bit value in RCAP2H and RCAP2L. The values inTimer in Capture ModeRCAP2H and RCAP2L are presetby software. If EXEN2 = 1, a 16-bit reload can be triggeredeither by an overflow or by a 1-to-0 transition at externalinput T2EX. This transition also sets the EXF2 bit. Both theTF2 and EXF2 bits can generate an interrupt if enabled.Setting the DCEN bit enables Timer 2 to count up or down,as shown in Figure 6. In this mode, the T2EX pin controlsthe direction of the count. A logic 1 at T2EX makes Timer 2count up. The timer will overflow at 0FFFFH and set theTF2 bit. This overflow also causes the 16-bit value inRCAP2H and RCAP2L to be reloaded into the timer regis-ters, TH2 and TL2, respectively.A logic 0 at T2EX makes Timer 2 count down. The timerunderflows when TH2 and TL2 equal the values stored inRCAP2H and RCAP2L. The underflow sets the TF2 bit andcauses 0FFFFH to be reloaded into the timer registers.The EXF2 bit toggles whenever Timer 2 overflows orunderflows and can be used as a 17th bit of resolution. Inthis operating mode, EXF2 does not flag an interrupt.OSCEXF2T2EX PINT2 PINTR2EXEN2C/T2 = 0C/T2 = 1CONTROLCAPTUREOVERFLOWCONTROLTRANSITIONDETECTORTIMER 2INTERRUPT12RCAP2LRCAP2HTH2TL2TF2AT89S5211Figure 6. Timer 2 Auto Reload Mode (DCEN = 0)Table 4. T2MOD Timer 2 Mode Control RegisterOSCEXF2TF2T2EX PINT2 PINTR2EXEN2C/T2 = 0C/T2 = 1CONTROLRELOADCONTROLTRANSITIONDETECTORTIMER 2INTERRUPT12RCAP2LRCAP2HTH2TL2OVERFLOWT2MOD Address = 0C9HReset Value = XXXX XX00BNot Bit AddressableT2OEDCENBit76543210Symbol FunctionNot implemented, reserved for futureT2OETimer 2 Output Enable bitDCENWhen set, this bit allows Timer 2 to be configured as an up/down counterAT89S5212Figure 7. Timer 2 Auto Reload Mode (DCEN = 1)Figure 8. Timer 2 in Baud Rate Generator ModeOSCEXF2TF2T2EX PINCOUNTDIRECTION1=UP0=DOWNT2 PINTR2CONTROLOVERFLOWTOGGLETIMER 2INTERRUPT12RCAP2LRCAP2H0FFH0FFHTH2TL2C/T2 = 0C/T2 = 1(DOWN COUNTING RELOAD VALUE)(UP COUNTING RELOAD VALUE)OSCSMOD1RCLKTCLKRxCLOCKTxCLOCKT2EX PINT2 PINTR2CONTROL111000TIMER 1 OVERFLOWNOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12TIMER 2INTERRUPT221616RCAP2LRCAP2HTH2TL2C/T2 = 0C/T2 = 1EXF2CONTROLTRANSITIONDETECTOREXEN2AT89S5213Baud Rate GeneratorTimer 2 is selected as the baud rate generator by settingTCLK and/or RCLK in T2CON (Table 2). Note that thebaud rates for transmit and receive can be different if Timer2 is used for the receiver or transmitter and Timer 1 is usedfor the other function. Setting RCLK and/or TCLK putsTimer 2 into its baud rate generator mode, as shown in Fig-ure 8.The baud rate generator mode is similar to the auto-reloadmode, in that a rollover in TH2 causes the Timer 2 registersto be reloaded with the 16-bit value in registers RCAP2Hand RCAP2L, which are preset by software.The baud rates in Modes 1 and 3 are determined by Timer2s overflow rate according to the following equation.The Timer can be configured for either timer or counteroperation. In most applications, it is configured for timeroperation (CP/T2 = 0). The timer operation is different forTimer 2 when it is used as a baud rate generator. Normally,as a timer, it increments every machine cycle (at 1/12 theoscillator frequency). As a baud rate generator, however, itincrements every state time (at 1/2 the oscillator fre-quency). The baud rate formula is given below.where (RCAP2H, RCAP2L) is the content of RCAP2H andRCAP2L taken as a 16-bit unsigned integer.Timer 2 as a baud rate generator is shown in Figure 8. Thisfigure is valid only if RCLK or TCLK = 1 in T2CON. Notethat a rollover in TH2 does not set TF2 and will not gener-ate an interrupt. Note too, that if EXEN2 is set, a 1-to-0transition in T2EX will set EXF2 but will not cause a reloadfrom (RCAP2H, RCAP2L) to (TH2, TL2). Thus, when Timer2 is in use as a baud rate generator, T2EX can be used asan extra external interrupt.Note that when Timer 2 is running (TR2 = 1) as a timer inthe baud rate generator mode, TH2 or TL2 should not beread from or written to. Under these conditions, the Timer isincremented every state time, and the results of a read orwrite may not be accurate. The RCAP2 registers may beread but should not be written to, because a write mightoverlap a reload and cause write and/or reload errors. Thetimer should be turned off (clear TR2) before accessing theTimer 2 or RCAP2 registers.Figure 9. Timer 2 in Clock-Out ModeModes 1 and 3 Baud Rates Timer 2 Overflow Rate16 -=Modes 1 and 3Baud Rate -Oscillator Frequency32 x 65536-RCAP2H,RCAP2L) -=OSCEXF2P1.0(T2)P1.1(T2EX)TR2EXEN2C/T2 BITTRANSITIONDETECTORTIMER 2INTERRUPTT2OE (T2MOD.1)2TL2(8-BITS)RCAP2LRCAP2HTH2(8-BITS)2AT89S5214Programmable Clock OutA 50% duty cycle clock can be programmed to come out onP1.0, as shown in Figure 9. This pin, besides being a regu-lar I/O pin, has two alternate functions. It can be pro-grammed to input the external clock for Timer/Counter 2 orto output a 50% duty cycle clock ranging from 61 Hz to 4MHz at a 16 MHz operating frequency.To configure the Timer/Counter 2 as a clock generator, bitC/T2 (T2CON.1) must be cleared and bit T2OE (T2MOD.1)must be set. Bit TR2 (T2CON.2) starts and stops the timer.The clock-out frequency depends on the oscillator fre-quency and the reload value of Timer 2 capture registers(RCAP2H, RCAP2L), as shown in the following equation.In the clock-out mode, Timer 2 roll-overs will not generatean interrupt. This behavior is similar to when Timer 2 isused as a baud-rate generator. It is possible to use Timer 2as a baud-rate generator and a clock generator simulta-neously. Note, however, that the baud-rate and clock-outfrequencies cannot be determined independently from oneanother since they both use RCAP2H and RCAP2L.InterruptsThe AT89S52 has a total of six interrupt vectors: two exter-nal interrupts (INT0 and INT1), three timer interrupts (Tim-ers 0, 1, and 2), and the serial port interrupt. Theseinterrupts are all shown in Figure 10.Each of these interrupt sources can be individually enabledor disabled by setting or clearing a bit in Special FunctionRegister IE. IE also contains a global disable bit, EA, whichdisables all interrupts at once.Note that Table 5 shows that bit position IE.6 is unimple-mented. In the AT89S52, bit position IE.5 is also unimple-mented. User software should not write 1s to these bitpositions, since they may be used in future AT89 products.Timer 2 interrupt is generated by the logical OR of bits TF2and EXF2 in register T2CON. Neither of these flags iscleared by hardware when the service routine is vectoredto. In fact, the service routine may have to determinewhether it was TF2 or EXF2 that generated the interrupt,and that bit will have to be cleared in software.The Timer 0 and Timer 1 flags, TF0 and TF1, are set atS5P2 of the cycle in which the timers overflow. The valuesare then polled by the circuitry in the next cycle. However,the Timer 2 flag, TF2, is set at S2P2 and is polled in thesame cycle in which the timer overflows.Table 5. Interrupt Enable (IE) RegisterFigure 10. Interrupt SourcesClock-Out FrequencyOscillator Frequency4 x 65536-(RCAP2H,RCAP2L) -= (MSB) (LSB)EAET2ESET1EX1ET0EX0 Enable Bit = 1 enables the interrupt. Enable Bit = 0 disables the interrupt.SymbolPositionFunctionEAIE.7Disables all interrupts. If EA = 0, no interrupt is acknowledged. If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit.IE.6Reserved.ET2IE.5Timer 2 interrupt enable bit.ESIE.4Serial Port interrupt enable bit.ET1IE.3Timer 1 interrupt enable bit.EX1IE.2External interrupt 1 enable bit.ET0IE.1Timer 0 interrupt enable bit.EX0IE.0External interrupt 0 enable bit.User software should never write 1s to unimplemented bits, because they may be used in future AT89 products.IE1IE01100TF1TF0INT1INT0TIRITF2EXF2AT89S5215Oscillator Characteristics XTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier that can be configured for use asan on-chip oscillator, as shown in Figure 11. Either a quartzcrystal or ceramic resonator may be used. To drive thedevice from an external clock source, XTAL2 should be leftunconnected while XTAL1 is driven, as shown in Figure 12.There are no requirements on the duty cycle of the externalclock signal, since the input to the internal clocking circuitryis through a divide-by-two flip-flop, but minimum and maxi-mum voltage high and low time specifications must beobserved.Idle Mode In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked bysoftware. The content of the on-chip RAM and all the spe-cial functions registers remain unchanged during thismode. The idle mode can be terminated by any enabledinterrupt or by a hardware reset. Note that when idle mode is terminated by a hardwarereset, the device normally resumes program executionfrom where it left off, up to two machine cycles before theinternal reset algorithm takes control. On-chip hardwareinhibits access to internal RAM in this event, but access tothe port pins is not inhibited. To eliminate the possibility ofan unexpected write to a port pin when idle mode is termi-nated by a reset, the instruction following the one thatinvokes idle mode should not write to a port pin or to exter-nal memory.Power-down Mode In the Power-down mode, the oscillator is stopped, and theinstruction that invokes Power-down is the last instructionexecuted. The on-chip RAM and Special Function Regis-ters retain their values until the Power-down mode is termi-nated. Exit from Power-down mode can be initiated eitherby a hardware reset or by an enabled external interrupt.Reset redefines the SFRs but does not change the on-chipRAM. The reset should not be activated before VCC isrestored to its normal operating level and must be heldactive long enough to allow the oscillator to restartand stabilize.Figure 11. Oscillator ConnectionsNote: C1, C2 = 30 pF 10 pF for Crystals= 40 pF 10 pF for Ceramic ResonatorsFigure 12. External Clock Drive Configuration C2XTAL2GNDXTAL1C1XTAL2XTAL1GNDNCEXTERNALOSCILLATORSIGNALTable 6. Status of External Pins During Idle and Power-down ModesModeProgram MemoryALEPSENPORT0PORT1PORT2PORT3IdleInternal11DataDataDataDataIdleExternal11FloatDataAddressDataPower-downInternal00DataDataDataDataPower-downExternal00FloatDataDataDataAT89S5216Program Memory Lock Bits The AT89S52 has three lock bits that can be left unpro-grammed (U) or can be programmed (P) to obtain the addi-tional features listed in the following table.When lock bit 1 is programmed, the logic level at the EA pinis sampled and latched during reset. If the device is pow-ered up without a reset, the latch initializes to a randomvalue and holds that value until reset is activated. Thelatched value of EA must agree with the current logic levelat that pin in order for the device to function properly.Programming the Flash Parallel ModeThe AT89S52 is shipped with the on-chip Flash memoryarray ready to be programmed. The programming interfaceneeds a high-voltage (12-volt) program enable signal andis compatible with conventional third-party Flash orEPROM programmers.The AT89S52 code memory array is programmed byte-by-byte.Programming Algorithm: Before programming theAT89S52, the address, data, and control signals should beset up according to the Flash programming mode table andFigures 13 and 14. To program the AT89S52, take the fol-lowing steps:1.Input the desired memory location on the address lines.2.Input the appropriate data byte on the data lines.3.Activate the correct combination of control signals. 4.Raise EA/VPP to 12V. 5.Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 50 s. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached.Data Polling: The AT89S52 features Data Polling to indi-cate the end of a byte write cycle. During a write cycle, anattempted read of the last byte written will result in the com-plement of the written data on P0.7. Once the write cyclehas been completed, true data is valid on all outputs, andthe next cycle may begin. Data Polling may begin any timeafter a write cycle has been initiated. Ready/Busy: The progress of byte programming can alsobe monitored by the RDY/BSY output signal. P3.0 is pulledlow after ALE goes high during programming to indicateBUSY. P3.0 is pulled high again when programming isdone to indicate READY.Program Verify: If lock bits LB1 and LB2 have not beenprogrammed, the programmed code data can be read backvia the address and data lines for verification. The status ofthe individual lock bits can be verified directly by readingthem back. Reading the Signature Bytes: The signature bytes areread by the same procedure as a normal verification oflocations 000H, 100H, and 200H, except that P3.6 andP3.7 must be pulled to a logic low. The values returned areas follows.(000H) = 1EH indicates manufactured by Atmel(100H) = 52H indicates 89S52(200H) = 06HChip Erase: In the parallel programming mode, a chiperase operation is initiated by using the proper combinationof control signals and by pulsing ALE/PROG low for a dura-tion of 200 ns - 500 ns.In the serial programming mode, a chip erase operation isinitiated by issuing the Chip Erase instruction. In this mode,chip erase is self-timed and takes about 500 ms.During chip erase, a serial read from any address locationwill return 00H at the data output.Programming the Flash Serial ModeThe Code memory array can be programmed using theserial ISP interface while RST is pulled to VCC. The serialinterface consists of pins SCK, MOSI (input) and MISO(output). After RST is set high, the Programming Enableinstruction needs to be executed first before other opera-tions can be executed. Before a reprogramming sequencecan occur, a Chip Erase operation is required.The Chip Erase operation turns the content of every mem-ory location in the Code array into FFH.Either an external system clock can be supplied at pinXTAL1 or a crystal needs to be connected across pinsXTAL1 and XTAL2. The maximum serial clock (SCK)Table 7. Lock Bit Protection ModesProgram Lock BitsLB1LB2LB3Protection Type1UUUNo program lock features2PUUMOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further programming of the Flash memory is disabled3PPUSame as mode 2, but verify is also disabled4PPPSame as mode 3, but external execution is also disabledAT89S5217frequency should be less than 1/16 of the crystal fre-quency. With a 33 MHz oscillator clock, the maximum SCKfrequency is 2 MHz.Serial Programming AlgorithmTo program and verify the AT89S52 in the serial program-ming mode, the following sequence is recommended:1.Power-up sequence:Apply power between VCC and GND pins.Set RST pin to “H”.If a crystal is not connected across pins XTAL1 andXTAL2, apply a 3 MHz to 33 MHz clock to XTAL1 pinand wait for at least 10 milliseconds.2.Enable serial programming by sending the Pro-gramming Enable serial instruction to pin MOSI/P1.5. The frequency of the shift clock sup-plied at pin SCK/P1.7 needs to be less than the CPU clock at XTAL1 divided by 16.3.The Code array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. The write cycle is self-timed and typically takes less than 1 ms at 5V.4.Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO/P1.6.5.At the end of a programming session, RST can be set low to commence normal device operation.Power-off sequence (if needed):Set XTAL1 to “L” (if a crystal is not used).Set RST to “L”.Turn VCC power off.Data Polling: The Data Polling feature is also available inthe serial mode. In this mode, during a write cycle anattempted read of the last byte written will result in the com-plement of the MSB of the serial output byte on MISO.Serial Programming Instruction SetThe Instruction Set for Serial Programming follows a 4-byteprotocol and is shown in Table 10.AT89S5218Programming Interface Parallel ModeEvery code byte in the Flash array can be programmed byusing the appropriate combination of control signals. Thewrite operation cycle is self-timed and once initiated, willautomatically time itself to completion.All major programming vendors offer worldwide support forthe Atmel microcontroller series. Please contact your localprogramming vendor for the appropriate software revision.Notes:1. Each PROG pulse is 200 ns - 500 ns for Chip Erase.2. Each PROG pulse is 200 ns - 500 ns for Write Code Data.3. Each PROG pulse is 200 ns - 500 ns for Write Lock Bits.4. RDY/BSY signal is output on P3.0 during programming.5. X = dont care.Figure 13. Programming the Flash Memory (Parallel Mode)Figure 14. Verifying the Flash Memory (Parallel Mode)Table 8. Flash Programming ModesModeVCCRSTPSENALE/PROGEA/VPPP2.6P2.7P3.3P3.6P3.7P0.7-0DataP2.4-0P1.7-0AddressWrite Code Data5VHL(2)12VLHHHHDINA12-8A7-0Read Code Data5VHLHHLLLHHDOUTA12-8A7-0Write Lock Bit 15VHL(3)12VHHHHHXXXWrite Lock Bit 25VHL(3)12VHHHLLXXXWrite Lock Bit 35VHL(3)12VHLHHLXXXRead Lock Bits1, 2, 35VHLHHHHLHLP0.2,P0.3,P0.4 XXChip Erase5VHL(1)12VHLHLLXXXRead Atmel ID5VHLHHLLLLL1EHX 000000HRead Device ID5VHLHHLLLLL52HX 000100HRead Device ID5VHLHHLLLLL06HX 001000HP1.0-P1.7P2.6P3.6P2.0 - P2.4A0 - A7ADDR.0000H/1FFFHSEE FLASHPROGRAMMINGMODES TABLE3-33 MHzP0VP2.7PGMDATAPROGV /VIHPPVIHALEP3.7XTAL2EARSTPSENXTAL1GNDVCCAT89S52P3.3P3.0RDY/BSYA8 - A12CCP1.0-P1.7P2.6P3.6P2.0 - P2.4A0 - A7ADDR.0000H/1FFFHSEE FLASHPROGRAMMINGMODES TABLE3-33 MHzP0P2.7PGM DATA(USE 10KPULLUPS)VIHVIHALEP3.7XTAL2EARSTPSENXTAL1GNDVCCAT89S52P3.3A8 - A12VCCAT89S5219Figure 15. Flash Programming and Verification Waveforms Parallel Mode Flash Programming and Verification Characteristics (Parallel Mode)TA = 20C to 30C, VCC = 4.5 to 5.5VSymbolParameterMinMaxUnitsVPPProgramming Supply Voltage11.512.5VIPPProgramming Supply Current10mAICCVCC Supply Current30mA1/tCLCLOscillator Frequency333MHztAVGLAddress Setup to PROG Low48tCLCLtGHAXAddress Hold After PROG48tCLCLtDVGLData Setup to PROG Low48tCLCLtGHDXData Hold After PROG48tCLCLtEHSHP2.7 (ENABLE) High to VPP48tCLCLtSHGLVPP Setup to PROG Low10stGHSLVPP Hold After PROG10stGLGHPROG Width0.21stAVQVAddress to Data Valid48tCLCLtELQVENABLE Low to Data Valid48tCLCLtEHQZData Float After ENABLE048tCLCLtGHBLPROG High to BUSY Low1.0stWCByte Write Cycle Time50stGLGHtGHSLtAVGLtSHGLtDVGLtGHAXtAVQVtGHDXtEHSHtELQVtWCBUSYREADYtGHBLtEHQZP1.0 - P1.7P2.0 - P2.5P3.4ALE/PROGPORT 0LOGIC 1LOGIC 0EA/VPPVPPP2.7(ENABLE)P3.0(RDY/BSY)PROGRAMMINGADDRESSVERIFICATIONADDRESSDATA INDATA OUTAT89S5220Figure 16. Flash Memory Serial DownloadingFlash Programming and Verification Waveforms Serial ModeFigure 17. Serial Programming WaveformsP1.7/SCKDATA OUTPUTINSTRUCTIONINPUTCLOCK IN3-33 MHzP1.5/MOSIVIHXTAL2RSTXTAL1GNDVCCAT89S52P1.6/MISOVCC76543210AT89S5221Notes:1. The signature bytes are not readable in Lock Bit Modes 3 and 4.2. B1 = 0, B2 = 0 Mode 1, no lock protectionB1 = 0, B2 = 1 Mode 2, lock bit 1 activatedB1 = 1, B2 = 0 Mode 3, lock bit 2 activatedB1 = 1, B1 = 1 Mode 4, lock bit 3 activatedAfter Reset signal is high, SCK should be low for at least 64system clocks before it goes high to clock in the enabledata bytes. No pulsing of Reset signal is necessary. SCKshould be no faster than 1/16 of the system clock atXTAL1.For Page Read/Write, the data always starts from byte 0 to255. After the command byte and upper address byte arelatched, each byte thereafter is treated as data until all 256bytes are shifted in/out. Then the next instruction will beready to be decoded.Table 9. Serial Programming Instruction SetInstructionInstruction FormatOperationByte 1Byte 2Byte 3Byte 4Programming Enable1010110001010011xxxxxxxxxxxxxxxx01101001 (Output)Enable Serial Programming while RST is highChip Erase10101100100xxxxxxxxxxxxxxxxxxxxxChip Erase Flash memory arrayRead Program Memory(Byte Mode)00100000xxx Read data from Program memory in the byte modeWrite Program Memory(Byte Mode)01000000xxxWrite data to Program memory in the byte modeWrite Lock Bits(2)10101100111000xxxxxxxxxxxxxxxxWrite Lock bits. See Note (2).Read Lock Bits00100100xxxxxxxxxxxxxxxxxx xxRead back current status of the lock bits (a programmed lock bit reads back as a 1)Read Signature Bytes(1)00101000xxxxxxxxxxSignature ByteRead Signature ByteRead Program Memory(Page Mode)00110000xxxByte 0Byte 1. Byte 255Read data from Program memory in the Page Mode (256 bytes)Write Program Memory(Page Mode)01010000xxxByte 0Byte 1. Byte 255Write data to Program memory in the Page Mode (256 bytes)D7D6D5D4D3D2D1D0A7A6A5A4A3A2A1A0A12A11A10A9A8B2B1A12A11A10A9A8A7A6A5A4A3A2A1A0D7D6D5D4D3D2D1D0LB3LB2LB1A5A4A3A2A1A0A12A11A10A9A8A12A11A10A9A8Each of the lock bits needs to be activated sequentially before Mode 4 can be executed.AT89S5222Serial Programming CharacteristicsFigure 18. Serial Programming TimingMOSIMISOSCKtOVSHtSHSLtSLSHtSHOXtSLIVTable 10. Serial Programming Characteristics, TA = -40C to 85C, VCC = 4.0 - 5.5V (Unless otherwise noted)SymbolParameterMinTypMaxUnits1/tCLCLOscillator Frequency033MHztCLCLOscillator Period30nstSHSLSCK Pulse Width High2 tCLCLnstSLSHSCK Pulse Width Low2 tCLCLnstOVSHMOSI Setup to SCK HightCLCLnstSHOXMOSI Hold after SCK High2 tCLCLnstSLIVSCK Low to MISO Valid101632nstERASEChip Erase Instruction Cycle Time500mstSWCSerial Byte Write Cycle Time64 tCLCL + 400sAT89S5223Notes:1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:Maximum IOL per port pin: 10 mAMaximum IOL per 8-bit port:Port 0: 26 mA Ports 1, 2, 3: 15 mAMaximum total IOL for all output pins: 71 mAIf IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.2. Minimum VCC for Power-down is 2V.Absolute Maximum Ratings*Operating Temperature -55C to +125C*NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Storage Temperature -65C to +150CVoltage on Any Pinwith Respect to Ground-1.0V to +7.0VMaximum Operating Voltage 6.6VDC Output Current 15.0 mADC CharacteristicsThe values shown in this table are valid for TA = -40C to 85C and VCC = 4.0V to 5.5V, unless otherwise noted.SymbolParameterConditionMinMaxUnitsVILInput Low Voltage(Except EA)-0.50.2 VCC-0.1VVIL1Input Low Voltage (EA)-0.50.2 VCC-0.3VVIHInput High Voltage(Except XTAL1, RST)0.2 VCC+0.9VCC+0.5VVIH1Input High Voltage(XTAL1, RST)0.7 VCCVCC+0.5VVOLOutput Low Voltage(1) (Ports 1,2,3)IOL = 1.6 mA0.45VVOL1Output Low Voltage(1)(Port 0, ALE, PSEN)IOL = 3.2 mA0.45VVOHOutput High Voltage(Ports 1,2,3, ALE, PSEN)IOH = -60 A, VCC = 5V 10%2.4VIOH = -25 A0.75 VCCVIOH = -10 A0.9 VCCVVOH1Output High Voltage(Port 0 in External Bus Mode)IOH = -800 A, VCC = 5V 10%2.4VIOH = -300 A0.75 VCCVIOH = -80 A0.9 VCCVIILLogical 0 Input Current (Ports 1,2,3)VIN = 0.45V -50AITLLogical 1 to 0 Transition Current (Ports 1,2,3)VIN = 2V, VCC = 5V 10% -650AILIInput Leakage Current (Port 0, EA)0.45 VIN VCC10ARRSTReset Pulldown Resistor1030KCIOPin CapacitanceTest Freq. = 1 MHz, TA = 25C10pFICCPower Supply CurrentActive Mode, 12 MHz25mAIdle Mode, 12 MHz6.5mAPower-down Mode(1)VCC = 5.5V 50AAT89S5224AC Characteristics Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all otheroutputs = 80 pF.External Program and Data Memory CharacteristicsSymbolParameter12 MHz OscillatorVariable OscillatorUnitsMinMaxMinMax1/tCLCLOscillator Frequency033MHztLHLLALE Pulse Width1272tCLCL-40nstAVLLAddress Valid to ALE Low43tCLCL-25nstLLAXAddress Hold After ALE Low48tCLCL-25nstLLIVALE Low to Valid Instruction In2334tCLCL-65nstLLPLALE Low to PSEN Low43tCLCL-25nstPLPHPSEN Pulse Width2053tCLCL-45nstPLIVPSEN Low to Valid Instruction In1453tCLCL-60nstPXIXInput Instruction Hold After PSEN00nstPXIZInput Instruction Float After PSEN59tCLCL-25nstPXAVPSEN to Address Valid75tCLCL-8nstAVIVAddress to Valid Instruction In3125tCLCL-80nstPLAZPSEN Low to Address Floa