基于AT89S52单片机和DS1302的电子万年历设计资料
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天津工程师范学院03级学生毕业设计中期报告系别自动化系班级自0302学生姓名许宁指导教师赵学玲课题名称：电子万年历设计简述开题以来所做的具体工作、取得的进展及下一步主要工作：2006-2007学年（1）第一学期（11.15-12.15） 通过收集整理资料，认真阅读资料，对电子万年历设计有个整体的了解。然后设计方案，对所设计的方案进行分析论证，记下各方案的优缺点，选择比较可取的方案而且电路所用到的器件必须是性价比较高、在市场上比较容易买到的。 方案选择完毕后，针对该方案看懂电路的原理，分析整个系统的流程并用框图表示出来，构造出大体框架。然后再分析每个模块电路的具体作用以及可能出现的问题。 根据方案选择出元器件后，查找各器件的管脚图及其用法，根据公式计算所用到器件的型号及大小，列元件清单，购买器件。（2）第二学期（4.5-4.20、4.20-5.10） 第一阶段：根据上学期整理的资料开始焊接电路，构思整个系统的信号流程和布局工作。对各个模块进行编程，不断修改程序以达到预期要实现的功能。 第二阶段：完成所有模块的编程及调试任务，接着统调，在统调的过程中注意电源的正负极以及各模块间的信号是否接好、是否共地、芯片是否装反等问题。（3）取得的进展各模块电路已基本实现，获得的指标与预期的差距不大。（4）下一步的主要工作 尽力解决统调过程中出现的问题，分析产生各种现象的原因。 记下调试过程中各个指标。 整理资料，准备着手写论文。 回想设计的整个过程，准备答辩。 学生签字： 年 月 日指导教师的建议与要求： 指导教师签字： 年 月 日注：本表格同毕业设计（论文）一同装订成册，由所在单位归档保存。天津工程师范学院03级学生毕业设计中期报告系别自动化系班级自0302学生姓名许宁指导教师赵学玲课题名称：电子万年历设计简述开题以来所做的具体工作、取得的进展及下一步主要工作：2006-2007学年（1）第一学期（11.15-12.15） 通过收集整理资料，认真阅读资料，对电子万年历设计有个整体的了解。然后设计方案，对所设计的方案进行分析论证，记下各方案的优缺点，选择比较可取的方案而且电路所用到的器件必须是性价比较高、在市场上比较容易买到的。 方案选择完毕后，针对该方案看懂电路的原理，分析整个系统的流程并用框图表示出来，构造出大体框架。然后再分析每个模块电路的具体作用以及可能出现的问题。 根据方案选择出元器件后，查找各器件的管脚图及其用法，根据公式计算所用到器件的型号及大小，列元件清单，购买器件。（2）第二学期（4.5-4.20、4.20-5.10） 第一阶段：根据上学期整理的资料开始焊接电路，构思整个系统的信号流程和布局工作。对各个模块进行编程，不断修改程序以达到预期要实现的功能。 第二阶段：完成所有模块的编程及调试任务，接着统调，在统调的过程中注意电源的正负极以及各模块间的信号是否接好、是否共地、芯片是否装反等问题。（3）取得的进展各模块电路已基本实现，获得的指标与预期的差距不大。（4）下一步的主要工作 尽力解决统调过程中出现的问题，分析产生各种现象的原因。 记下调试过程中各个指标。 整理资料，准备着手写论文。 回想设计的整个过程，准备答辩。 学生签字： 年 月 日指导教师的建议与要求： 指导教师签字： 年 月 日注：本表格同毕业设计（论文）一同装订成册，由所在单位归档保存。天津工程师范学院毕业设计任务书 2006 年11月 4日题 目（包括副标题）电子万年历设计教师姓名赵学玲系 别自动化工程系职 称讲师学生姓名许宁班 级自0302班 学 号15课题成果形式论文 设计说明书 实物 软件 其它1毕业设计（论文）课题任务的内容和要求（如原始数据、技术要求、工作要求等）：1、毕业设计的主要内容：1） 设计并制作电子万年历2） 完成相关的技术文档和毕业设计论文2、毕业设计的主要技术指标1） 显示阳历年、月、日、时、分、秒、星期及阴历年、月、日，能标明是否闰月2） 用液晶进行显示，用按键进行调整3） 实现闹铃功能3、毕业设计的基本要求：1） 完成电子系统的方案设计，技术调试，硬件实现2） 完成技术指标中的各项要求为优秀2毕业设计（论文）工作进度计划：周 次工作内容第一周、第二周第三周，第四周第五周，第六周第七、八、九周第十、十一、十二周查找资料、设计电路方案论证、购买元件制作电路、程序设计系统制作、整体调试总结论文、准备答辩 教研室（学科组）主任签字： 天津工程师范学院毕业设计任务书 2006 年11月 4日题 目（包括副标题）电子万年历设计教师姓名赵学玲系 别自动化工程系职 称讲师学生姓名许宁班 级自0302班 学 号15课题成果形式论文 设计说明书 实物 软件 其它1毕业设计（论文）课题任务的内容和要求（如原始数据、技术要求、工作要求等）：1、毕业设计的主要内容：1） 设计并制作电子万年历2） 完成相关的技术文档和毕业设计论文2、毕业设计的主要技术指标1） 显示阳历年、月、日、时、分、秒、星期及阴历年、月、日，能标明是否闰月2） 用液晶进行显示，用按键进行调整3） 实现闹铃功能3、毕业设计的基本要求：1） 完成电子系统的方案设计，技术调试，硬件实现2） 完成技术指标中的各项要求为优秀2毕业设计（论文）工作进度计划：周 次工作内容第一周、第二周第三周，第四周第五周，第六周第七、八、九周第十、十一、十二周查找资料、设计电路方案论证、购买元件制作电路、程序设计系统制作、整体调试总结论文、准备答辩 教研室（学科组）主任签字： 英文翻译OverviewThe 8051 family of micro controllers is based on an architecture which is highly optimized for embedded control systems. It is used in a wide variety of applications from military equipment to automobiles to the keyboard on your PC. Second only to the Motorola 68HC11 in eight bit processors sales, the 8051 family of microcontrollers is available in a wide array of variations from manufacturers such as Intel, Philips, and Siemens. These manufacturers have added numerous features and peripherals to the 8051 such as I2C interfaces, analog to digital converters, watchdog timers, and pulse width modulated outputs. Variations of the 8051 with clock speeds up to 40MHz and voltage requirements down to 1.5 volts are available. This wide range of parts based on one core makes the 8051 family an excellent choice as the base architecture for a companys entire line of products since it can perform many functions and developers will only have to learn this one platform.The basic architecture consists of the following features:1 an eight bit ALU2 32 descrete I/O pins (4 groups of 8) which can be individually accessed3 two 16 bit timer/counters4 full duplex UART5 6 interrupt sources with 2 priority levels6 128 bytes of on board RAM7 separate 64K byte address spaces for DATA and CODE memoryOne 8051 processor cycle consists of twelve oscillator periods. Each of the twelve oscillator periods is used for a special function by the 8051 core such as op code fetches and samples of the interrupt daisy chain for pending interrupts. The time required for any 8051 instruction can be computed by dividing the clock frequency by 12, inverting that result and multiplying it by the number of processor cycles required by the instruction in question. Therefore, if you have a system which is using an 11.059MHz clock, you can compute the number of instructions per second by dividing this value by 12. This gives an instruction frequency of 921583 instructions per second. Inverting this will provide the amount of time taken by each instruction cycle (1.085 microseconds).Memory OrganizationThe 8051 architecture provides the user with three physically distinct memory spaces which can be seen in Figure A - 1. Each memory space consists of contiguous addresses from 0 to the maximum size, in bytes, of the memory space. Address overlaps are resolved by utilizing instructions which refer specifically to a given address space. The three memory spaces function as described below.The CODE SpaceThe first memory space is the CODE segment in which the executable program resides. This segment can be up to 64K (since it is addressed by 16 address lines) . The processor treats this segment as read only and will generate signals appropriate to access a memory device such as an EPROM. However, this does not mean that the CODE segment must be implemented using an EPROM. Many embedded systems these days are using EEPROM which allows the memory to be overwritten either by the 8051 itself or by an external device. This makes upgrades to the product easy to do since new software can be downloaded into the EEPROM rather than having to disassemble it and install a new EPROM. Additionally, battery backed SRAM can be used in place of an EPROM. This method offers the same capability to upload new software to the unit as does an EEPROM, and does not have any sort of read/write cycle limitations such as an EEPROM has. However, when the battery supplying the RAM eventually dies, so does the software in it. Using an SRAM in place of an EPROM in development systems allows for rapid downloading of new code into the target system. When this can be done, it helps avoid the cycle of programming/testing/erasing with EPROM, and can also help avoid hassles over an in circuit emulator which is usually a rare commodity.In addition to executable code, it is common practice with the 8051 to store fixed lookup tables in the CODE segment. To facilitate this, the 8051 provides instructions which allow rapid access to tables via the data pointer (DPTR) or the program counter with an offset into the table optionally provided by the accumulator. This means that oftentimes, a tables base address can be loaded in DPTR and the element of the table to access can be held in the accumulator. The addition is performed by the 8051 during the execution of the instruction which can save many cycles depending on the situation. An example of this is shown later in this chapter in.The DATA SpaceThe second memory space is the 128 bytes of internal RAM on the 8051, or the first 128 bytes of internal RAM on the 8052. This segment is typically referred to as the DATA segment. The RAM locations in this segment are accessed in one or two cycles depending on the instruction. This access time is much quicker than access to the XDATA segment because memory is addressed directly rather than via a memory pointer such as DPTR which must first be initialized. Therefore, frequently used variables and temporary scratch variables are usually assigned to the DATA segment. Such allocation must be done with care, however, due to the limited amount of memory in this segment. Variables stored in the DATA segment can also be accessed indirectly via R0 or R1. The register being used as the memory pointer must contain the address of the byte to be retrieved or altered. These instructions can take one or two processor cycles depending on the source/destination data byte.The DATA segment contains two smaller segments of interest. The first sub segment consists of the four sets of register banks which compose the first 32 bytes of RAM. The 8051 can use any of these four groups of eight bytes as its default register bank. The selection of register banks is changeable at any time via the RS1 and the RS0 bits in the Processor Status Word (PSW). These two bits combine into a number from 0 to 3 (with RS1 being the most significant bit) which indicates the register bank to be used. Register bank switching allows not only for quick parameter passing, but also opens the door for simplifying task switching on the 8051.The second sub-segment in the DATA space is a bit addressable segment in which each bit can be individually accessed. This segment is referred to as the BDATA segment. The bit addressable segment consists of 16 bytes (128 bits) above the four register banks in memory. The 8051 contains several single bit instructions which are often very useful in control applications and aid in replacing external combinatorial logic with software in the 8051 thus reducing parts count on the target system. It should be noted that these 16 bytes can also be accessed on a byte-wide basis just like any other byte in the DATA space.Special Function RegistersControl registers for the interrupt system and the peripherals on the 8051 are contained in internal RAM at locations 80 hex and above. These registers are referred to as special functionRegisters (or SFR for short). Many of them are bit addressable. The bits in the bit addressable SFR can either be accessed by name, index or bit address. Thus, you can refer to the EA bit of the Interrupt Enable SFR as EA, IE.7, or 0AFH. The SFR control things such as the function of the timer/counters, the UART, and the interrupt sources as well as their priorities. These registers are accessed by the same set of instructions as the bytes and bits in the DATA segment. A memory map of the SFRS indicating the registers.The IDATA SpaceCertain 8051 family members such as the 8052 contain an additional 128 bytes of internal RAM which reside at RAM locations 80 hex and above. This segment of RAM is typically referred to as the IDATA segment. Because the IDATA addresses and the SFR addresses overlap, address conflicts between IDATA RAM and the SFRs are resolved by the type of memory access being performed, since the IDATA segment can only be accessed via indirect addressing modes.The XDATA Space.The final 8051 memory space is 64K in length and is addressed by the same 16 address lines as the CODE segment. This space is typically referred to as the external data memory space (or the XDATA segment for short). This segment usually consists of some sort of RAM (usually an SRAM) and the I/O devices or external peripherals to which the 8051 must interface via its bus. Read or write operations to this segment take a minimum of two processor cycles and are performed using either DPTR, R0, or R1. In the case of DPTR, it usually takes two processor cycles or more to load the desired address in addition to the two cycles required to perform the read or write operation. Similarly, loading R0 or R1 will take minimum of one cycle in addition to the two cycles imposed by the memory access itself. Therefore, it is easy to see that a typical operation with the XDATA segment will, in general, take a minimum of three processor cycles. Because of this, the DATA segment is a very attractive place to store any frequently.It is possible to fill this segment entirely with 64K of RAM if the 8051 does not need to perform any I/O with devices in its bus or if the designer wishes to cycle the RAM on and off when I/O devices are being accessed via the bus. Methods for performing this technique will be discussed in chapters later in this book.On-Board Timer/CountersThe standard 8051 has two timer/counters (other 8051 family members have varying amounts), each of which is a full 16 bits. Each timer/counter can be function as a free running timer (in which case they count processor cycles) or can be used to count falling edges on the signal applied to their respective I/O pin (either T0 or T1). When used as a counter, the input signal must have a frequency equal to or lower than the instruction cycle frequency divided by 2 (ie: the oscillator frequency /24) since the incoming signal is sampled every instruction cycle, and the counter is incremented only when a 1 to 0 transition is detected (which will require two samples). If desired, the timer/counters can force a software interrupt when they overflow.The TCON (Timer Control) SFR is used to start or stop the timers as well as hold the overflow flags of the timers. The TCON SFR is detailed below in Table A - 7. The timer/counters are started or stopped by changing the timer run bits (TR0 and TR1) in TCON. The software can freeze the operation of either timer as well as restart the timers simply by changing the Trx bit in the TCON register. The TCON register also contains the overflow flags for the timers. When the timers overflow, they set their respective flag (TF0 or TF1) in this register. When the processor detects a 0 to 1 transition in the flag, an interrupt occurs if it is enabled. It should be noted that the software can set or clear this flag at any time. Therefore, an interrupt can be prevented as well as forced by the software.Microcomputer interfaceA microcomputer interface converts information between two forms .Outside the microcomputer the information handled by an electronic system exists as a physical signals, but within the program , it is represented numerically . The function of any interface can be broken down into a number of operations which modify the data in some way ,so than the process of conversion between the external and internal forms is carried out in a number or steps.This can be illustrated by means of an example such as than or Fig 10-1,which shows an interface between a microcomputer and a transducer producing a continuously variable analog signal. transducers often produce very small out requiring amply frication, or they may generate signals .in a form that needs to be converted again before being handled by the rest of the system .For example ,many transducers these variable resistance which must be converted to a voltage by a special circuit. This process of converting the transducer output into a voltage4 signal which can be connected to the rest of the system is called signal conditioning .In the example of Figure 10-1, the sigma conditioning section translates the range lf voltage or current signals from the transducer to one which can be converted to digital forum by an analog-to-digital converter. Transducer A DCSignal conditioningI/O SectionFig 10-1 output Interface Analog-to-digital digital converter (ADC) is used to convert a continuously variable signal to a corresponding digital forum which can take any one of a fixed number of possible binary values .If the output lf the transducer does not vary continuously ,no ADC is necessary. In this case the signal conditioning section must convert the incoming signal to a form which can be connected directly to the next part of the interface, the input/output section lf the microcomputer itself.The I/O section converts digital “on/off” voltage signals to a form which can be presented to the processor via the via the system buses .Here the state of each input line whether it is “on” or “off”, is indicated by a corresponding “1” or “0”.In the line inputs which have been converted to digital form, the patterns of ones and zeros in the internal representation will form binary numbers corresponding to the quantity being converted. The “raw” numbers from the interface are limited by the design of the interface circuitry and they often require linearization and scaling to produce values suitable for use in the main program. For example ,the interface night be rise to convert temperatures in the range 20 to +50 dress, buy the numbers produced by an 8-bit converter will lie in the range 0 to 255.Obviously it is easier , the programmers point of view to deal directly with temperature rather than to work out the equivalent of any given temperature in terms of the numbers produced by the ADC .Every time the interface is used to read a transducer ,the same operations must be carried out to convert the input number into a more convenient form .Addtionarly ,the operation of some interfaces requires control signals to be passed between the microcomputer and components of the interface ,For these reasons it is normal to use a subroutine to loot after the detailed operation of the interface and carry out any scaling and /or linearization which might be needed. Output interfaces take a similar form (Fig.10-2), the biopic difference being that here the flow of information is in the opposite direction; it is passed from the program to the outside world. In this case the program may call an output subroutine which supervises the operation of the interface and performs the scaling numbers which may be needed for a digital-to-analog converter (DAC) .This subroutine passes information in term to an out analog form using a DAC .Finally the signal is conditioned (usually amplified ) to a form suitable for operating an actuator. Fig 10-2 output Interface The signals used within microcomputer circuits are almost always too small to be connected directly to the “outside world ”and some king of interface must be used to translate them to a more appropriate form .The design of section of interface circuits is one of the most important tasks facing the engineer wishing to apply microcomputers. We have seen that in microcomputers information is represented as discrete patterns of bits ;this digital form is most useful when the microcomputer is to be connected to equipment which can only be switched on or off, where each bit might represent the state of a switch or actuator. Care must be taken when connecting logic circuits to ensure that their logic levels and current ratings are compatible .The output voltages produced by a logic circuit are normally specified in terms of worst case values when sourcing or sinking the maximum rated currents .Thus VOH is the guaranteed minimum “high ” voltage when sourcing the maximum rate “high” output current IOH ,while VOL is the guaranteed “low” output voltage when sinking the maximum rated “low ”output current IOL .There are corresponding specifications for logic inputs which specify the minimum input voltage which will be recognized as a logic “high” state VIH ,and the maximum input voltage which will be regarded as a logic “low” state VIL.For input interface, perhaps the main problem facing the designer is that of electrical nois e .Small noise signal may cause the system to malfunction, while larger amounts of moist can permanently damage it. The designer must be aware of these dangers from the outset. There are many methods to protect interface circuits and microcomputer from various kinds of noise .Following is some examples:1. Input and output electrical isolating between the microcomputer system and external devices using an opt-isolator or a transformer.2. Removing high frequency noise pulses by a low-pea filter and Schmitt-trigger.3. Protecting against excessive input voltages using a pair of diodes to power supply reversibly biased in normal direction. For output interface, parameters VOH, VOL, IOH and IOL of a logic device are usually much to low to allow loads to be connected directly, and in practice an external circuit must be connected to amplify the current and voltage to drive a load. Although several types of semiconductor devices are now available for controlling DC and AC powers up to many kilowatts, there are two basic ways in which a switch can be connected to a load to control it : series connection and shunt connection as shown in Figure 10-3.Fig 10-3 Series and Shunt ConnectionWith series connection, the switch allows current to flow through the load when closed, while with shunt connection closing the switch allows current to bypass the load.Both connections are useful in low-power circuits, but only the series connection can be used in high-power circuits because of the power wasted in the series resistor R.THE INTRODUCTION OF AT89C52Features of the AT89C52 Compatible with MCS-51 Products 8K Bytes of In-System Reprogrammable Flash Memory Endurance: 1,000 Write/Erase Cycles Fully Static Operation: 0 Hz to 24 MHz Three-level Program Memory Lock 256 x 8-Bit Internal RAM 32 Programmable I/O Lines Three 16-bit Timer/Counters Eight Interrupt Sources Programmable Serial Channel Low Power Idle and Power Down ModesDescriptionThe AT89C52 is a low-power, high-performance CMOS 8-bit microcomputer with 8K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmels high density nonvolatile memory technology and is compatible with the industry standard 80C51 and 80C52 instruction set and pin out. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C52 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.The AT89C52 provides the following standard features: 8Kbytes of Flash, 256 bytes of RAM, 32 I/O lines, three 16-bit timer/counters, a six-vector two-level interrupt architecture a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89C52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM timer/counters, serial port, and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next hardware reset.Pin DescriptionVCC Supply voltage.GND Ground.Port 0 Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs. Port 0 can also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pullups.Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pullups are required during program verification.Port 1 Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high byThe internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.In addition, P1.0 and P1.1 can be configured to be thetimer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following table.Port 1 also receives the low-order address bytes during Flash programming and verification.TABLE 1 - Port Pin functionPort pinAlternate FunctionsP1.0T2(external count input to Timer/Counter2),clock-outP1.1T2EX(Timer/Counter 2 capture/reload trigger and direction control)Port 2 Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3 Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.17翻译中文概述8051系列微控制器是基于高度完善的嵌入式控制系统的体系结构。从军事设备到汽车，再到PC机的键盘，它都有很广泛的应用。另外，对于摩托罗拉公司生产的M68HC11（8位处理器）可以应用于不同厂商生产的8051系列微控制器，如：Intel 、Philips 及Siemens等。这些厂商都对8051增加了许多功能部件和外围设备，如：12C总线接口、模/数转换器、监视跟踪定时器和脉冲宽度调制输出。8051的允许范围：时钟频率上至40MHz，电压下至1.5V都是有效的 。一个公司的生产线要完成许多功能，开发人员就不得不学习这个平台，为此以8051系列作为基本体系结构是最好的选择，以它为核心得到了广泛的应用。基本体系结构由下列功能部件组成：1) 8位ALU；2) 32个I/O引脚（4组，每组8个），可分别存取；3) 2个16位定时/计数器；4) 全双工通用异步收发器；5) 6个中断源，2个中断优先级；6) 128字节随机存储器；7) 64字节地址空间，存放数据和代码。一个8051的处理器周期是由12个振荡周期组成。12个振荡周期中每一个都能完成一种特殊功能，8051的核心如：操作码的取出、典型的菊花链待定中断。任何8051指令所需的定时都是由时钟脉冲频率除以12，再将所得结果乘以处理机所需的循环数计算得到。因此，如果你有一个系统时钟11.059MHz，你可以用这个值除以12计算出每秒所需指令数。这里我们给出一个指令频率921583/秒。将它转化成实际时间，每个指令周期（1.085微妙）。存储器组织8051体系结构为用户提供了3个物理直接存储空间。每个存储空间占用连续地址空间，按字节从0到最大尺寸。地址重叠是通过利用引用特定地址空间指令来解决的。这三个存储空间功能如下所述：代码空间第一个存储空间是代码段，其中用来存放可执行程序。这个段最大可达64K（因为它有16根地址线）。处理机将它视为只读，能产生相应的信号对一存储器件进行存取，如可擦可编程只读存储器 EPROM。然而，这不意味着代码段必须作为EPROM的工具。目前，许多嵌入式系统都利用EPROM，通过8051或一个外部设备允许对它存储或改写。这可能轻而易举的提高产品，因为新的软件可以下载到EPROM，而不必将它分解后再安装成一个新的 EPROM。另外，电池后面的静态存储器SRAM也可用来代替EPROM。这种方法和加载软件到电可擦可编程只读存储器EEPROM是一样的，但是EEPROM没有任何读/写周期限制。然而，当电池电源RAM没电了，也可如此将软件加载到里面。在开发系统中若用SRAM代替EPROM，则允许在目标系统中快速下载新代码。如果可以那样做，它将帮助我们避免对EPROM的循环执行/测试/擦写，同时也能帮助我们避免对通常很少使用的线路仿真器产生争论。除可执行程序代码之外，8051通常在代码段存放安装查找表。为了简化，8051提供了允许快速存取查找表指令的途径数据指针（DPTR）或带偏移量的程序计数器通过累加器随意的指向查找表。通常这意味着，一个查找表的基地址能用DPTR来定位，而表中的元素可以通过累加器存储。用 8051 执行加法，在指令执行期间可以根据情况存放许多循环数。数据空间8051辅助存储空间是128字节的内部RAM，而8052的高128字节是辅助存储空间。这个段被认为是典型的数据段。RAM定位在这个段，依靠指令循环存取一次或二次。这样存取时间比存取在XDATA段要快很多，因为存储器直接给出地址，胜于由存储指针如DPTR必须先初始化。因此，通常将已用变量和临时定义变量都放在数据段。然而，这样的分配会占用段中少量的存储单元。数据段中的可变存储器还可以由R0或R1间接存储。使用寄存器作存储指针就必须包含已检索或已改变字节的地址。这些指令可以依靠源/目的数据字节使一个或二个处理机循环。数据段又包含两个重要的小段。第一个子段由四个寄存器组组成，它占用了RAM的低32字节。8051用这四组（每组8字节）作为缺省寄存器组。寄存器组选定区域在任何时候都通过处理机状态字（PSW）中的RS1和RS0这两位来改变。这两位组合表示数03（RS1作最高有效位），用来指明哪个寄存器组在被使用。在8051中，寄存器组开关不但允许快速参数传递，而且能打开单任务开关。在数据空间的第二个子段是一个可寻址位段，每一位都能单独存取。这个段称为BDATA段。可寻址的位段由内存中四个寄存器组16字节（128位）组成。8051包含许多位指令，它通常用于控制某一位的应用及在8051中用软件替换外部组合逻辑给予帮助，这样在目标系统中以减少部分依赖。人们注意到这个16字节还可以按“一位”宽在数据空间像其他字节一样进行存取。特殊功能寄存器8051内部RAM的80H以上的单元为控制寄存器，包含中断系统和外部设备。这些寄存器称为特殊功能寄存器（简称SFR）。它们大部分是可按位寻址的。在可按位寻址的SFR中的位可以是被访问的名称、索引或者是位地址。因此，你可以参看中断允许SFR中的EA（EA、IE.7或0AFH）位。SFR可控制的东西有：定时/计数器和UART的功能。中断源以及它们的优先级。这些被访问的寄存器在数据段中的字节和位是同一张指令表。表A所示SFR的存储图中指明了可寻址的位寄存器。IDATA空间某些8051家族成员，如8052在内部RAM中包含一个辅助128字节，存放在80H以上的单元。这个典型的RAM段被称为IDATA段。因为IDATA地址和SFR地址重叠，IDATA RAM和SFR之间的地址冲突是通过分解被存取存储器的类型来解决，因为IDATA段只能通过间接寻址方式存取。XDATA空间8051存储空间为64K，代码段可用16根地址线寻址。这个典型空间被称为外部数据存储空间（简称XDATA段）。这个段通常由各种RAM（通常为SRAM）、I/O设备或外围设备组成，8051必须通过总线连接。这个段的读或写操作至少需两次循环处理，并且它的执行既要用到DPTR又要用到R0和R1。就DPTR来说，它通常要在执行读或写操作所要求的两个循环外再附加加载两个或更多循环处理地址。同样，在一个周期内除了利用存储器自身存取之外，至少要加载R0或R1。显而易见，XDATA段的典型操作很简单，通常最少需三个循环处理。因此，数据段常用来存储常用变量。如果8051不需要用总线执行任何I/O设备或者设计者希望当I/O设备通过总线存取时让RAM循环开、关，那么它可使这个段全部占满64KRAM。微机接口微机接口实
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