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天津工程师范学院2006届毕业设计（论文）目 录1 引言12设计要求 13 400Hz中频电源的硬件原理与设计 13.1振荡电路2 3.2分频电路23.3 积分电路 43.4 放大电路 64.2控制电路的原理与设计方案 95测试结果116结论12参考文献13致谢14附录 系统电路图 14英文资料及中文翻译151 引言 400Hz中频电源，可广泛应用于舰艇，飞机及机载设备以及工业控制设备，例如，旋转变压器是一种信号检测设备，通过角度的改变，可实现输出电压的改变，进而为控制设备提供控制信号。利用400Hz中频电源给旋转变压器供电，可以实现系统电信号的控制，将非电量转变成了电量。在航天航空设备中，中频电源性能的优劣和可靠性将决定着航行器的安全行驶与战斗力的发挥。新型中频电源自动控制系统具有电路简单，可以实现复杂的控制，控制灵活且具有通用性的优点。当电源本身特性发生变化时候，完全可以通过对软件参数进行修改来对电路进行改动，可以为进一步实现集中控制带来方便。采用新型数字控制系统后，中频电源具有启动平稳、运行稳定、控制精度高、调试与维修方便、体积小等优点。2 设计要求(1) 实现输出频率为稳定的400Hz正弦波。(2) 输出波形没有明显失真。(3) 输出电压为25V65V连续可调（有效值）。3 400Hz中频电源的硬件原理与设计4MHz信号基准电源，通过分频电路进行分频得到400Hz的信号，经过积分电路将方波转化为正弦波，为提高电压的幅值还要经过放大电路进行放大，再通过升压变压器使最后的输出电压的有效值在25V65V之间。通过检波电路得到直流电压，AD采集首先将模拟信号转变成数字信号后，再将采集到的电压值送到单片机中，最后通过单片机送到数码管显示电压，为保证放大电路中TDA7294的正常工作，单片机控制系统还通过稳压电路为其提供电压。中频电源设计原理流程图如图31所示。振荡电路分频电路积分电路放大电路图31 400Hz中频电源设计原理流程3.1 振荡电路为得到频率稳定性很高的振荡信号，多采用由石英晶体组成的石英晶体振荡器。石英晶体的电路符号及振荡电路如图32所示。图32振荡电路在石英晶体两个管脚加交变电场时，它将会产有利于一定频率的机械变形，而这种机械振动又会产生交变电场，上述物理现象称为压电效应。一般情况下，无论是机械振动的振幅，还是交变电场的振幅都非常小。但是，当交变电场的频率为某一特定值时，振幅骤然增大，产生共振，称之为压电振荡。这一特定频率就是石英晶体的固有频率，也称谐振频率。石英晶体的选频特性非常好，串联谐振频率fs也极为稳定，且等效品质因数Q值很高。只有频率为fs的信号最容易通过，而其他频率的信号均会被晶体所衰减。电路中并联在两个反相器4069输入，输出间的电阻R的作用是使反相器工作在线性放大区，R的阻值分别为3.3k和2.7k。电容C1用于两个反相器间的耦合，而C2的作用，则是抑制高次谐波，以保证稳定的频率输出。电容C2的选择应使2RC2fs1，从而使RC2并联网络在fs处产生极点，以减少谐振信号损失。C1的选择应使C1在频率为fs时的容抗可以忽略不计。电路的振荡频率仅取决于石英晶体的串联谐振频率fs，而与电路中的R，C的数值无关。这是因为电路对fs频率所形成正反馈最强而易于维持振荡。为了改善输出波形,增强带负载的能力，通常在振荡器的输出端再加一级反相器4069。输入的信号为4MHz，这样输出的信号频率为4MHz。3.2 分频电路3.2.1 CD4024分频器然后进入CD4024分频器1。CD4024是多位二进制输出串行计数器，它是7位的串行计数或分配器。如图33所示。图33CD4024分频器是由D型触发器组成的二进制计数器。多位二进制计数器主要用于分频和定时，使用极其简单和方便。CD4024特点是IC内部有7个计数级，每个计数级均有输出端子，即Q1Q7。CD4024计数工作时，Q1是CP脉冲的二分频；Q2又是Q1输出的二分频；Q3又是Q2输出的二分频所以有fQ7f2cp。所以进入CD4024的信号4096KHz在Q1端输出的信号为2048KHz，在Q2端输出的信号为1024KHz，在Q3端输出的信号为512KHz，在Q4端输出的信号为256KHz，在Q5端输出的信号为128KHz，在Q6端输出的信号为64KHz，在Q7端输出的信号为32KHz。然后32KHz的信号又进入一个CD4024分频器，在第二个分频器的Q1端的输出信号为16KHz，在Q2端的输出信号为8KHz，在Q3端的输出信号为4KHz。这样输出频率为4KHz的信号又进入下一个分频器74LS90。3.2.2 74LS90计数器74LS90是异步十进制计数器2 。其逻辑电路图和引脚图如图34所示。它由1个1位二进制计数器和1个异步五进制计数器组成。如果计数脉冲由CLK0端输入，输出由Q0端引出，即得二进制计数器；如果计数脉冲由CLK1端输入，输出由Q1Q3引出，即是五进制计数器；如果将Q0与CLK1相连，计数脉冲由CLK0输入，输出由Q0Q1引出，即得8421码十进制计数器。因此，又称此电路为二五十进制计数器。图3474LS90计数器管脚图本设计中信号由CLK1端输入，输出由Q1Q3引出，即是五进制计数器。也可看成五分频器，即Q3是CLK1输出的五分频，Q2是Q3输出的五分频4KHz信号输入在Q3端输出是800Hz信号。此点输出波形为脉冲波形。输出为800Hz的信号又进入下一个分频器D触发器。3.2.3 D触发器边沿型D触发器如图35所示。图35D触发器边沿型触发器3的特点是，输出状态发生变化的时刻只能在时钟脉冲CP的上升沿触发。输出状态Qn+1的值仅仅取决于Qn及CP信号有效沿时刻的输入信号，具备这种特点的触发器就叫做边沿型触发器。D触发器是一种延迟型触发器，不管触发器的现态是0还是1，CP脉冲上升沿到来后，触发器的状态都将改变成与CP脉冲上升沿到来时的D端输入值相同，相当于将数据D存入了D触发器中。表 31 是边沿型D触发器的功能表。表31 边沿型D触发器DQnQn+1说明001101010011输出状态与D端状态相同从功能表写出D触发器的特性方程为： （3.1）D触发器为二分频触发器。即从Q输出的信号为400Hz的方波。400Hz方波要进行二次积分，整形变成正弦波。3.3 积分电路3.3.1 方波变三角波电路如图36（a）所示。由图可见，在理想条件下，图 36（a ）基本积分电路 (3.2)如果电容两端的初始电压为零，则(3.3)当Ui(t)是幅值为Ei的阶跃电压时(3.4)此时，输出电压Uo(t)随时间线性下降，如（33）可知，时间常数RC的数值越大，达到给定的Uo值所需要的时间越长。图36（b）图36（c）输入为阶跃电压时的输出波形输入为方波时的输出波形当Ui(t)是峰值振幅为Uip-p的方波时，Uo(t)的波形则为三角形波，如图36（c）所示。这时，根据式（3.4），输出电压的峰峰值为 （3.5）在实际的积分电路中，通常都在积分电容C的两端并接反馈电阻Rf如图36（a）所示。Rf的作用是产生直流负反馈，目的是减小集成运放输出端的直流漂移。但是，Rf的存在将影响积分器的线性积分关系，这时，输出积分波形将如图36（b）虚线所示。因此，为了改善积分器的线性度，Rf值取大些，但太大对抑制直流漂移不利，因此，Rf应取适中的数值4。3.3.2 三角波变正弦波如图37所示。经过二次积分所得到的波形是正弦波，但此时正弦波是带有直流的波形，频率是400Hz。经过整形滤出直流波形变成正弦波。 图37三角波变正弦波三角波再经过一次积分变成正弦波5。然后进入放大电路，输出电压的幅度不够所以要经过多次放大。3.4 放大电路3.4.1 负反馈放大反馈：可描述为将放大电路的输出量（电压或电流）的一部分或全部，通过一定的方式送回放大电路的输入端。我们有时把引入反馈的放大电路称为闭环放大器，没有引入的称为开环放大器。它可分为负反馈和正反馈。反馈输入信号能使原来的输入信号减小即为负反馈，反之则为正反馈。就是通过比较反馈前后的输入量的改变情况，若反馈后的净输入量减小则为负反馈，反之则为正反馈。（净输入量是反馈后的输入量）判断的方法是：瞬时极性法。先将反馈网络与放大电路的输入段断开，然后设定输入信号有一个正极性的变化，再看反馈回来的量是正极性的还是负极性的，若是负极性，则表示反馈量是削弱输入信号，因此是负反馈。反之则为正反馈6。负反馈对放大倍数的影响(1) 负反馈使放大倍数下降由放大倍数的一般表达式： （3.6） 我们可以看出引入负反馈后，放大倍数下降了(1+FA)倍。(2) 负反馈提高放大倍数的稳定性我们用相对变化量来表示（对上式求导）： （3.7）从上式我们可以看出放大倍数的稳定性也提高了（1+FA）倍。负反馈可以使放大电路的非线性失真减小，它还可以抑制放大电路自身产生的噪声。本设计选用的是加法电路如图39所示。在反相比例放大器的基础上增加几个输入支路便组成反相求和运算电路。如图所示，其输出电压为 （3.8）如果，则 。图39加法电路经过两级负反馈放大调整，输出的仍为400Hz的正弦波形，电压幅值适当调节。3.4.2 TDA7294放大TDA7294是著名的ST意法微电子公司推出一款新型DMOS大功率音频功放集成电路，它具有较宽范围的工作电压，（VCC+VEE）=80V；较高的输出功率（高达100W的音乐输出功率），并且具有静音待机功能，以及过热、短路保护功能。很小的噪声和失真，其音质极具胆味，这缘于其内部电路从输入到输出都是场效应器件。TDA7294实际功率能达到50W的功放IC,在过热保护方面的表现已经做得非常好。他们在功放IC的发热温度低于最高允许值时，输出信号波形始终都保持正常。必须在功放IC金属片上的温度到达115度之后，它们才关段输出。相对于其他大功率功放IC来说， TDA7294确实是其中的佼佼者。经实际使用证明：这款功放IC本身的静态输出背景噪声电压不大于0.25Mv,在4欧负载上输出1W功率时的信噪比已大于75Db，在4欧负载上满功率输出50W功率时的信噪比将高达95Db。TDA7294如图310所示。该器件为15脚封装,各端脚作用如下：脚为待机端；脚为反相输入端；脚为正相输入端；脚接地；、脚为空脚；脚为自举端；脚为+Vs(信号处理部分)；脚为-Vs(信号处理部分)脚为待机脚；脚为静音脚；脚为+Vs(末级)；脚为输出端；脚为-Vs(末级)。 图310TDA7294芯片TDA7294 主要参数如表32所示。表32 TDA7294参数TDA7294主要参数Vs（电源电压）10V40VIO（输入电流峰值）10APO（RMS连续输出功率）当Vs=35V、R=8时 PO=70W当Vs=27V、R=4时 PO=70W音乐功率（有效值）当Vs=38V、R=8时 P=100W当Vs=29V、R=4时 P=100WTDA7294内部线路设计以音色为重点，兼有双极信号处理电路和功率MOS的特点，具有耐压高、低噪音、低失真度等特色，短路电流及过热保护功能使其性能更加完善。TDA7294标准应用电路如图311所示,电路闭环增益为30dB，增大R3或减小R2可以提高放大器增益,反之增益下降；R4、C4决定待机时间常数，取值大时增加等待开/关时间，反之缩短时间；R5、R6、C3决定静音时间常数，取值大时静音时间延长，反之缩短；当控制端接低电位时为待机或静音状态。当控制端接Vs时，因（R5+R6）R4，脚比脚后升到高电位，而关机时先变为低电位，这就使待机和关机过程均在静音状态下进行，保证了放大器开关机无噪声。图311TDA7294标准应用电路信号经C1、R1输入IC正相输入端脚。R7和IC第脚的R3、C3、C4构成负反馈网络，本放大器的闭环增益约34倍。、脚分别是待机、静音端，由于第脚R、C网络时间常数比第脚大，使得开关机均在静音下进行，避免了开关冲击声，C7为自举电容。通过TDA7294放大后输出信号频率仍为400Hz，电压的幅值在40V左右。然后通过升压变压器，变压比为1：4，得到的电压幅值为170V左右，则有效值在65V左右。经过检波电路后，得到直流电压，有效值在25V65V之间，频率仍为400Hz。4 电子控制单元电路。4. 控制电路的原理与设计方案4.1 电源供给模块(1) +V1和-V1的电源如图43所示。图43+V1和-V1供电模块+V1和-V1分别提供+30V和-30V电压供给TDA7294所用。 继电器的定义 继电器是一种当输入量（电、磁、声、光、热）达到一定值时，输出量将发生跳跃式变化的自动控制器件。继电器也是一种电门，但与一般开关不同，继电器并非以机械方式控制的，它是以一定的输入信号(如电流、电压或其它热、光非电信号)实现自动切换电路的“开关”。所以，它是一种自动电器元件。 继电器的分类继电器的分类方法较多，可以按作用原理、外形尺寸、保护特征、触点负载、产品用途等分类。按作用原理分为：电磁继电器（在输入电路内电流的作用下，由机械部件的相对运动产生预定响应的一种继电器）。固态继电器（输入、输出功能由电子元件完成而无机械运动部件的一种继电器）。时间继电器、温度继电器等。 继电器工作原理本设计中是一款固态继电器，固态继电器是一种由固态电子组件组成的新型无触点开关，利用开关三极管的开关特性，达到无触点、无火花、而能接通和断开电路的目的，控制信号通过三极管使发光二极管发光，光源促使与继电器相连的三极管导通，电能转换为磁能，从而使继电器开关闭合，这样就可以输出V1电压。(2) V3和V5的电源如图44所示。 图44V3和V5供电模块V3和V5通过芯片7805分别提供+5V电压。(3) V2和V4的电源如图45所示。图45V2和V4供电模块V2和V4通过芯片LM317分别提供+9V电压。5 测试结果(1) 分步调试过程测量值如下表表51测量值电路波形频率测试电压振荡电路正弦波4MHz4.63V分频电路CD4024分频方波4KHz6.49V74LS90分频脉冲波形800Hz3.17VD触发器方波400Hz3.12V积分电路正弦波400Hz0.56V放大电路负反馈放大正弦波400Hz1.76VTDA7294放大正弦波400Hz42.6V升压变压器正弦波400Hz170.4V检波电路正弦波400Hz60V（有效值）调试过程中，振荡电路出来的频率是十分稳定的，因为本设计要求的频率稳定性特别高，所以一定要通过石英晶体振荡电路给整个电路一个稳定的信号。分频电路中因为CD4024是由D触发器构成的，所以出来的波形是方波。经过积分电路以后，正弦波是带有直流的，要通过整形，变成正弦波。在TDA7294放大之前，电压的幅值都是不够大的，所以要经过TDA7294放大，放大倍数很大，由图表可以看出。(2) 输出结果的测量试验的结果通过对旋转变压器输出电压的测量，结果符合要求。旋转变压器可以改变的最大变压比为0.45，如输入为10V的电压，最大输出电压为4.5V。本设计通过旋转变压器的旋转角度，电压在027V可调。用示波器查看，通过升压变压器以后的电压为170V左右，也即为电压的峰峰值为170V，则电压的有效值为60V。所以输出电压的值为60V，与设计所输出的电压值相吻合。图51示波器显示电压的图形图51为通过示波器显示的波形（示波器显示通过升压变压器后的波形），电压为最大值为Vmax170V，也频率为400Hz,时间即为t s 。电压的有效值为60V。6 结论通过对400Hz中频电源的设计的研究和试验，得出如下结论：(1) 该电源最后通过对旋转变压器的旋转角度的改变进而改变其电压值的测量，符合其最后输出电压的标准。(2) 在此期间保证400Hz频率的不变，波形没有明显的失真。(3) 该系统结构简单，成本低，控制精确。可以用于舰艇，飞机及机载设备、雷达、导航等军用电子设备，以及其它需要400Hz中频电源控制设备。 参考文献 1 曹汉房，陈耀奎数字技术教程，北京：电子工业出版社，1995年26352 康华光，邹寿彬电子技术基础（数字部分），北京：高等教育出版社，2003年，2532593 李士雄，丁康源数字集成电子技术教程，北京：高等教育出版社，1993年，63704 康华光，陈大钦电子技术基础（模拟部分），北京：高等教育出版社，2003年，3333355 衣承斌，刘京南编模拟集成电子技术基础。南京：东南大学出版社，1994年，1021156 童诗白主编模拟电子技术基础，北京：高等教育出版社，1998年，70787 李广弟，朱月秀，王秀山单片机基础（修订版），北京：北京航空航天大学出版社，2001年，16178 刘瑞新，赵全利，赵建军等单片机原理及应用教程，北京：机械工业出版社，2003年7月，1571649 梅丽凤，王艳秋，张军等单片机原理及接口技术，北京：北京交通大学出版社，2004年，29630310 楼然苗，李光飞51系列单片机设计实例，北京：北京航空航天大学出版社，2002年，495211 吴金戌，沈庆阳，郭庭吉8051单片机实践与应用，北京：清华大学出版社，2001年，29330012 秦玲，刘敬波一种用于D/A转换电路的带隙基准电压源的设计，电子设计应用，2006年5月，10011213 Low power DCVSL circuits employing AC power supply WU Xunwei,HANG Guoqiang, Massoud Pedram14 Maksimovic, D., Oklobdzija, V. C., Nikolic, B. et al., Clocked CMOS adiabatic logic with integrated single-phase power-clock supply: experimental results, in Proc. of the International Symposium on Low-Power Electronics and Design, Monterey, New York: IEEE, 1997, 32332715 Wu, X., Pedram, Low power CMOS circuits with alternative power supply, in Proc. China Eleventh Conference on Integrated Circuits and Silicon Materials (in Chinese), 1999, 68869116 Wu, X., Hang, G., Energy recovery circuits with crosscoupled structure, J. of Circuits and S ystems (in Chinese), 2000, 5(2), 18致 谢转瞬之间大学三年的生活已经接近尾声，从上学期毕业设计题目的选择到现在顺利的完成，在此过程中我非常感谢我的指导老师李杰老师，他们给予了我极大的帮助与支持使我受益匪浅。在不久的几个月，我也要踏上工作岗位，老师们那种踏实勤恳、一丝不苟、认真求实的优良品质和学习作风是值得我去学习和发扬的。毕业设计是对我大学三年学习的总结和概括，基本融会了我所学到的知识，在本课题的研究上，虽然我遇到很多麻烦和困难，但是李杰老师给予了我很大支持和鼓励。从最初的实物制作到程序的编写，一遍一遍的重复调试，使我深深的感受到在任何时候都不要轻言放弃，做人如此，做事亦如此。设计过程加深了我对所学知识的掌握，同时也接触到不少新的知识，既增长了见识，又开阔了眼界。最后我要对我的老师们说一句老师您辛苦了，衷心的谢谢您！附录系统电路图英文资料及中文翻译FLIP-FLOPS1 IntorduceIn this passage, we show how to design flip-flops, which operate as one-bit memory cells. Flip-flops are also called latches. Logic circuits constructed using flip-flops can have the present output be a function of both the past and present inputs. Such circuits are called senfiential logic circuits. All flip-flops are based on the same principle: Positive feedback is used to produce a circuit that is bistable . A bistable circuit is one that has two stable operating points. Which operating point the circuit is in is called the state of the circuit. If the state can be sensed and changed, then the circuit can function as a one-bit memory element. The simplest bistable circuit is constructed using two inverters in a loop as shown in Figure 11.This circuit only has two nodes, A and B. Because of the inverters, if A is high, B must be low and vice versa; hence, the circuit has two stable states. The operation of the bistable circuit can also be viewed using a plot of the transfer characteristic of the two inverters in series, as shown in Figure 12. Part (a) of the figure shows the static transfer characteristic of one of the inverters. When the input voltage is below the threshold (a logical ZERO), the output voltage is high (a logical ONE). When the input voltage is greater than the threshold, the output voltage is low. In part (b) of the figure, we show the transfer characteristic that results from putting both inverters in series. Any solution of the equations for this circuit must also lie on this characteristic. Because of the external connection, the input and output voltages of the series connection of the two inverters must be the same. Therefore, we draw a line with a slope of unity on the plot as well. This line is called the load line, because it represents the external load connection for the two inverters in series. Any solution of the equations for this circuit must also lie on the load line. Therefore, when the equations are simultaneously solved, the only possible operating points are found where the straight line intersects the transfer characteristic. There are three intersections on the plot, but only two of them are stable, as we will now demonstrate.The point where the load line intersects the middle of the transfer characteristic is not stable. To see that this statement is true, suppose for the moment that the circuit is at this point. If the input voltage increases at all (due to noise or some change in the circuit), the output voltage of the inverters must also increase. But the output is input, so as it increases, it causes further increases in the output, and the original change is magnified. This positive feedback will quickly drive the circuit to the top operating point shown. At that point, the input and output of the two-inverter chain are high and the midpoint (B in Figure 11) is low, so the circuit is stable and can remain in this state forever. If we started at the midpoint and let the input voltage decrease a bit, we would end up at the lower operating point, which is again stable.In the sections that follow, we show how we can move this bistable circuit from one operating point to the other. The internal positive feedback will then hold the circuit at that state until we deliberately change it; hence, the circuit has memory.Figure 11A bistable circuit(a)(b)Figure 12 (a) One inverter and its transfer characteristic (b) The transfer characteristic for two inverters in series and the load line for the circuit 2 The Set-Reset Flip-FlopA set-reset (SR) flip-flop is shown in Figure 21(a). A table describing the function of the circuit is shown in part (b) of the figure, and the schematic symbol is shown in part (c). This function table is similar to a truth table, but it describes a dynamic situation, not a static one. The output is the output at some discrete time, denoted by Qn, and the table includes an entry for the previous state of the flip-flop (Qn-1). Although the circuit is drawn differently, the two NOR gates are in series, just like the inverters in Figure 12(b). The configuration shown here is usually described as cross coupled. The flip-flop has two outputs that are complements of each other. We usually consider the Q output to be the state of the flip-flop.(a)SRQn00Qn-101010111不允许的（b）(c) Figure 21 (a) An SR flip-flop, (b) a table describing the circuits function (c) the schematic symbol.The circuit operates in the following way: If both inputs (S and R) are zero, the previous state is retained. Suppose, for example, that Qn-1 is high (i.e., ONE). Then the output of the bottom NOR, which isn-1 , will be low (i.e., ZERO), independently of what S is. In this case, both inputs to the top NOR are low, so its output is high, as originally assumed. Now suppose that Qn-1 is low. In this case, both inputs to the bottom NOR are low, so n-1 is high. Therefore, the output of the top NOR, Qn-1, will be low, as assumed. Now consider what happens when the set input, S, goes high while R remains low. The output of the bottom NOR, n-1 , will now go low, independent of what the previous state of the circuit was. With R low as well, this guarantees that Qn will go high (i.e, the flip-flop has been “set”). Note that S does not have to stay high. Once the flip-flop is set, the S input can go low again, and the state will be retained. This sequence of events is illustrated in Figure 22 The figure shows that there is some delay through each gate, so it takes a time td for the change at the gate input to affect its output. Figure 22 A timing diagram for the SR flip-flop. The arrows indicate which transition causes the following change.The operation of the reset input is similar. If R goes high while S is kept low, the output of the top NOR, Qn, will go low (i.e., the flip-flop is “reset”). With Qn and S both low, the bottom NOR output will be high. The reset input can go low again, and this new state will be retained. This sequence is also illustrated in Figure 22.Finally, we note that both inputs should not be allowed to go high at the same time. If this happens, both NOR outputs go low, so Q and are not complements anymore. Also, if both inputs are high and then go low at exactly the same time, we cant predict what the resulting output state will be, since both outputs will try to go high, which is a condition that cannot be sustained. Which output will actually stay high depends on mismatches in the NOR gates and cannot be predicted.3 The JK Flip-FlopThe fact that the output of an SR flip-flop is undefined if both inputs go high is troublesome in many applications. The JK flip-flop avoids this problem and is more flexible in its operation. The JK flip-flop is a clocked flip-flop; that is, it requires a separate clock input to operate. This clock signal is usually a square wave with a fixed period. Logic circuits that require a clock and that only allow output transitions to occur in synchrony with the clock are called synchronous-logic circuits. The clock can be generated using an astable multivibrator. (a) (b)JKQn00Qn-101010111n-1 (c) Figure 31 (a) A JK flip-flop made using an SR flip-flop. (b) The Schematic symbol for a JK flip-flop (c) the function table. (The flip-flop only changes state when the clock is high.)A JK flip-flop is shown in Figure 31(a); the schematic symbol is shown in part (b) of the figure, and the function table is shown in part (c). The AND gates serve to enable the inputs to the SR flip-flop. That is, only when the clock is high are the J and K inputs able to affect the SR flip-flop. In addition to needing the clock to be high, the J input affects S only if the SR flip-flop is currently reset, and the K input affects R only if the flip-flop is currently set. Therefore, we see that when both J and K are low, S and R will be low, and the flip-flop will hold its present state just like the SR flip-flop. When J is high and the flip-flop is currently reset (i.e., n-1 is high), the flip-flop will be set when the clock goes high, independently of what K is. If K is high and the flip-flop is currently set (i.e., Qn-1 is high), the flip-flop will reset when the clock goes high, independently of what J is. It follows that if both J and K are high, the flip-flop will toggle its state when the clock goes high. When operated in the toggle mode, a JK flip-flop is sometimes called a T flip-flop.The JK flip-flop as shown in Figure 31has a major problem: It will work only if the clock pulse width (i.e., the time the clock is high) is short compared with the propagation delay of the gate. To understand this limitation, consider what happens when J and K are both high and Qn-1 is low. In this case, the output of the flip-flop will toggle when the clock goes high, as indicated in the function table. But, if the output toggles and the clock is still high, the output will toggle again . This process will repeat until either the clock goes low or J or K changes. In order to avoid this problem, we use master-slave JK flip-flop.A master-slave JK flip-flop is shown in Figure 32. The master flip-flop is enabled when the clock is high, so the data are latched into the master during that portion of the clock cycle. During that time, c is low and the slave is disabled and holds the previous value. Then the clock goes low, c goes high and enables the slave. The data from the master are then transferred to the slave and show up at the output. Since the master and slave flip-flops are never enabled at the same time, the output will not continue to toggle if the clock is held in any one state for too long. The clock does have to remain in each state long enough to allow for the propagation delay through one of the flip-flops.Figure 32 A master-slave JK flip-flopIn designing a master-slave JK flip-flop, we must carefully consider the propagation delays of the individual gates to prevent the slave from changing before it should. For example, in the figure, the data on SM and RM can change one gate delay after the clock goes high. The slave clock, which is c, goes low one inverter delay after the clock goes high. We must be sure that the slave clock changes before the output of the master flip-flop can change; otherwise, the data will pass on through to the slave and we will not have accomplished our purpose. Similarly, when the clock goes low, we must be sure that the master is disabled before the slave outputs can change.The JK flip-flop just described is level-triggered flip-flop; that is, the master is enabled when the clock level is high, and the slave is enabled when the clock level is low. The problem with level-triggered JK flip-flops is that they are sensitive to glitches on the inputs at certain points in the operation. For example, suppose that the previous state of the flip-flop was Q=0 and that we are now ready for the next clock cycle. Suppose further that J=0 and K=1, so we are resetting the flip-flop again; in other words, we dont want the state to change. In this case, while the clock is high, both SM and RM are low, so the master flip-flop output should not change. However, if a positive glitch occurs on the J input prior to the clock going low, it can pass through to SM and set the master flip-flop. Since Q is low, the AND gate driving RM is disabled, so we dont have any opportunity for the flip-flop to be reset. As a result, when the clock goes low, this error will be passed on to the slave. A similar situation exists if we are trying to set the flip-flop when it is already set. A positive glitch on the K input can cause an erroneous reset. This problem is sometimes called ones catching, since the flip-flop has captured an erroneous ONE. We could make the problem far less likely to occur if we used a clock with a very short positive pulse, but a much better solution is to use an edge-triggered JK flip-flop.An edge-triggered JK flip-flop is shown in Figure 33(a), and the schematic symbol is shown in part (b) of the figure. The triangle inside the block in part (b) indicates that the flip-flop is edge-triggered. as explained in a moment, and the bubble indicates that it is negative edge triggered (i.e., the input is latched on the negative-going edge of the clock ). (a) (b) Figure 33 (a) An edge-triggered JK flip-flop (b) the schematic symbol for it To understand how this circuit operates, we need to first examine the input gate structure. Consider, for example, the situation where Q=0 and we want to set the flip-flop, so J=1. Part of the input structure is shown in Figure 34(a) for this case, and the corresponding waveforms are shown in part (b) of the figure. (a) (b) Figure 34(a) A part of the input circuit when Q=0. (b) The resulting waveforms.The bubbles at the input of the second gate invert the inputs so that the AND is true when both inputs are low. Because Q=0, we know that =1. Now, with J=1, the output of the NAND gate, Jc, will be the inverse of the clock, delayed by one gate delay. Therefore, when the clock goes low, Jc will go high one gate delay later, as shown. During that gate delay, both inputs to the second gate are low, so the AND is true and S goes high. In other words, the negative edge of the clock has produced a narrow pulse on the S line as a result of the J input being high. Similarly, if the K input is high and Q=1, a negative clock edge will produce a narrow pulse on the R line. In this way, the SR flip-flop is set or reset only on the negative clock edge. As long as the J and K inputs are held constant for some short time prior to the clock edge (called the setup time) and are held constant for some short time after the clock edge (called the hold time), the circuit is insensitive to glitches on the inputs. It is also possible to make positive edge-triggered circuits4 The D Flip-FlopA D flip-flop is shown is Figure 41(a), and its schematic symbol is shown in part (b) of the figure. This flip-flop implements a digital delay; that is, the output at the end of each clock cycle is equal to the input on the previous cycle, as seen in the function table in part (c) of the figurehence the name D flip-flop. This particular circuit is positive-edge triggered, so the output changes state slightly after the positive-going edge of the clock. The output is insensitive to the value of the D input, except for a brief time before (the setup time) and after (the hold time) the positive clock edge. D flip-flips are commonly used in shift registers and counters, as discussed in the next section. (a) (b)Dn-1Qn0011 (c) Figure 41 (a) A D flip-flop (b) its schematic symbol (c) the function table. Clocked flip-flops also frequently have asynchronous clear and preset inputs, as shown for a D flop-flop in Figure 42. The preset input will set the flip-flop so that Q=1 at any time, regardless of the state of the clock; that is what is meant by being asynchronous. In similar fashion, the clear input will clear the flip-flop so that Q=0 at any time. Figure 42 A D flip-flop with preset and clear inputs 触发器1简介本文，我们将介绍如何设计可作为一位存储单元的触发器。触发器也可称为锁存器。采用触发器的逻辑电路结构其当前的输出是电路的前一稳定状态和当前稳定状态的函数。这样的电路称为时序逻辑电路。所有的触发器都遵循同一规则：正反馈用来生成双稳态电路，双稳态电路是一个具有两个稳定工作点的电路。电路所处的工作点称为电路的一个状态。如果其状态能够读出和改变，那么此电路就可以作为一个一位存储器单元。最简单的双稳态电路是在一个回路中利用两个反相器构成的。如图11所示。这个电路只有两个节点，A和B。由于是反相器，所以如果A是高电平,那么B就必须是低电平，或者反相。因此，电路具有两个稳定状态。也可以通过两个串联的反相器的传输特性曲线图来查看双稳态电路的操作，如图12所示。突12（a）给出了其中一个反相器的静态传输特性。当输入电压低于门限电压（逻辑0），输出电压变为高电平（逻辑1）。当输入电压超过门限电压，则输出为低电平。在图12（b），给出了将两个反相器串联后所得到的传输特性曲线。该电路逻辑等式的任何一个结果都必须落在这条特性曲线上。由于是外部连接，两个反相器的串联连接处的输入输出电压必须相等。因此，再在图中划出一条单位斜率的直线。这条线称为负载线，因为它代表了两个串联反相器的外部负载的关系。该电路逻辑等式的任何一个解也必须落在负载线上。因此，如果将这两个等式联立求解，就可以得到唯一的工作点，这一点正是负载直线与传输特性曲线的交点。在图中的曲线上一共有三个交点，但是只有其中两个是稳定的，正如我们将要论证的。图 11双稳态电路 (a) （b） 图 12（a）反相器和它的传输特性 （b）两个反相器串联的传输特性和负载曲线负载直线与传输特性曲线中部的交点是不稳定的。为了证明这点，假设在某一时刻电路工作与这一点。如果无论何时输入电压增加了（由于噪声或是电路发生一些变化），反相器的输出电压也必须增大。但是由于输出就是输入，因此它的增大会导致输出的进一步增加，原有的变化被放大了。这样的正反馈将迅速驱动电路达到所示的顶端的工作点。在那一点，二反相器链的输入输出电压都很高，而中间点电压（图11中的vB）较低。因此电路是稳定的并且能够永远保持着状态。如果从中间点开始让输入电压减小一点，那么会落在更低的工作点上，再次达到稳定。在接下来的部分，我们将说明如何使这个双稳态电路从一个工作状态转移到另一个工作状态，但是，内部的正反馈将会使电路保持在这个状态直到有意改变它。因此电路具有记忆。2 SR触发器SR（设置-复位）触发器如图21（a）所示。图21（b）给出了电路的功能表，而图21(c)给出了它的电路逻辑符号。这个功能表与真值表类似，但它描述的是动态的情况，而不是静态的。其输出是在一些离散时间上的输出，用Qn表示，此外表中还包括触发器前一状态的输入(Qn-1)。虽然所画的电路与上节所讲得不相同，但它也是两个或非门串联在一起，就像图12(b)中的两个反相器一样。这里所示的结构通常也被描述为交叉耦合。触发器的两个输出是互补的。我们通常认为输出Q是触发器的状态。(a)SRQn00Qn-101010111不允许的 （b） (c) 图 21 (a) SR触发器 （b）描述电路的功能表 （c）电路逻辑符号该电路的工作原理如下：如果两个输入端(S和R)都是逻辑0，则保持前一状态。例如，假设Qn-1时高电平（即逻辑1），那么无论S是什么状态，下面那个或非门的输出 n-1 都将是低电平(即逻辑0)。在这种情况下，上面那个或非门的两个输入端都是低电平，因此它的输出是高电平，正如前面所假设的那样。现在，我们假设Qn-1是低电平。在这种情况下，下面那个或非门的两个输入都是低电平，所以其输出 n-1 为高电平。因此，上面那个或非门的输出Qn-1就像假设的那样是低电平。现在考虑当置1端S为高电平而置0端R保持低电平时会发生什么情况。这时无论电路的前一状态是怎样的，下方的或非门的输出 n-1 都将变为低电平。再加上R也是低电平，这就保证了Qn将变为高电平（即触发器被置位为1）。注意，S不必一直处于高电平，一旦触发器被置1，输入端S便可再次回到低电平，状态将被保持。整个过程的顺序在图22中用图解进行了说明。从图中可以看到，在通过每一个门时都有一定的延时。因此，在门输入端的变化需要延迟一个时间td才能影响到输出端。 图22 SR 触发器的时序图 箭头表明此处输入电平的转换引起的随后输出的变化置0输入端的工作原理是类似的。如果R达到高电平而S保持而低电平，那么上面那个或非门的输出Qn将变为低电平（即触发器被置0）。由于Qn和S都为低电平，下方的或非门的输出将为高电平。此时置0端可以再次回到低电平，新的状态将被保持。其顺序在图22中也有图解说明。最后，要注意这两个输入端不允许同时为高电平。如果发生这种情况，两个或非门的输出都为低电平，而Q和 也不再互补。同样，如果两个输入端同时为高电平又在同一时刻变为低电平，那么我们将不能预测输出结果会是什么状态，这是因为两个输出端都将试图变为高电平，而这种情况是不可维持的。如果输出状态真都保持在高电平，则主要是由或非门失陪引起的。3 JK触发器事实上，当两个输入端都是高电