DES加密算法Verilog实现源代码.doc

module des_top(input clk, input des_enable, input reset, input des_mode, input 1:64 data_i, input 1:64 key_i, output wire 1:64 data_o,output ready_o);wire 3:0 inter_num_curr;wire 1:32 R_i_var, L_i_var;wire 1:56 Key_i_var_out;wire 1:64 data_o_var_t;wire 1:32 R_i, L_i;wire 1:32 R_o, L_o;wire 1:56 Key_o;wire 1:28 C0, D0;IP IP1(.in(data_i), .L_i_var(L_i_var), .R_i_var(R_i_var);IP_niIP_ni(.in(data_o_var_t), .out(data_o);pc_1 pc_1(.key_i(key_i), .C0(C0), .D0(D0);/F(R,K)des_f des_f1(.clk(clk), .reset(reset), .des_mode(des_mode), .inter_num_i(inter_num_curr), .R_i(R_i), .L_i(L_i), .Key_i(Key_i_var_out), .R_o(R_o), .L_o(L_o), .Key_o(Key_o); /contral 16 F(R,K)contrl contrl1(.data_o_var_t(data_o_var_t), .inter_num_curr(inter_num_curr), .Key_i_var_out(Key_i_var_out), .R_i(R_i), .L_i(L_i), .ready_o(ready_o), .L_o(L_o), .R_o(R_o), .R_i_var(R_i_var), .L_i_var(L_i_var), .Key_o(Key_o), .C0(C0), .D0(D0), .clk(clk), .reset(reset), .des_enable(des_enable);endmodulemodule contrl(output 1:64 data_o_var_t, output reg 3:0 inter_num_curr, output reg 1:56 Key_i_var_out, output reg 1:32 R_i, L_i, output reg ready_o, input 1:32 L_o, input 1:32 R_o, input 1:32 R_i_var, L_i_var, input 1:56 Key_o, input 1:28 C0, D0, input clk, reset, des_enable); reg 3:0 inter_num_next;assign data_o_var_t = (ready_o = 1b1)?L_o,R_o:64hzzzzzzzzzzzzzzzz;always (posedge clk or negedge reset)if(reset = 1b0)begin inter_num_next = 4d0; inter_num_curr = 4d0; ready_o = 1b0; endelse if(des_enable)beginif(ready_o = 1b0)inter_num_curr = inter_num_next;endalways (posedge clk or negedge reset)beginif(reset = 1b0)ready_o = 1b0;else if(inter_num_curr = 4d15) ready_o = 1b1; else ready_o = 1b0;end always (*)begincase(inter_num_curr)4d0:begin/ready_o = 1b0; R_i = R_i_var; L_i = L_i_var; Key_i_var_out = C0, D0; inter_num_next = 4d1; end4d1: begin/ready_o = 1b0; R_i = R_o;L_i = L_o;Key_i_var_out = Key_o;inter_num_next = 4d2;end4d2: begin/ready_o = 1b0; R_i = R_o;L_i = L_o;Key_i_var_out = Key_o;inter_num_next = 4d3;end4d3: begin/ready_o = 1b0; R_i = R_o;L_i = L_o;Key_i_var_out = Key_o;inter_num_next = 4d4;end4d4: begin/ready_o = 1b0; R_i = R_o;L_i = L_o;Key_i_var_out = Key_o;inter_num_next = 4d5;end4d5: begin/ready_o = 1b0; R_i = R_o;L_i = L_o;Key_i_var_out = Key_o;inter_num_next = 4d6;end4d6: begin/ready_o = 1b0; R_i = R_o;L_i = L_o;Key_i_var_out = Key_o;inter_num_next = 4d7;end4d7: begin/ready_o = 1b0; R_i = R_o;L_i = L_o;Key_i_var_out = Key_o;inter_num_next = 4d8;end4d8: begin/ready_o = 1b0; R_i = R_o;L_i = L_o;Key_i_var_out = Key_o;inter_num_next = 4d9;end4d9: begin/ready_o = 1b0; R_i = R_o;L_i = L_o;Key_i_var_out = Key_o;inter_num_next = 4d10;end4d10: begin/ready_o = 1b0; R_i = R_o;L_i = L_o;Key_i_var_out = Key_o;inter_num_next = 4d11;end4d11: begin/ready_o = 1b0; R_i = R_o;L_i = L_o;Key_i_var_out = Key_o;inter_num_next = 4d12;end4d12: begin/ready_o = 1b0; R_i = R_o;L_i = L_o;Key_i_var_out = Key_o;inter_num_next = 4d13;end4d13: begin/ready_o = 1b0; R_i = R_o;L_i = L_o;Key_i_var_out = Key_o;inter_num_next = 4d14;end4d14: begin/ready_o = 1b0; R_i = R_o;L_i = L_o;Key_i_var_out = Key_o;inter_num_next = 4d15;end4d15:if(ready_o = 1b0) begin R_i = R_o; L_i = L_o; Key_i_var_out = Key_o;/ready_o = 1b1; end endcaseendendmodulemodule des_f(input clk, input reset, input des_mode, input 3:0 inter_num_i, input 1:32 R_i, input 1:32 L_i, input 1:56 Key_i, output reg 1:32 R_o, output reg 1:32 L_o, output reg 1:56 Key_o); reg 1:32 next_R;/reg 31:0 R_i_var;wire 1:48 expandedR;reg 1:56 pre_key;reg 1:48 new_key_tmp;reg 3:0 inter_num;wire 1:32 p;reg 1:48 address_s;reg 1:32 Soutput;wire 1:32 Soutput_wire;wire 1:48 new_key;wire 1:56 out_key;key_get key_get(.pre_key(pre_key), .des_mode(des_mode), .inter_num(inter_num), .new_key(new_key), .out_key(out_key);s1 sbox1(.stage1_input(address_s1:6), .stage1_output(Soutput_wire1:4);s2 sbox2(.stage1_input(address_s7:12), .stage1_output(Soutput_wire5:8);s3 sbox3(.stage1_input(address_s13:18), .stage1_output(Soutput_wire9:12);s4 sbox4(.stage1_input(address_s19:24), .stage1_output(Soutput_wire13:16);s5 sbox5(.stage1_input(address_s25:30), .stage1_output(Soutput_wire17:20);s6 sbox6(.stage1_input(address_s31:36), .stage1_output(Soutput_wire21:24);s7 sbox7(.stage1_input(address_s37:42), .stage1_output(Soutput_wire25:28);s8 sbox8(.stage1_input(address_s43:48), .stage1_output(Soutput_wire29:32);always (posedge clk or negedge reset)beginif(reset = 1b0)beginR_o = 32d0;L_o = 32d0;Key_o = 56d0;endelsebeginKey_o = out_key;if(inter_num = 4b1111)beginR_o = R_i;L_o = next_R;endelsebeginR_o = next_R;L_o = R_i;endendendassign expandedR =R_i32,R_i1,R_i2,R_i3,R_i4,R_i5, R_i4,R_i5,R_i6,R_i7,R_i8,R_i9, R_i8,R_i9,R_i10,R_i11,R_i12,R_i13, R_i12,R_i13,R_i14,R_i15,R_i16,R_i17, R_i16,R_i17,R_i18,R_i19,R_i20,R_i21, R_i20,R_i21,R_i22,R_i23,R_i24,R_i25, R_i24,R_i25,R_i26,R_i27,R_i28,R_i29, R_i28,R_i29,R_i30,R_i31,R_i32,R_i1;assign p = Soutput16,Soutput7,Soutput20,Soutput21, Soutput29,Soutput12,Soutput28,Soutput17, Soutput1,Soutput15,Soutput23,Soutput26, Soutput5,Soutput18,Soutput31,Soutput10, Soutput2,Soutput8,Soutput24,Soutput14, Soutput32,Soutput27,Soutput3,Soutput9, Soutput19,Soutput13,Soutput30,Soutput6, Soutput22,Soutput11,Soutput4,Soutput25; always (*)beginpre_key = Key_i;inter_num = inter_num_i;new_key_tmp = new_key;address_s = new_key_tmp expandedR;Soutput = Soutput_wire;/?next_R = (L_ip); endendmodulemodule IP(input 1:64 in, output 1:32 L_i_var, output 1:32 R_i_var); assign L_i_var, R_i_var = in58,in50,in42,in34,in26,in18,in10,in2, in60,in52,in44,in36,in28,in20,in12,in4, in62,in54,in46,in38,in30,in22,in14,in6, in64,in56,in48,in40,in32,in24,in16,in8, in57,in49,in41,in33,in25,in17,in9,in1, in59,in51,in43,in35,in27,in19,in11,in3, in61,in53,in45,in37,in29,in21,in13,in5, in63,in55,in47,in39,in31,in23,in15,in7; Endmodulemodule IP_ni(input 1:64 in, output 1:64 out); assign out = in40,in8,in48,in16,in56,in24,in64,in32, in39,in7,in47,in15,in55,in23,in63,in31, in38,in6,in46,in14,in54,in22,in62,in30, in37,in5,in45,in13,in53,in21,in61,in29, in36,in4,in44,in12,in52,in20,in60,in28, in35,in3,in43,in11,in51,in19,in59,in27, in34,in2,in42,in10,in50,in18,in58,in26, in33,in1,in41,in9,in49,in17,in57,in25;Endmodulemodule key_get(input 1:56 pre_key, input des_mode, input 3:0 inter_num, output wire 1:48 new_key, output reg 1:56 out_key); reg pre_key_0, pre_key_1; reg 1:56 pre_key_var; always (*) begin if(des_mode = 1b0) begincase(inter_num) 4d0, 4d1, 4d8, 4d15: begin pre_key_var = pre_key; pre_key_0 = pre_key_var1; pre_key_var1:28 = pre_key_var1:28 1; pre_key_var28 = pre_key_0; pre_key_0 = pre_key_var29; pre_key_var29:56 = pre_key_var29:56 1; pre_key_var56 = pre_key_0; end 4d2, 4d3, 4d4, 4d5, 4d6, 4d7, 4d9, 4d10, 4d11, 4d12, 4d13, 4d14: begin pre_key_var = pre_key; pre_key_1, pre_key_0 = pre_key_var1:2; pre_key_var1:28 = pre_key_var1:28 2; pre_key_var27:28 = pre_key_1, pre_key_0; pre_key_1, pre_key_0 = pre_key_var29:30; pre_key_var29:56 = pre_key_var29:56 1; pre_key_var1 = pre_key_0; pre_key_0 = pre_key_var56; pre_key_var29:56 = pre_key_var29:56 1; pre_key_var29 = pre_key_0; end default: begin pre_key_var = pre_key; pre_key_1, pre_key_0 = pre_key_var27:28; pre_key_var1:28 = pre_key_var1:28 2; pre_key_var1:2 = pre_key_1, pre_key_0; pre_key_1, pre_key_0 = pre_key_var55:56; pre_key_var29:56 = pre_key_var29:56 2; pre_key_var29:30 = pre_key_1, pre_key_0; end endcaseendout_key = pre_key_var; end assign new_key = pre_key_var14,pre_key_var17,pre_key_var11,pre_key_var24,pre_key_var1,pre_key_var5, pre_key_var3,pre_key_var28,pre_key_var15,pre_key_var6,pre_key_var21,pre_key_var10, pre_key_var23,pre_key_var19,pre_key_var12,pre_key_var4,pre_key_var26,pre_key_var8, pre_key_var16,pre_key_var7,pre_key_var27,pre_key_var20,pre_key_var13,pre_key_var2, pre_key_var41,pre_key_var52,pre_key_var31,pre_key_var37,pre_key_var47,pre_key_var55, pre_key_var30,pre_key_var40,pre_key_var51,pre_key_var45,pre_key_var33,pre_key_var48, pre_key_var44,pre_key_var49,pre_key_var39,pre_key_var56,pre_key_var34,pre_key_var53, pre_key_var46,pre_key_var42,pre_key_var50,pre_key_var36,pre_key_var29,pre_key_var32; Endmodulemodule pc_1(input 1:64 key_i, output 1:28 C0, output 1:28 D0);assign C0=key_i57,key_i49,key_i41,key_i33,key_i25,key_i17,key_i9, key_i1,key_i58,key_i50,key_i42,key_i34,key_i26,key_i18, key_i10,key_i2,key_i59,key_i51,key_i43,key_i35,key_i27, key_i19,key_i11,key_i3,key_i60,key_i52,key_i44,key_i36; assign D0=key_i63,key_i55,key_i47,key_i39,key_i31,key_i33,key_i15, key_i7,key_i62,key_i54,key_i46,key_i38,key_i30,key_i22, key_i14,key_i6,key_i61,key_i53,key_i45,key_i37,key_i29, key_i21,key_i13,key_i5,key_i28,key_i20,key_i12,key_i4;Endmodulemodule s1(stage1_input,stage1_output);input 5:0 stage1_input;output 3:0 stage1_output;reg 3:0 stage1_output;/BIT5 and BIT0 is ? /BIT41 is ?always ( stage1_input)begin case(stage1_input)/synopsys full_case parallel_case 0: stage1_output = 4d14; 1: stage1_output = 4d0; 2: stage1_output = 4d4; 3: stage1_output = 4d15; 4: stage1_output = 4d13; 5: stage1_output = 4d7; 6: stage1_output = 4d1; 7: stage1_output = 4d4; 8: stage1_output = 4d2; 9: stage1_output = 4d14; 10: stage1_output = 4d15; 11: stage1_output = 4d2; 12: stage1_output = 4d11; 13: stage1_output = 4d13; 14: stage1_output = 4d8; 15: stage1_output = 4d1; 16: stage1_output = 4d3; 17: stage1_output = 4d10; 18: stage1_output = 4d10; 19: stage1_output = 4d6; 20: stage1_output = 4d6; 21: stage1_output = 4d12; 22: stage1_output = 4d12; 23: stage1_output = 4d11; 24: stage1_output = 4d5; 25: stage1_output = 4d9; 26: stage1_output = 4d9; 27: stage1_output = 4d5; 28: stage1_output = 4d0; 29: stage1_output = 4d3; 30: stage1_output = 4d7; 31: stage1_output = 4d8; 32: stage1_output = 4d4; 33: stage1_output = 4d15; 34: stage1_output = 4d1; 35: stage1_output = 4d12; 36: stage1_output = 4d14; 37: stage1_output = 4d8; 38: stage1_output = 4d8; 39: stage1_output = 4d2; 40: stage1_output = 4d13; 41: stage1_output = 4d4; 42: stage1_output = 4d6; 43: stage1_output = 4d9; 44: stage1_output = 4d2; 45: stage1_output = 4d1; 46: stage1_output = 4d11; 47: stage1_output = 4d7; 48: stage1_output = 4d15; 49: stage1_output = 4d5; 50: stage1_output = 4d12; 51: stage1_output = 4d11; 52: stage1_output = 4d9; 53: stage1_output = 4d3; 54: stage1_output = 4d7; 55: stage1_output = 4d14; 56: stage1_output = 4d3; 57: stage1_output = 4d10; 58: stage1_output = 4d10; 59: stage1_output = 4d0; 60: stage1_output = 4d5; 61: stage1_output = 4d6; 62: stage1_output = 4d0; 63: stage1_output = 4d13; endcaseendendmodulemodule s2(stage1_input,stage1_output);input 5:0 stage1_input;output 3:0 stage1_output;reg 3:0 stage1_output;always ( stage1_input)begin case(stage1_input)/synopsys full_case parallel_case 0: stage1_output = 4d15; 1: stage1_output = 4d3; 2: stage1_output = 4d1; 3: stage1_output = 4d13; 4: stage1_output = 4d8; 5: stage1_output = 4d4; 6: stage1_output = 4d14; 7: stage1_output = 4d7; 8: stage1_output = 4d6; 9: stage1_output = 4d15; 10: stage1_output = 4d11; 11: stage1_output = 4d2; 12: stage1_output = 4d3; 13: stage1_output = 4d8; 14: stage1_output = 4d4; 15: stage1_output = 4d14; 16: stage1_output = 4d9; 17: stage1_output = 4d12; 18: stage1_output = 4d7; 19: stage1_output = 4d0; 20: stage1_output = 4d2; 21: stage1_output = 4d1; 22: stage1_output = 4d13; 23: stage1_output = 4d10; 24: stage1_output = 4d12; 25: stage1_output = 4d6; 26: stage1_output = 4d0; 27: stage1_output = 4d9; 28: stage1_output = 4d5; 29: stage1_output = 4d11; 30: stage1_output = 4d10; 31: stage1_output = 4d5; 32: stage1_output = 4d0; 33: stage1_output = 4d13; 34: stage1_output = 4d14; 35: stage1_output = 4d8; 36: stage1_output = 4d7; 37: stage1_output = 4d10; 38: stage1_output = 4d11; 39: stage1_output = 4d1; 40: stage1_output = 4d10; 41: stage1_output = 4d3; 42: stage1_output = 4d4; 43: stage1_output = 4d15; 44: stage1_output = 4d13; 45: stage1_output = 4d4; 46: stage1_output = 4d1; 47: stage1_output = 4d2; 48: stage1_output = 4d5; 49: stage1_output = 4d11; 50: stage1_output = 4d8; 51: stage1_output = 4d6; 52: stage1_output = 4d12; 53: stage1_output = 4d7; 54: stage1_output = 4d6; 55: stage1_output = 4d12; 56: stage1_output = 4d9; 57: stage1