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DAC0832设计020Hz超低频信号发生器1引言 雷达的天线控制系统是一个自动调整系统，其任务是使天线自动跟踪目标。目标(例如：飞机等)在空间瞬时坐标的倍息，就是雷达天线控制系统的输入量。要实现对雷达天线控制系统的性能测试，必须对目标信息进行模拟，为此，我们设计了一种单片机控制下的超低频信号发生器，用其产生频率和幅度都能改变的正弦信号模拟不同的目标信息。该超低频信号发生器采用了主一从式双CPU结构，通过串行通信方式将两个CPU联系起来。从CPU控制产生020Hz频率变化的正弦信号，主CPU控制所产生信号的幅度，并且充分地利用了单片机强大的程序控制和计算功能，采用查表的方法利用软件生成了正弦信号，从而大大地节省了硬件开销，动态地实现了目标信息的模拟。2超低频信号发生器硬件组成及工作过程超低频信号发生器的硬件结构框图如图1所示。三要由以下部分组成：双机通信部分：实现主从CPU的串行通信。D/A转换电路；把8031从单片机送来的正弦二进制数码变成正弦电压，其幅度由D/A转换器2所输出的参考电压控制。正弦信号的幅度控制电路：在8031主单片机控制的控制下产生一定幅度范围内的参考电压。功率放大z把D/A变换送来的正弦电压进行功率放大，驱动雷达天线转动。其工作过程是：由从CPU查询频率存储单元(存放信号频率值)，并开始执行信号生成程序，通过D/A转换器1和两级运算放大器，将数字量变成模拟量，从而得到超低频的正弦信号，其正弦信号的幅度控制由主CPU控制D/A转换器l的参考电压，从而实现正弦信号幅度的控制，正弦信号的频率通过主一从CPU的串行通信由主CPU预置到从CPU的频率存储器单元。3超低频信号发生器的硬件电路设计3.1双机通信部分超低频信号发生器由两个CPU控制，主、从CPU都以MCS一51系列单片机8031为核心，配以锁存器74LS373、和EPROM27128构成单片机最小系统。从CPU主要是产生正弦信号，经过D/A转换和运算放大器，信号形成后经过一级功率放大送到雷达天控系统的相敏检波器，其正弦信号的幅度、频率均受主CPU的控制。主CPU和从CPU之间的通信采用串行通信，通信方式为异步通信，引脚是10(RXD)和110(TXD)，一个是接收，一个是发送。在本系统中主CPU通过串行通信控制从CPU，初始化串行口工作方式1，波特率为1200baud。3.2数模(D/A)转换部分D/A转换部分选用的是DAC0832。DAC0832是CMOS工艺制造的8位单片D/A转换器，属于R-2RT型电阻网络的8位D/A转换器，建立时间150ms，为电流输出型，并且片内带输入数字锁存器。DAC0832与8031接成的是单缓冲方式，由于DAC0832是电流输出，而我们用的是模拟电压，在这种情况下，要将输出的电流转换成电压，转换电路接成同相电压输出形式，其输出电压Vout=IR(1+R2/R1)。在D/A转换电路中，ILE接+5V，片选信号CS和转换控制信号XFER都通过非门连到P2.7，这样输出寄存器和DAC寄存器地址都是7000H，“写”选通线WR1和WR2都和8031的“写”信号线连接，CPU对0832执行一次“写”操作，把一个数据直接写入DAC寄存器，DAC0832的输出模拟信号随之对应变化。这样，由CPU送来的数据SD0SD7，通过DAC0832转换成电流输出，由R4、R5等将电流信号转换成电压信号，经反相放大使得到了所需要的超低频正弦信号。3.3正弦信号的幅度控制电路正弦信号的幅度控制电路如图1所示。由于改变D/A转换器1的VREF脚的电压便能控制输出信号的幅度，因此利用主CPU控制D/A转换器2，使之输出不同幅度的电压，从而去控制D/A转换器1的VREF脚的电压，达到幅度控制的目的。D/A转换器2的参考电压为+5V，其输出模拟电压幅度也可通过硬件进行调节，这样幅度控制范围可以调节。4超低频信号发生器的软件实现超低频信号发生器的软件的编制主要采用的是查表法。对于正弦信号，其每一个点的值的确定方法是：选取半个正弦周期，将半个周期分为254段，取254个点，让其最大值为#FFH，因为所用的0832D/A转换为8位的，这样可以充分保证其转换的精度，同时目是超低频，频率范围在0.0120Hz之间，所以两点之间的延迟时间完全可以满足D/A转换的时间关系。正弦波幅值的计算公式如下：A=100*sin(I*/255)I=1255正弦波的幅度主要采用由主CPU控制D/A转换的参考电压来控制，正弦波频率的变化由改变输出点之间的延时来实现，根据正弦波的周期性和对称性来编制汇编程序，可以很方便地得到幅度和频率都受控的超低频信号。5结论该超低频信号发生器能够动态地实现对雷达跟踪目标信息的模拟，采用了主从式双CPU结构，充分地利用了单片机的软硬件资源，硬件结构简单。目前，该超低频信号发生器已成功地应用于雷达跟踪性能测试上，满足了对天线控制系统频域的开环增益，以及闭环带宽、峰值的测试所需激励信号的要求。DAC0830/DAC08328-Bit P Compatible, Double-Buffered D to A ConvertersGeneral DescriptionThe DAC0830 is an advanced CMOS/Si-Cr 8-bit multiplyingDAC designed to interface directly with the 8080, 8048,8085, Z80, and other popular microprocessors.Adepositedsilicon-chromium R-2R resistor ladder network divides thereference current and provides the circuit with excellent tem-perature tracking characteristics (0.05% of Full Scale Rangemaximum linearity error over temperature). The circuit usesCMOS current switches and control logic to achieve lowpower consumption and low output leakage current errors.Special circuitry provides TTL logic input voltage level com-patibility.Double buffering allows these DACs to output a voltage cor-responding to one digital word while holding the next digitalword. This permits the simultaneous updating of any numberof DACs.The DAC0830 series are the 8-bit members of a family ofmicroprocessor-compatible DACs (MICRO-DAC).Featuresn Double-buffered, single-buffered or flow-through digitaldata inputsn Easy interchange and pin-compatible with 12-bitDAC1230 seriesn Direct interface to all popular microprocessorsn Linearity specified with zero and full scale adjustonly NOT BEST STRAIGHT LINE FIT.n Works with10V reference-full 4-quadrant multiplicationn Can be used in the voltage switching moden Logic inputs which meet TTL voltage level specs (1.4Vlogic threshold)n Operates “STAND ALONE” (without P) if desiredn Available in 20-pin small-outline or molded chip carrierpackageKey Specificationsn Current settling time:1 sn Resolution:8 bitsn Linearity:8, 9, or 10 bits (guaranteed over temp.)n Gain Tempco:0.0002% FS/Cn Low power dissipation:20 mWn Single power supply:5 to 15 VDCTypical ApplicationBI-FETand MICRO-DACare trademarks of National Semiconductor Corporation.Z80is a registered trademark of Zilog Corporation.DS005608-1May 1999DAC0830/DAC0832 8-Bit P Compatible, Double-Buffered D to A Converters 1999 National Semiconductor CorporationDS005608Connection Diagrams(Top Views)Dual-In-Line andSmall-Outline PackagesDS005608-21Molded Chip Carrier PackageDS005608-222Absolute Maximum Ratings(Notes 1, 2)If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.Supply Voltage (VCC)17 VDCVoltage at Any Digital InputVCCto GNDVoltage at VREFInput25VStorage Temperature Range65C to +150CPackage Dissipationat TA=25C (Note 3)500 mWDC Voltage Applied toIOUT1or IOUT2(Note 4)100 mV to VCCESD Susceptability (Note 4)800VLead Temperature (Soldering, 10 sec.)Dual-In-Line Package (plastic)260CDual-In-Line Package (ceramic)300CSurface Mount PackageVapor Phase (60 sec.)215CInfrared (15 sec.)220COperating ConditionsTemperature RangeTMINTATMAXPart numbers with “LCN” suffix0C to +70CPart numbers with “LCWM” suffix0C to +70CPart numbers with “LCV” suffix0C to +70CPart numbers with “LCJ” suffix40C to +85CPart numbers with “LJ” suffix55C to +125CVoltage at Any Digital InputVCCto GNDElectrical CharacteristicsVREF=10.000 VDCunless otherwise noted. Boldface limits apply over temperature, TMINTATMAX. For all other limitsTA=25C.ParameterConditionsSeeNoteVCC= 4.75 VDCVCC= 15.75 VDCVCC= 5 VDC5%VCC= 12 VDC5%to 15 VDC5%LimitUnitsTyp(Note 12)TestedLimit(Note 5)DesignLimit(Note 6)CONVERTER CHARACTERISTICSResolution888bitsLinearity Error MaxZero and full scale adjusted4, 810VVREF+10VDAC0830LJ & LCJ0.050.05% FSRDAC0832LJ & LCJ0.20.2% FSRDAC0830LCN, LCWM &LCV0.050.05% FSRDAC0831LCN0.10.1% FSRDAC0832LCN, LCWM &LCV0.20.2% FSRDifferential NonlinearityZero and full scale adjusted4, 8Max10VVREF+10VDAC0830LJ & LCJ0.10.1% FSRDAC0832LJ & LCJ0.40.4% FSRDAC0830LCN, LCWM &LCV0.10.1% FSRDAC0831LCN0.20.2% FSRDAC0832LCN, LCWM &LCV0.40.4% FSRMonotonicity10VVREFLJ & LCJ488bits+10VLCN, LCWM & LCV88bitsGain Error MaxUsing Internal Rfb70.211% FS10VVREF+10VGain Error Tempco MaxUsing internal Rfb0.00020.0006%FS/CPower Supply RejectionAll digital inputs latched highVCC=14.5V to 15.5V0.00020.0025%11.5V to 12.5V0.0006FSR/V4.5V to 5.5V0.0130.015ReferenceMax152020kInputMin151010kOutput Feedthrough ErrorVREF=20 Vp-p, f=100 kHzAll data inputs latched low3mVp-p3Electrical Characteristics(Continued)VREF=10.000 VDCunless otherwise noted. Boldface limits apply over temperature, TMINTATMAX. For all other limitsTA=25C.ParameterConditionsSeeNoteVCC= 4.75 VDCVCC= 15.75 VDCVCC= 5 VDC5%VCC= 12 VDC5%to 15 VDC5%LimitUnitsTyp(Note 12)TestedLimit(Note 5)DesignLimit(Note 6)CONVERTER CHARACTERISTICSOutput LeakageCurrent MaxIOUT1All data inputsLJ & LCJ10100100nAlatched lowLCN, LCWM & LCV50100IOUT2All data inputsLJ & LCJ100100nAlatched highLCN, LCWM & LCV50100OutputIOUT1All data inputs45pFCapacitanceIOUT2latched low115IOUT1All data inputs130pFIOUT2latched high30DIGITAL AND DC CHARACTERISTICSDigital InputMaxLogic LowLJ:4.75V0.6VoltagesLJ:15.75V0.8LCJ:4.75V0.7VDCLCJ:15.75V0.8LCN, LCWM, LCV0.950.8MinLogic HighLJ & LCJ2.02.0VDCLCN, LCWM, LCV1.92.0Digital InputMaxDigital inputs2.0VLJ & LCJ0.1+10+10ALCN, LCWM, LCV+8+10Supply CurrentMaxLJ & LCJmADrainLCN, LCWM, LCV1.72.0Electrical CharacteristicsVREF=10.000 VDCunless otherwise noted. Boldface limits apply over temperature, TMINTATMAX. For all other limitsTA=25C.SymbolParameterConditionsSeeNoteVCC=15.75 VDCVCC=12 VDC5%to 15 VDC5%VCC=4.75 VDCVCC=5VDC5%LimitUnitsTyp(Note 12)TestedLimit(Note 5)Design Limit(Note 6)Typ(Note 12)TestedLimit(Note 5)DesignLimit(Note 6)AC CHARACTERISTICStsCurrent SettingVIL=0V, VIH=5V1.01.0sTimetWWrite and XFERVIL=0V, VIH=5V11100250375600Pulse Width Min9320320900900tDSData Setup TimeVIL=0V, VIH=5V9100250375600Min320320900900tDHData Hold TimeVIL=0V, VIH=5V93050nsMin3050tCSControl Setup TimeVIL=0V, VIH=5V9110250600900Min32032011001100tCHControl Hold TimeVIL=0V, VIH=5V9001000Min00Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operatingthe device beyond its specified operating conditions.Note 2: All voltages are measured with respect to GND, unless otherwise specified.4Electrical Characteristics(Continued)Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, JA, and the ambient temperature, TA. The maximumallowable power dissipation at any temperature is PD=(TJMAX TA)/JAor the number given in the Absolute Maximum Ratings, whichever is lower. For this device,TJMAX=125C (plastic) or 150C (ceramic), and the typical junction-to-ambient thermal resistance of the J package when board mounted is 80C/W. For the N pack-age, this number increases to 100C/W and for the V package this number is 120C/W.Note 4: For current switching applications, both IOUT1and IOUT2must go to ground or the “Virtual Ground” of an operational amplifier. The linearity error is degradedby approximately VOSVREF. For example, if VREF=10V then a 1 mV offset, VOS, on IOUT1or IOUT2will introduce an additional 0.01% linearity error.Note 5: Tested limits are guaranteed to Nationals AOQL (Average Outgoing Quality Level).Note 6: Guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels.Note 7: Guaranteed at VREF=10 VDCand VREF=1 VDC.Note 8: The unit “FSR” stands for “Full Scale Range.” “Linearity Error” and “Power Supply Rejection” specs are based on this unit to eliminate dependence on a par-ticular VREFvalue and to indicate the true performance of the part. The “Linearity Error” specification of the DAC0830 is “0.05% of FSR (MAX)”. This guarantees thatafter performing a zero and full scale adjustment (see Sections 2.5 and 2.6), the plot of the 256 analog voltage outputs will each be within 0.05%xVREFof a straightline which passes through zero and full scale.Note 9: Boldface tested limits apply to the LJ and LCJ suffix parts only.Note 10: A 100nA leakage current with Rfb=20k and VREF=10V corresponds to a zero error of (100x109x20x103)x100/10 which is 0.02% of FS.Note 11: The entire write pulse must occur within the valid data interval for the specified tW, tDS, tDH, and tSto apply.Note 12: Typicals are at 25C and represent most likely parametric norm.Note 13: Human body model, 100 pF discharged through a 1.5 k resistor.Switching WaveformDS005608-25Definition of Package PinoutsControl Signals(All control signals level actuated)CS:Chip Select (active low). The CS in combinationwith ILE will enable WR1.ILE:Input Latch Enable (active high). The ILE in combi-nation with CS enables WR1.WR1:Write 1. The active low WR1is used to load the digi-tal input data bits (DI) into the input latch. The datain the input latch is latched when WR1is high. Toupdate the input latchCS and WR1must be lowwhile ILE is high.WR2:Write 2 (active low). This signal, in combination withXFER, causes the 8-bit data which is available inthe input latch to transfer to the DAC register.XFER:Transfer control signal (active low). The XFER willenable WR2.Other Pin FunctionsDI0-DI7:Digital Inputs. DI0is the least significant bit (LSB)and DI7is the most significant bit (MSB).IOUT1:DAC Current Output 1. IOUT1is a maximum for adigital code of all 1s in the DAC register, and iszero for all 0s in DAC register.IOUT2:DAC Current Output 2. IOUT2is a constant minusIOUT1, or IOUT1+ IOUT2= constant (I full scale fora fixed reference voltage).Rfb:Feedback Resistor. The feedback resistor is pro-vided on the IC chip for use as the shunt feedbackresistor for the external op amp which is used toprovide an output voltage for the DAC. This on-chip resistor should always be used (not an exter-nal resistor) since it matches the resistors whichare used in the on-chip R-2R ladder and tracksthese resistors over temperature.VREF:Reference Voltage Input. This input connects anexternal precision voltage source to the internalR-2R ladder. VREFcan be selected over the rangeof +10 to 10V. This is also the analog voltage in-put for a 4-quadrant multiplying DAC application.VCC:Digital Supply Voltage. This is the power supplypin for the part. VCCcan be from +5 to +15VDC.Operation is optimum for +15VDCGND:The pin 10 voltage must be at the same groundpotential as IOUT1and IOUT2for current switchingapplications. Any difference of potential (VOSpin10) will result in a linearity change ofFor example, if VREF= 10V and pin 10 is 9mV offset fromIOUT1and IOUT2the linearity change will be 0.03%.Pin 3 can be offset100mV with no linearity change, but thelogic input threshold will shift.Linearity ErrorDefinition of TermsResolution: Resolution is directly related to the number ofswitches or bits within the DAC. For example, the DAC0830has 28or 256 steps and therefore has 8-bit resolution.Linearity Error: Linearity Error is the maximum deviationfrom astraight line passing through the endpoints of theDAC transfer characteristic. It is measured after adjusting forzero and full-scale. Linearity error is a parameter intrinsic tothe device and cannot be externally adjusted.Nationals linearity “end point test” (a) and the “best straightline” test (b,c) used by other suppliers are illustrated above.The “end point test greatly simplifies the adjustment proce-dure by eliminating the need for multiple iterations of check-ing the linearity and then adjusting full scale until the linearityis met. The “end point test guarantees that linearity is metafter a single full scale adjust. (One adjustment vs. multipleiterations of the adjustment.) The “end point test uses astandard zero and F.S. adjustment procedure and is a muchmore stringent test for DAC linearity.Power Supply Sensitivity: Power supply sensitivity is ameasure of the effect of power supply changes on the DACfull-scale output.Settling Time: Settling time is the time required from a codetransition until the DAC output reaches within12LSB of thefinal output value. Full-scale settling time requires a zero tofull-scale or full-scale to zero output change.Full Scale Error: Full scale error is a measure of the outputerror between an ideal DAC and the actual device output.Ideally, for the DAC0830 series, full scale is VREF1LSB.For VREF= 10V and unipolar operation, VFULL-SCALE=10,0000V39mV 9.961V. Full-scale error is adjustable tozero.DS005608-23a) End point test afterzero and fs adj.DS005608-24b) Best straight lineDS005608-25c) Shifting fs adj. to passbest straight line test6Definition of Terms(Continued)Differential Nonlinearity: The difference between any twoconsecutive codes in the transfer curve from the theoretical1 LSB to differential nonlinearity.Monotonic: If the output of a DAC increases for increasingdigital input code, then the DAC is monotonic. An 8-bit DACwhich is monotonic to 8 bits simply means that increasingdigital input codes will produce an increasing analog output.Typical Performance CharacteristicsDS005608-4FIGURE 1. DAC0830 Functional DiagramDigital Input Thresholdvs. TemperatureDS005608-26Digital Input Thresholdvs. VCCDS005608-27Gain and Linearity ErrorVariation vs. TemperatureDS005608-287Typical Performance Characteristics(Continued)DAC0830 Series Application HintsThese DACs are the industrys first microprocessor compat-ible, double-buffered 8-bit multiplying D to A converters.Double-buffering allows the utmost application flexibility froma digital control point of view. This 20-pin device is also pinfor pin compatible (with one exception) with the DAC1230, a12-bit MICRO-DAC. In the event that a systems analog out-put resolution and accuracy must be upgraded, substitutingthe DAC1230 can be easily accomplished. By tying addressbit A0to the ILE pin, a two-byte P write instruction (doubleprecision) which automatically increments the address forthe second byte write (starting with A0=“1”) can be used.This allows either an 8-bit or the 12-bit part to be used withno hardware or software changes. For the simplest 8-bit ap-plication, this pin should be tied to VCC(also see other usesin section 1.1).Analog signal control versatility is provided by a precisionR-2R ladder network which allows full 4-quadrant multiplica-tion of a wide range bipolar reference voltage by an applieddigital word.1.0 DIGITAL CONSIDERATIONSA most unique characteristic of these DACs is that the 8-bitdigital input byte is double-buffered. This means that thedata must transfer through two independently controlled 8-bitlatching registers before being applied to the R-2R laddernetwork to change the analog output. The addition of a sec-ond register allows two useful control features. First, anyDAC in a system can simultaneously hold the current DACdata in one register (DAC register) and the next data word inthe second register (input register) to allow fast updating ofthe DAC output on demand. Second, and probably more im-portant, double-buffering allows any number of DACs in asystem to be updated to their new analog output levels si-multaneously via a common strobe signal.The timing requirements and logic level convention of theregister control signals have been designed to minimize oreliminate external interfacing logic when applied to mostpopular microprocessors and development systems. It iseasy to think of these converters as 8-bit “write-only”memory locations that provide an analog output quantity. Allinputs to these DACs meet TTL voltage level specs and canalso be driven directly with high voltage CMOS logic innon-microprocessor based systems. To prevent damage tothe chip from static discharge, all unused digital inputsshould be tied to VCCor ground. If any of the digital inputsare inadvertantly left floating, the DAC interprets the pin as alogic “1”.1.1 Double-Buffered OperationUpdatingtheanalogoutputoftheseDACsinadouble-buffered manner is basically a two step or doublewrite operation. In a microprocessor system two unique sys-tem addresses must be decoded, one for the input latch con-trolled by the CS pin and a second for the DAC latch whichis controlled by the XFER line. If more than one DAC is beingdriven,Figure 2, the CS line of each DAC would typically bedecoded individually, but all of the converters could share acommon XFER address to allow simultaneous updating ofany number of DACs. The timing for this operation is shown,Figure 3.It is important to note that the analog outputs that will changeafter a simultaneous transfer are those from the DACswhose input register had been modified prior to the XFERcommand.Gain and Linearity ErrorVariation vs. Supply VoltageDS005608-29Write Pulse WidthDS005608-30Data Hold TimeDS005608-318DAC0830 Series Application Hints(Continued)The ILE pin is an active high chip select which can be de-coded from the address bus as a qualifier for the normal CSsignal generated during a write operation. This can be usedto provide a higher degree of decoding unique control sig-nals for a particular DAC, and thereby create a more efficientaddressing scheme.Another useful application of the ILE pin of each DAC in amultiple DAC system is to tie these inputs together and usethis as a control line that can effectively “freeze” the outputsof all the DACs at their present value. Pulling this line lowlatches the input register and prevents new data from beingwritten to the DAC. This can be particularly useful in multi-processing systems to allow a processor other than the onecontrolling the DACs to take over control of the data bus andcontrol lines. If this second system were to use the same ad-dresses as those decoded for DAC control (but for a differentpurpose) the ILE function would prevent the DACs from be-ing erroneously altered.In a “Stand-Alone” system the control signals are generatedby discrete logic. In this case double-buffering can be con-trolled by simply taking CS and XFER to a logic “0”, ILE to alogic “1” and pulling WR1low to load data to the input latch.Pulling WR2low will then update the analog output. A logic“1” on either of these lines will prevent the changing of theanalog output.DS005608-35*TIE TO LOGIC 1 IF NOT NEEDED (SEE SEC. 1.1).FIGURE 2. Controlling Mutiple DACsDS005608-36FIGURE 3.9DAC0830 Series Application Hints(Continued)1.2 Single-Buffered OperationIn a microprocessor controlled system where maximum datathroughput to the DAC is of primary concern, or when onlyone DAC of several needs to be updated at a time, asingle-buffered configuration can be used. One of the two in-ternal registers allows the data to flow through and the otherregister will serve as the data latch.Digital signal feedthrough (see Section 1.5) is minimized ifthe input register is used as the data latch. Timing for thismode is shown inFigure 4.Single-buffering in a “stand-alone” system is achieved bystrobing WR1low to update the DAC with CS, WR2andXFER grounded and ILE tied high.1.3 Flow-Through OperationThough primarily designed to provide microprocessor inter-face compatibility, the MICRO-DACs can easily be config-ured to allow the analog output to continuously reflect thestate of an applied digital input. This is most useful in appli-cations where the DAC is used in a continuous feedbackcontrol loop and is driven by a binary up-down counter, or infunction generation circuits where a ROM is continuouslyproviding DAC data.Simply grounding CS, WR1, WR2, and XFER and tying ILEhigh allows both internal registers to follow the applied digitalinputs (flow-through) and directly affect the DAC analog out-put.1.4 Control Signal TimingWhen interfacing these MICRO-DAC to any microprocessor,there are two important time relationships that must be con-sidered to insure proper operation. The first is the minimumWR strobe pulse width which is specified as 900 ns for allvalid operating conditions of supply voltage and ambienttemperature, but typically a pulse width of only 180ns is ad-equate if VCC=15VDC. A second consideration is that theguaranteed minimum data hold time of 50ns should be metor erroneous data can be latched. This hold time is definedas the length of time data must be held valid on the digital in-putsaftera qualified (via CS) WR strobe makes a low to hightransition to latch the applied data.If the controlling device or system does not inherently meetthese timing specs the DAC can be treated as a slowmemory or peripheral and utilize a technique to extend thewrite strobe. A simple extension of the write time, by addinga wait state, can simultaneously hold the write strobe activeand data valid on the bus to satisfy the minimum WR pulse-width. If this does not provide a sufficient data hold time atthe end of the write cycle, a negative edge triggeredone-shot can be included between the system write strobeand the WR pin of the DAC. This is illustrated inFigure 5foran exemplary system which provides a 250ns WR strobetime with a data hold time of less than 10ns.The proper data set-up time prior to the latching edge (LO toHI transition) of the WR strobe, is insured if the WR pulse-width is within spec and the data is valid on the bus for theduration of the DAC WR strobe.1.5 Digital Signal FeedthroughWhen data is latched in the internal registers, but the digitalinputs are changing state, a narrow spike of current may flowout of the current output terminals. This spike is caused bythe rapid switching of internal logic gates that are respondingto the input changes.There are several recommendations to minimize this effect.When latching data in the DAC, always use the input registeras the latch. Second, reducing the VCCsupply for the DACfrom +15V to +5V offers a factor of 5 improvement in themagnitude of the feedthrough, but at the expense of internallogic switching speed. Finally, increasing CC(Figure 8) to avalue consistent with the actual circuit bandwidth require-ments can provide a substantial damping effect on any out-put spikes.DS005608-7ILE=LOGIC “1”; WR2 and XFER GROUNDEDFIGURE 4.10DAC0830 Series Application Hints(Continued)2.0 ANALOG CONSIDERATIONSThe fundamental purpose of any D to A converter is to pro-vide an accurate analog output quantity which is representa-tive of the applied digital word. In the case of the DAC0830,the output, IOUT1, is a current directly proportional to theproduct of the applied reference voltage and the digital inputword. For application versatility, a second output, IOUT2, isprovided as a current directly proportional to the complementof the digital input. Basically:where the digital input is the decimal (base 10) equivalent ofthe applied 8-bit binary word (0 to 255), VREFis the voltageat pin 8 and 15 k is the nominal value of the internal resis-tance, R, of the R-2R ladder network (discussed in Section2.1).Several factors external to the DAC itself must be consid-ered to maintain analog accuracy and are covered in subse-quent sections.2.1 The Current Switching R-2R LadderThe analog circuitry,Figure 6, consists of a silicon-chromium(SiCr or Si-chrome) thin film R-2R ladder which is depositedon the surface oxide of the monolithic chip. As a result, thereare no parasitic diode problems with the ladder (as theremay be with diffused resistors) so the reference voltage,VREF, can range 10V to +10V even if VCCfor the device is5VDC.The digital input code to the DAC simply controls the positionof the SPDT current switches and steers the available laddercurrent to either IOUT1or IOUT2as determined by the logic in-put level (“1” or “0”) respectively, as shown inFigure 6. TheMOS switches operate in the current mode with a small volt-age drop across them and can therefore switch currents ofeither polarity. This is the basis for the 4-quadrant multiplyingfeature of this DAC.2.2 Basic Unipolar Output VoltageTo maintain linearity of output current with changes in the ap-plied digital code, it is important that the voltages at both ofthe current output pins be as near ground potential (0VDC)as possible. With VREF=+10V every millivolt appearing at ei-ther IOUT1or IOUT2will cause a 0.01% linearity error. In mostapplications this output current is converted to a voltage byusing an op amp as shown inFigure 7.The inverting input of the op amp is a “virtual ground” createdby the feedback from its output through the internal 15 k re-sistor, Rfb. All of the output current (determined by the digitalinput and the reference voltage) will flow through Rfbto theoutput of the amplifier. Two-quadrant operation can be ob-tained by reversing the polarity of VREFthus causing IOUT1toflow into the DAC and be sourced from the output of the am-plifier. The output voltage, in either case, is always equal toIOUT1xRfband is the opposite polarity of the reference volt-age.The reference can be either a stable DC voltage source oran AC signal anywhere in the range from 10V to +10V. TheDAC can be thought of as a digitally controlled attenuator:the output voltage is always less than or equal to the appliedreference voltage. The VREFterminal of the device presentsa nominal impedance of 15 k to ground to external circuitry.Always use the internal Rfbresistor to create an output volt-age since this resistor matches (and tracks with tempera-ture) the value of the resistors used to generate the outputcurrent (IOUT1).DS005608-8FIGURE 5. Accommodating a High Speed System11DAC0830 Series Application Hints(Continued)2.3 Op Amp ConsiderationsThe op amp used inFigure 7should have offset voltage null-ing capability (See Section 2.5).The selected op amp should have as low a value of inputbias current as possible. The product of the bias currenttimes the feedback resistance creates an output voltage er-ror which can be significant in low reference voltage applica-tions. BI-FETop amps are highly recommended for usewith these DACs because of their very low input current.Transient response and settling time of the op amp are im-portant in fast data throughput applications. The largest sta-bility problem is the feedback pole created by the feedbackresistance, Rfb, and the output capacitance of the DAC. Thisappears from the op amp output to the () input and includesthe stray capacitance at this node. Addition of a lead capaci-tance, CCinFigure 8, greatly reduces overshoot and ringingat the output for a step change in DAC output current.Finally, the output voltage swing of the amplifier must begreater than VREFto allow reaching the full scale output volt-age. Depending on the loading on the output of the amplifierand the available op amp supply voltages (only12 volts inmany development systems), a reference voltage less than10 volts may be necessary to obtain the full analog outputvoltage range.2.4 Bipolar Output Voltage with a Fixed ReferenceThe addition of a second op amp to the previous circuitry canbe used to generate a bipolar output voltage from a fixed ref-erence voltage. This, in effect, gives sign significance to theMSB of the digital input word and allows two-quadrant multi-plication of the reference voltage. The polarity of the refer-ence can also be reversed to realize full 4-quadrant multipli-cation:VREFxDigital Code=VOUT. This circuit is showninFigure 9.This configuration features several improvements over exist-ing circuits for bipolar outputs with other multiplying DACs.Only the offset voltage of amplifier 1 has to be nulled to pre-serve linearity of the DAC. The offset voltage error of thesecond op amp (although a constant output voltage error)has no effect on linearity. It should be nulled only if absoluteoutput accuracy is required. Finally, the values of the resis-tors around the second amplifier do not have to match the in-ternal DAC resistors, they need only to match and tempera-ture track each other. A thin film 4-resistor network availablefrom Beckman Instruments, Inc. (part no. 694-3-R10K-D) isideally suited for this application. These resistors arematched to 0.1% and exhibit only 5 ppm/C resistance track-ing temperature coefficient. Two of the four available 10 kresistors can be paralleled to form R inFigure 9and theother two can be used independently as the resistances la-beled 2R.2.5 Zero AdjustmentFor accurate conversions, the input offset voltage of the out-put amplifier must always be nulled. Amplifier offset errorscreate an overall degradation of DAC linearity.The fundamental purpose of zeroing is to make the voltageappearing at the DAC outputs as near 0VDCas possible.This is accomplished for the typical DAC op amp connec-tion (Figure 7) by shorting out Rfb, the amplifier feedback re-sistor, and adjusting the VOSnulling potentiometer of the opamp until the output reads zero volts. This is done, of course,with an applied digital code of all zeros if IOUT1is driving theop amp (all ones for IOUT2). The short around Rfbis then re-moved and the converter is zero adjusted.DS005608-37FIGURE 6.DS005608-38FIGURE 7.12DAC0830 Series Application Hints(Continued)2.6 Full-Scale AdjustmentIn the case where the matching of Rfbto the R value of theR-2R ladder (typically0.2%) is insufficient for full-scale ac-curacy in a particular application, the VREFvoltage can beadjusted or an external resistor and potentiometer can beadded as shown inFigure 10to provide a full-scale adjust-ment.The temperature coefficients of the resistors used for this ad-justment are of an important concern. To prevent degrada-tion of the gain error temperature coefficient by the externalresistors, their temperature coefficients ideally would have tomatch that of the internal DAC resistors, which is a highly im-practical constraint. For the values shown inFigure 10, if theresistor and the potentiometer each had a temperature coef-ficient of100 ppm/C maximum, the overall gain error tem-perature coefficent would be degraded a maximum of0.0025%/C for an adjustment pot setting of less than 3% ofRfb.DS005608-39tsOP AmpCC(O to Full Scale)LF35622 pF4 sLF35122 pF5 sLF357*10 pF2 s*2.4 k RESISTOR ADDED FROMINPUT TO GROUND TOINSURE STABILITYFIGURE 8.DS005608-40Input CodeIDEAL VOUTMSBLSB+VREFVREF111111111100000010000000011111110011111100000000*THESE RESISTORS ARE AVAILABLE FROM BECKMAN INSTRUMENTS, INC. AS THEIR PART NO. 694-3-R10K-DFIGURE 9.13DAC0830 Series Application Hints(Continued)2.7 Using the DAC0830 in a Voltage SwitchingConfigurationThe R-2R ladder can also be operated as a voltage switch-ing network. In this mode the ladder is used in an invertedmanner from the standard current switching configuration.The reference voltage is connected to one of the current out-put terminals (IOUT1for true binary digital control, IOUT2is forcomplementary binary) and the output voltage is taken fromthe normal VREFpin. The converter output is now a voltagein the range from 0V to 255/256 VREFas a function of the ap-plied digital code as shown inFigure 11.This configuration offers several useful application advan-tages. Since the output is a voltage, an external op amp isnot necessarily required but the output impedance of theDAC is fairly high (equal to the specified reference input re-sistance of 10 k to 20 k) so an op amp may be used forbuffering purposes. Some of the advantages of this modeare illustrated inFigures 12, 13, 14, 15.There are two important things to keep in mind when usingthis DAC in the voltage switching mode. The applied refer-ence voltage must be positive since there are internal para-sitic diodes from ground to the IOUT1and IOUT2terminalswhich would turn on if the applied reference went negative.There is also a dependence of conversion linearity and gainerror on the voltage difference between VCCand the voltageapplied to the normal current output terminals. This is a re-sult of the voltage drive requirements of the ladder switches.To ensure that all 8 switches turn on sufficiently (so as not toadd significant resistance to any leg of the ladder andthereby introduce additional linearity and gain errors) it isrecommended that the applied reference voltage be keptless than +5VDCand VCCbe at least 9V more positive thanVREF. These restrictions ensure less than 0.1% linearity andgain error change.Figures 16, 17, 18characterize the ef-fects of bringing VREFand VCCcloser together as well astypical temperature performance of this voltage switchingconfiguration.DS005608-11FIGURE 10. Adding Full-Scale AdjustmentDS005608-12FIGURE 11. Voltage Mode SwitchingDS005608-41Voltage switching mode eliminates output signal inver-sion and therefore a need for a negative power supply.Zero code output voltage is limited by the low level outputsaturation voltage of the op amp. The 2 k pull-down re-sistor helps to reduce this voltage.VOSof the op amp has no effect on DAC linearity.FIGURE 12. Single Supply DAC14DAC0830 Series Application Hints(Continued)DS005608-42FIGURE 13. Obtaining a Bipolar Output from a FixedReference with a Single Op AmpDS005608-60FIGURE 14. Bipolar Output with Increased Output Voltage Swing15DAC0830 Series Application Hints(Continued)DS005608-14FIGURE 15. Single Supply DAC with Level Shift and Span-Adjustable OutputGain and Linearity ErrorVariation vs. Supply VoltageDS005608-32Note: For these curves, VREFis the voltage applied to pin 11 (IOUT1) withpin 12 (IOUT2) grounded.FIGURE 16.Gain and Linearity ErrorVariation vs. Reference VoltageDS005608-33FIGURE 17.16DAC0830 Series Application Hints(Continued)2.8 Miscellaneous Application HintsThese converters are CMOS products and reasonable careshould be exercised in handling them to prevent catastrophicfailures due to static discharge.Conversion accuracy is only as good as the applied refer-ence voltage so providing a stable source over time and tem-perature changes is an important factor to consider.A “good” ground is most desirable. A single point ground dis-tribution technique for analog signals and supply returnskeeps other devices in a system from affecting the output ofthe DACs.During power-up supply voltage sequencing, the 15V (or12V) supply of the op amp may appear first. This will causethe output of the op amp to bias near the negative supply po-tential. No harm is done to the DAC, however, as the on-chip15 k feedback resistor sufficiently limits the current flowfrom IOUT1when this lead is internally clamped to one diodedrop below ground.Careful circuit construction with minimization of lead lengthsaround the analog circuitry, is a primary concern. Good highfrequency supply decoupling will aid in preventing inadvert-ant noise from appearing on the analog output.Overall noise reduction and reference stability is of particularconcern when using the higher accuracy versions, theDAC0830 and DAC0831, or their advantages are wasted.3.0 GENERAL APPLICATION IDEASThe connections for the control pins of the digital input regis-ters are purposely omitted. Any of the control formats dis-cussed in Section 1 of t