交通灯控制器课程设计报告.doc

电气与信息工程学院本科生课程设计湖南大学电气与信息工程学院本科生课程设计题目： 交通灯控制器课程： 数电课程设计专业：自动化专业班级：学号：姓名：设计时间： 20目录一、 设计目的二、 设计要求三、 设计原理四、 设计程序五、设计心得一、 设计目的1、用红、绿、黄三色发光二极管做信号灯，主干道a为东西向，设红、绿、黄三色灯为ar、ag、ay；支干道b喂南北向。三色灯为br、bg、by。2、主干道车辆较多，所以亮绿灯的时间设为50s；支干道亮绿灯的时间设为30s。当主干道允许通行亮绿灯时则支干道亮红灯；相反，支干道允许通行亮绿灯时则主干道亮红灯。每次由绿灯转变为红灯时，其间要亮5s的黄灯作为过渡，以便行驶中的车辆有时间停到禁止线以内。3、交通灯正常运行时，用4位数码管m1、m2、m3、m4显示主干道和支干道的倒计时时间，m1、m2显示主干道在当前状态剩余时间；m3、m4显示支干道在当前状态的剩余时间。4、能实现系统总清0，清0后计数器由出事状态开始计数。指示灯指示主干道亮绿灯。5、具有一定的扩展功能： 它能实现特殊状态的功能先死，用开关s作为特殊信号传感器，s为1时进入特殊状态并实现下列特殊状态功能： 1）显示器m1、m2、m3、m4闪烁，即在全0和当前计时时间中交替显示。 2）计数器停止计数并保持原来的时间数据。 3）东西、南北方向的三色灯全显示为红色状态。 4）特殊状态解除后能继续返回正常工作状态。 5）进入特殊状态时，音响电路发出急促的“嘀嘟”声，以示警告。二、设计要求 1、分析设计任务，拟定多种设计方案，根据当时的制作条件，选定其中的一种方案绘制系统框图和设计流程。 2、设计各部分单元电路或编写vhdl描述程序。计算元器件参数、确定元器件幸好和数量，提出元器件清单。 3、安装调试硬件电路，或制作以cpld/fpga为基础的专用集成电路芯片asic。 4、对制作的电路进行功能测试，分析各项技术指标；或对设计的电路进行功能仿真，分析仿真波形。对asic电路做硬件测试或脱机运行。 5、总结设计资料，打印包括原理电路（或vhdl描述）、仿真波形的设计报告，交验并演示电路装置三、设计原理 1、系统设计原理框图 交通灯控制器原理框图如下，包括置数模块、主控制器模块、译码器模块和数据选择器模块几个部分。置数模块将交通灯的点亮时间初值预置到置数电路中，预置的具体数据则由控制器当前的状态决定，即点亮不同颜色的灯则置入不同的值。计数器电路则根据预置的初值做减1操作，当减到零时则预置时间到；又使主控制器的状态发生变化，启动计时电路进入下一个状态的倒计时。译码器模块将主控制电路的当前状态译码为红、绿、黄三色信号灯的点亮信号。整个电路的核心是主控制器。南北方向显示器东西方向显示器时钟信号1hz清0（cr）特殊状态sbrbybgagayar主控制器十位个位译码器译码器mux接地计数器a置数器a十位个位译码器译码器mux接地计数器b置数器b分频器绿 黄 红 红 黄 绿交通灯控制器原理框图2、主控制器 主控制器决定控制电路状态变化的顺序。主控制器的输入信号有：控制器目前状态s1s0，特殊情况输入信号s、50s计时时间到信号t50,30s计时时间到信号t30，输出信号是控制器的次态z1z0。可直接设计为时序电路，也可以先设计为组合电路后加接触发器，下图是主控电路的框图。主控制器原理框图ffc1ffc0s0 z0s1 z1 st30t50 s0s1 st30t50cpclrd qc clrd qc clrz0z1四、设计程序 library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity tr_m is port ( rst : in std_logic; clk : in std_logic; s : in std_logic; speak:out std_logic; bcd_out : out std_logic_vector (7 downto 0); bcdout : out std_logic_vector (7 downto 0); led: out std_logic_vector (7 downto 0);end tr_m;architecture behavioral of tr_m istype numstate is (s1gr,s2yr,s3rg,s4ry,s5rr,s6rr);signal state : numstate;signal sbcd_out : std_logic_vector (7 downto 0);constant c1: std_logic_vector (7 downto 0) :=x55;constant c3: std_logic_vector (7 downto 0) :=x35;signal state_tem: numstate;signal sled : std_logic_vector (7 downto 0) ;signal n:std_logic;beginled=sled;process(clk,rst)begin if(rst=1) then n=1; elsif(rising_edge(clk) then if(sbcd_out=x55) then bcd_out=x50; bcdout=x55; elsif sbcd_out=x35 then bcd_out=x35; bcdout=x0 and sbcd_out(3 downto 0)=x4) then bcd_out = sbcd_out-x6-5; else bcd_out = sbcd_out-5; end if; bcdout = sbcd_out; elsif(sled=x21) then bcd_out = sbcd_out; bcdout =x0 and sbcd_out(3 downto 0)=x4) then bcdout = sbcd_out-x6-5; else bcdout = sbcd_out-5; end if; bcd_out = sbcd_out; elsif(sled=x12) then bcd_out = sbcd_out; bcdout = sbcd_out; elsif(sled=x11 and n=1 and s=1) then n=0; bcd_out = x00; bcdout = x00; elsif(sled=x11 and n=0 and s=1) then n=x0 and sbcd_out(3 downto 0)=x4) then bcdout = sbcd_out-x6-5; else bcdout = sbcd_out-5; end if; bcd_out =x0 and sbcd_out(3 downto 0)=x4) then bcd_out = sbcd_out-x6-5; else bcd_out = sbcd_out-5; end if; bcdout = sbcd_out; else bcd_out = sbcd_out; bcdout =x0 and sbcd_out(3 downto 0)=x4) then bcdout = sbcd_out-x6-5; else bcdout = sbcd_out-5; end if; bcd_out =x0 and sbcd_out(3 downto 0)=x4) then bcd_out = sbcd_out-x6-5; else bcd_out = sbcd_out-5; end if; bcdout = sbcd_out; else bcd_out = sbcd_out; bcdout = sbcd_out; end if; end if; end if;end process;cntproc: process(rst,clk,state_tem)beginif rst=1 then sbcd_out=c1;elsif rising_edge(clk) then if s=1 then sbcd_out=sbcd_out; elsif sbcd_out=1 then if sled=x12 then sbcd_out=c1; elsif sled=x21 then sbcd_out=c3; end if; elsif sbcd_out(3 downto 0)=0 then sbcd_out = sbcd_out-7; else sbcd_out = sbcd_out-1; end if;end if;end process;stateproc: process(rst,clk)begin if rst=1 then state=s1gr; state_tem=s1gr; elsif rising_edge(clk) then if s=1 and n=1 then state=s5rr; elsif s=1 and n=0 then state=s6rr; elsif sled=x11 then state=state_tem; elsif sbcd_out=x06 then if sled=x41 then state=s2yr; state_tem=s2yr; elsif sled=x14 then state=s4ry; state_tem=s4ry; end if; elsif sbcd_out=x01 then if sled=x21 then state=s3rg; state_tem=s3rg; elsif sled=x12 then state=s1gr; state_tem sled=x41; speak sled=x21; speak sled=x14; speak sled=x12; speak sled=x11; speak sled=x11; speak null;end case;end if;end process;end behavioral; - company:- engineer:- create date: 14:56:21 05/13/2012- design name:- module name: jiaotongdeng - behavioral- project name:- target devices:- tool versions:- description:- dependencies:- revision:- revision 0.01 - file created- additional comments:-library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;- uncomment the following library declaration if instantiating- any xilinx primitives in this code.-library unisim;-use unisim.vcomponents.all;entity jiaotongdeng is port ( clk : in std_logic; rst : in std_logic; s : in std_logic; ar : out std_logic; ag : out std_logic; ay : out std_logic; br : out std_logic; bg : out std_logic; by : out std_logic; bcd_out : out std_logic_vector (7 downto 0); sound : out std_logic);end jiaotongdeng;architecture behavioral of jiaotongdeng istype numstate is (s1gr,s2yr,s3rg,s4ry);signal state: numstate;signal sbcd_out: std_logic_vector (7 downto 0);signal sar : std_logic;signal sag : std_logic;signal say : std_logic;signal sbr : std_logic;signal sbg : std_logic;signal sby : std_logic;signal ssound:std_logic;beginbcd_out=sbcd_out;ar=sar;ag=sag;ay=say;br=sbr;bg=sbg;by=sby;sound=ssound;out_process:process(state,clk,s)beginif s=1 then sar=1; sag=0; say=0; sbr=1; sbg=0; sby=0; ssound=1;elsif rising_edge(clk) then if state=s1gr then sar=0; sag=1; say=0; sbr=1; sbg=0; sby=0; ssound=0; elsif state=s2yr then sar=0; sag=0; say=1; sbr=1; sbg=0; sby=0; ssound=0; elsif state=s3rg then sar=1; sag=0; say=0; sbr=0; sbg=1; sby=0; ssound=0; elsif state=s4ry then sar=1; sag=0; say=0; sbr=0; sbg=0; sby=1; ssound=0; end if;end if;end process;sbcd_process:process(clk,rst,s)beginif s=1 then sbcd_out=sbcd_out;elsif rst=1 then sbcd_out=x55;elsif rising_edge(clk) then if sbcd_out=1 then if state=s4ry then sbcd_out=x55; elsif state=s2yr then sbcd_out=x35; end if; elsif sbcd_out(3 downto 0)=0 then sbcd_out = sbcd_out-7; else sbcd_out = sbcd_out-1; end if;end if;end process;state_process:process(clk,rst)beginif rst=1 then state=s1gr;elsif rising_edge(clk) then if sbcd_out=x06 then if state=s1gr then state=s2yr; elsif state=s3rg then state=s4ry; end if; elsif sbcd_out=x01 then if state=s2yr then state=s3rg; elsif state=s4ry then state=s1gr; end if; end if;end if;end process;end behavioral; library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity alarm isport( clk,rst: in std_logic; alarm : in std_logic; div : out std_logic);end alarm;architecture arct of alarm issignal cnt : natural range 0 to 200000 ;signal div_r : std_logic;beginprocess(div_r)begindiv = div_r;end process;process(clk,rst)beginif(rst = 1) then cnt = 0; div_r = 0;elsif(rising_edge(clk) then if(alarm = 1) then if(cnt = 200000) then div_r = not div_r; cnt = 0; else cnt = cnt + 1; end if; else if(alarm=0) then div_r=0; end if; end if;end if;end process;end arct;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity jtdlcd is port (cpin,r,busy :in std_logic; ew,sn :in std_logic_vector(7 downto 0); ewryg,snryg : in std_logic_vector(2 downto 0); clk,rst,strobe,outline : out std_logic; data : out std_logic_vector(7 downto 0); addr : out std_logic_vector(3 downto 0) );end entity ;architecture jgt of jtdlcd is type states is (s0,s1,s2,s3,s4); signal s: states; signal lcdpt : integer range 0 to 10; signal cpct : integer range 0 to 65535; signal cp: std_logic; signal ascew,ascsn : std_logic_vector(7 downto 0);beginprocess(cpin,r)beginclk=cpin;if r=1 then cpct=65535;elsif cpin=1 and cpin event then if cpct=0 then cpct=65535;cp=not cp; else cpct=cpct-1; end if;end if;end process; process(cp,r)beginif r=1 then s=s0;lcdpt=0;rst s=s1;lcdpt=0;rst rst=0;strobe=0; if busy=0 then lcdpt=lcdpt+1; if lcdpt=5 then s=s3; else s s=s1;strobe strobe=0; if busy=0 then if lcdpt=10 then lcdpt=5; else lcdpt=lcdpt+1; end if; s strobe=1;s null; end case;end if; end process;process(lcdpt)begincase lcdpt iswhen 0 = null;when 1= data=01000101;addr=0101;outline data=01010111;addr=0110;outline data=01010011;addr=1001;outline data=01001110;addr=1010;outlinedata=0011&ew(7 downto 4);addr=0101;outlinedata=0011&ew(3 downto 0);addr=0110;outlinedata=ascew;addr=0100;outlinedata=0011&sn(7 downto 4);addr=1001;outlinedata=0011&sn(3 downto 0);addr=1010;outlinedata=ascsn;addr=1000;outline null;end case;end process;process(ewryg)begincase ewryg iswhen 100 = ascew ascew ascew null;end case;end process;process(snryg)begincase snryg iswhen 100 = ascsn ascsn ascsn null;end case;end process; end architecture jgt;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;- uncomment the following library declaration if using- arithmetic functions with signed or unsigned values-use ieee.numeric_std.all;- uncomment the following library declaration if instantiating- any xilinx primitives in this code.-library unisim;-use unisim.vcomponents.all;entity fengmingming_main is port ( clk_1 : in std_logic; clk_2 : in std_logic; s_main : in std_logic; out_cp : out std_logic; clk_main : in std_logic);end fengmingming_main;architecture behavioral of fengmingming_main issignal sjudje_1: std_logic:=0;signal sjudje_2: std_logic:=0;signal scomplete: std_logic:=0;signal sout_cp:std_logic:=0;beginout_cp=sout_cp;process(s_main,clk_main,clk_1,clk_2)begin if s_main=1 and scomplete=0 then if rising_edge(clk_main) then if sjudje_1=0 then sjudje_1=1; elsif sjudje_2=0 and sjudje_1=1 then sjudje_2=1; elsif sjudje_1=1 and sjudje_2=1 then scomplete=1; sout_cp=0; end if; else sjudje_1=sjudje_1;sjudje_2=sjudje_2;scomplete=scomplete; end if; if sjudje_1=1 and sjudje_2=0 then sout_cp=clk_1; elsif sjudje_2=1 and sjudje_1=1 then sout_cp=clk_2; end if; elsif s_main=0 then scomplete=0;sjudje_1=0;sjudje_2=0; sout_cp=0; end if;end process;end behavioral;- company:- engineer:- create date: 15:25:56 06/25/2012- design name:- module name: freq_div - behavioral- project name:- target devices:- tool versions:- description:- dependencies:- revision:- revision 0.01 - file created- additional comments:-library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;- uncomment the following library declaration if using- arithmetic functions with signed or unsigned values-use ieee.numeric_std.all;- uncomment the following library declaration if instantiating- any xilinx primitives in this code.-library unisim;-use unisim.vcomponents.all;entity freq_div is port ( clkin : in std_logic; rst : in std_logic; alarm : in std_logic; div : out std_logic);end freq_div;architecture behavioral of freq_div istype numstate is (s0,s1);signal state_curr,state_next:numstate;signal sdiv_1 : std_logic;signal sdiv_2 : std_logic;signal cnt_1 :integer range 0 to 30000;signal cnt_2 :integer range 0 to 30000;-signal t1:integer range 0 to 30000;constant rate_1 :integer :=5000; - 10m/5000 = 2000hzconstant rate_2 :integer :=25000; - 10m/25000 = 400hzconstant freq :integer :=1500000; - 4beginwith state_curr select div = sdiv_1 when s0, sdiv_2 when s1, u when others;wave_1:process(clkin,rst,alarm)begin if rst = 1 then sdiv_1 = 0; else if ( rising_edge(clkin) ) then if ( cnt_1 = rate_1 ) then cnt_1 = 0; sdiv_1 = not sdiv_1; else cnt_1 = cnt_1 + 1; end if; end if; if alar