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级学生毕业设计（论文）中期报告系别班级学生姓名指导教师课题名称：多功能工业控制平台简述开题以来所做的具体工作、取得的进展及下一步主要工作：所做的工作：1. 在图书馆和网络上查找相关资料，了解MSP430F149单片机的功能和工程开发的应用，为深入研究做好准备。2. 查找各器件的管脚图及其原理，列元件清单，购买器件。3. 根据之前的准备进行电路的焊接工作，从元器件的特性，电路的外观上合理的布局，完成硬件电路焊接。 4.对电路进行调试。 取得的进展：各模块电路已基本实现，获得的指标和设想差距不大。下一步的主要工作：1. 解决调试中出现的问题，并且分析其原因。2. 记录调试数据，整理资料，准备写论文。3. 总结之前所作的工作，为毕业答辩做好充分的准备。 学生签字： 年 月 日指导教师的建议与要求： 设计思路清晰，进度安排合理，同时希望在以后的制作过程中要抓紧时间完成后期的工作。 指导教师签字： 年 月 日英文资料及中文翻译1英文资料The Design of a Rapid Prototype Platform for ARM Based Embedded SystemHardware prototype is a vital step in the embedded system design. In this paper, we discuss our design of a fast prototyping platform for ARM based embedded systems, providing a low-cost solution to meet the request of flexibility and testability in embedded system prototype development. It also encourages concurrent development of different parts of system hardware as well as module reusing. Though the fast prototyping platform is designed for ARM based embedded system, our idea is general and can be applied to embedded system of other types. I.INTRODUCTIONEmbedded systems are found everywhere, including in cellular telephones, pagers, VCRs, camcorders, thermostats, curbside rental-car check-in devices, automated supermarket stockers, computerized inventory control devices, digital thermometers, telephone answering machines, printers, portable video games, TV set-top boxes - the list goes on. Demand for embedded system is large, and is growing rapidly. In order to deliver correct-the-first-time products with complex system requirements and time-to-market pressure, design verification is vital in the embedded system design process. A possible choice for verification is to simulate the system being designed. If a high-level model for the system is used, simulation is fast but may not be accurate enough, with a low-level model too much time may be required to achieve the desired level of confidence in the quality of the evaluation. Since debugging of real systems has to take into account the behavior of the target system as well as its environment, runtime information is extremely important. Therefore, static analysis with simulation methods is too slow and not sufficient. And simulation cannot reveal deep issues in real physical system. A hardware prototype is a faithful representation of the final design, guarantying its real-time behavior. And it is also the basic tool to find deep bugs in the hardware. For these reasons, it has become a crucial step in the whole design flow. Traditionally, a prototype is designed similarly to the target system with all the connections fixed on the PCB (printed circuit boards).As embedded systems are getting more complex, the needs for thorough testing become increasingly important. Advances in surface-mount packaging and multiple-layer PCB fabrication have resulted in smaller boards and more compact layout, making traditional test methods, e.g., external test probes and bed-of-nails test fixtures, harder to implement. As a result, acquiring signals on boards, which is beneficial to hardware testing and software development, becomes infeasible, and tracking bugs in prototype becomes increasingly difficult. Thus the prototype design has to take account of testability. However, simply adding some test points is not enough. If errors on the prototype are detected, such as misconnections of signals, it could be impossible to correct them on the multiple-layer PCB board with all the components mounted. All these would lead to another round of prototype fabrication, making development time extend and cost increase.Besides testability, it is important to maintain high flexibility during development of the prototype as design specification changes are common. Nowadays complex systems are often not built from scratch but are assembled by reusing previously designed modules or off-the-shelf components such as processors, memories or peripheral circuitry in order to cope with more aggressive time-to-market constraints. Following the top-down design methodology, lots of effort in the design process is spent on decomposing the customers, requirements into proper functional modules and interfacing them to compose the target system.Some previous research works have suggested that FPLDs (field programmable logic device) could be added to the final design to provide flexibility as FPLDs can offer programmable interconnections among their pins and many more advantages. However, extra devices may increase production cost and power dissipation, weakening the market competition power of the target system. To address these problems, there are also suggestions that FPLDs could be used in hardware prototype as an intermediate approach 1-3, whereas this would still bring much additional work to the prototype design. Moreover, modules on the prototype cannot be reused directly. In industry, there have been companies that provide commercial solutions based on FPLDs for rapid prototyping 4. Their products are aimed at SOC (system on a chip) functional verification instead of embedded system design and development.In this paper, we discuss our design of a Rapid Prototyping Platform for ARM based Embedded System, providing a low cost solution to meet the request of flexibility and testability in embedded system prototype development. It also encourages concurrent development of different parts of system hardware as well as module reusing. The rest of the paper is organized as follows. In section 2, we discuss the details of our rapid prototyping platform. Section 3 shows the experimental results, followed by an overall conclusion in section 4.II. THE DESIGN OF A RAPID PROTOTYPING PLATFORMA. OverviewARM based embedded processors are wildly used in embedded systems due to their low-cost, low-power consumption and high performance. An ARM based embedded processor is a highly integrated SOC including an ARM core with a variety of different system peripherals5. Many arm based embedded processors, e.g.6-8, adopt a similar architecture as the one shown in Fig. 1.The integrated memory controller provides an external memory bus interface supporting various memory chips and various operation modes (synchronous, asynchronous, burst modes). It is also possible to connect bus-extended peripheral chips to the memory bus. The on-chip peripherals may include interrupt controller, OS timer, UART, I2C, PWM, AC97, and etc. Some of these peripherals signals are multiplexed with general-purpose digital I/O pins to provide flexibility to user while other on-chip peripherals, e.g. USB host/client, may have dedicated peripheral signal pins. By connecting or extending these pins, user may use these onchip peripherals. When the on-chip peripherals cannot fulfill the requirement of the target system, extra peripheral chips have to be extended.The architecture of an ARM based embedded system is shown in Fig. 2. The whole system is composed of embedded processor, memory devices, and peripheral devices. To enable rapid prototyping, the platform should be capable of quickly assembling parts of the system into a whole through flexible interconnection. Our basic idea is to insert a reconfigurable interconnection module composed by FPLD into the system to provide adjustable connections between signals, and to provide testability as well. To determine where to place this module, we first analyze the architecture of the system.The embedded system shown in Fig. 2 can be divided into two parts. One is the minimal system composed of the embedded processor and memory devices. The other is made up of peripheral devices extended directly from on-chip peripheral interfaces of the embedded processor, and specific peripheral chips and circuits extended by the bus.The minimal system is the core of the embedded system, determining its processing capacity. The embedded processors are now routinely available at clock speeds of up to 400MHz, and will climb still further. The speed of the bus connecting the processor and the memory chips is exceeding 100MHz. As pin-to-pin propagation delay of a FPLD is in the magnitude of a few nanoseconds, inserting such a device will greatly impair the system performance.The peripherals enable the embedded system to communicate and interactive with the circumstance in the real world. In general, peripheral circuits are highly modularized and independent to each other, and there are hardly needs for flexible connections between them.Here we apply a reconfigurable interconnection module to substitute the connections between microcomputer and the peripherals, which enables flexible adjusting of connections to facilitate interfacing extended peripheral circuits and modules. As the speed of the data communication between the peripherals and the processor is much slower than that in the minimal system, the FPLD solution is feasible.Following this idea, we design the Rapid Prototyping Platform as shown in Fig. 3. We define the interface ICB between the platform and the embedded processor core boar that holds the minimal system of the target embedded system. The interface IPB between the platform and peripheral boards that hold extended peripheral circuits and modules is also defined. These enable us to develop different parts of the target embedded system concurrently and to compose them into a prototype rapidly, and encourage module reusing as well. The two interfaces are connected by a reconfigurable interconnect module. There are also some commonly used peripheral modules, e.g. RS232 transceiver module, bus extended Ethernet module, AC97 codec, PCMCIA/CompactFlash Card slot, and etc, on the platform which can be interfaced through the reconfigurable interconnect module to expedite the embedded system development.B. Reconfigurable Interconnect ModuleWith the facility of state-of-arts FPLDs, we design a reconfigure interconnection module to interconnect, monitor and test the bus and I/O signals between the minimal system and peripherals.As the bus accessing obeys specific protocol and has control signals to identify the data direction, the interconnection of the bus can be easily realized by designing a corresponding bus transceiver into the FPLD, whereas the interconnection of the I/Os is more complex. As I/Os are multiplexed with on-chip peripherals signals, there may be I/Os with bi-direction signals, e.g. the signals for on-chip I2C9 interface, or signals for on-chip MMC (Multi Media Card10) interface. The data direction on these pins may alter without an external indication, making it difficult to connect them via a FPLD. One possible solution is to design a complex state machine according to corresponding accessing protocol to control the data transfer direction. In our design we assign specific locations on the ICB and IPB interfaces to these bi-direction signals and use some jumpers to directly connect these signals when needed. The problem is circumvented at the expense of losing some flexibility.The use of FPLD to build the interconnection module not only offers low cost and simple architecture for fast prototyping, but also provides many more advantages. First, interconnections can be changed dynamically through internal logic modification and pin re-assignment to the FPLD. Second, as FPLD is connected with most pins from the embedded processor, it is feasible to detect interconnection problems due to design or physical fabricate fault in the minimal system with BST (Boundary-Scan Test, IEEE Standard 1149.1 specification). Third, it is possible to route the FPLD internal signals and data to the FPLDs I/O pins for quick and easy access without affecting the whole system design and performance. It is even possible to implement an embedded logical analyzer into the FPLD to smooth the progress of the hardware verification and software development.C. Power SupplyPower dissipation has a great impact on system cost and reliability. It is an increasingly important problem in embedded systems designs not only for the portableelectronics industry but in other areas including consumer electronics, industry control, communications, etc. In order to facilitate the design of power supply for the target embedded system, power supply issues have also been considered in the design of the platform.First, the power supplies to the devices on the platform are separated from those to the core board and peripheral expand boards, which makes it more realistic to measure and verify the power dissipation on the platform for the target embedded system. Second, the power supplies for the core board and peripheral expand boards are built on a separate board and connected to the platform through a slot. As a result, it provides flexibility for power system design while speeding up the whole design process.To meet the demand for higher system speed and lower power consumption in data communications and processing, embedded processor vendors use increasingly advanced processing technologies requiring lower core operating voltages, and keep the interface voltage compatible with most low voltage semiconductor devices on market. Consequently, almost every embedded processor requires more than one power supply, such as power supply for internal logic, for PLLs and oscillators, for memory bus interface, and for other I/Os. Further, different embedded processors may have different requirements on power supply, such as different power supply voltage, power-up sequence, and different strategies to adjust the core voltage in different CPU run mode for minimizing power dissipation.A survey of some widely used ARM based embedded processor suggests that most of them need no more than 3 groups of separated power supply, as shown in Table 1. As the peripherals may require different supply voltages for special purpose, such as +5V for powering the USB ports, we divide the power supply from the power supply slot into 4 separated channels, which is connected to both the core board slot and the peripheral board slot. Each channel of power supplies has a “power good” signal to indicate power output status of the channel, and a shutdown signal to shut the power supply of the channel down. And these signals are directly connected to the core board slot to accommodate the embedded processors requirement of power-up sequence. In order to enable dynamic voltage adjusting, some control signals are routed to the power supply board by the reconfigurable interconnect module.III. EXPERIMENTAL RESULTSAs the Rapid Prototyping Platform is still under development, we present an example applied with the same considerations in the Rapid Prototyping Platform. It is an embedded system prototype based on Intel XScale PXA255, which is an ARM based embedded processor. The diagram of the prototype is illustrated in Fig. 5(a). The photo is shown in Fig. 5(b), where a Bluetooth module is connected to the prototype USB port and a CF LAN card is inserted.The FPGA (an Altera Cyclone EP1C6F256) here offers the same function as the reconfigurable interconnection module shown in Fig. 3. Most of the peripheral devices are expanded to the system through the FPGA, and more peripherals can be easily interfaced when needed. As both of the FPGA and PXA255 support the BST, we can detect faults, e.g. short-circuit and open-circuit faults, on the connections between the two devices by chaining their JTAG ports and performing BST. Here, we use an open source software package 11 to perform the BST.The FPGA internal signals can be routed to the debugging LED matrix for easy access, which is helpful in some simple testing and debugging. We also insert an embedded logical analyzer, the SignalTap II embedded logic analyzer 12 provided in Alteras Quartus II software, into the FPGA for handling more complicated situations. With the help of the logical analyzer, we are able to capture and monitor data passing through over a period of time, which expedites the debugging process for the prototype system. Fig. 6 shows the captured data communication between the embedded processor and the USB host module during the initialization process of the Philips ISP1161 USB host chip13. It can be seen clearly from the figure that the embedded processor writes the command code of 0027H to address 01H (the ISP1161s host controller command port) to access the HcChipID register, and reads 6120H (the chips ID) from address 00H (the ISP1161s host controller data port).The power supply module of the prototype system is held on a separate board connected to the system via a socket. We designed two power supply modules for the prototype system (shown in Fig. 7). One is a large module providing fixed output composed with simple but low-efficiency linear regulator (the upside one in the Fig. 7), the other is a compact module, capable of dynamic voltage adjusting, made up of complex high-efficiency switch regulator(the downside one in the Fig. 7). The former module is first used to accommodate the basic power supply requirements during hardware test and relative software development. During the process, the later is developed and refined, and replaced the former one finally. The separation of power supply module from prototype allows refinement of the power supply module without affecting development of other parts of the system.In this paper, we discuss the design of a fast prototyping platform for ARM based embedded systems to accommodate the requirements of flexibility and testability in the prototyping phase of an embedded system development.With the aid of the platform, modules of the target embedded system can be developed simultaneously, and previous modules can be applied to future designs. As a result, develop process is greatly accelerated.Though the fast prototyping platform is designed for ARM based embedded system, our idea is general and can be applied to embedded system of other types. 2中文资料基于ARM的嵌入式系统的速成样机平台设计在嵌入式系统的设计中，硬件模型的设计是非常重要的。在这篇论文中，我们将讨论一种我们自行设计的快速模型平台，这是基于ARM的嵌入式系统的。这是一种低成本的设计方法，并且符合在嵌入式系统模型发展上对于灵活性和易测试性的要求。我们提供的方法同样支持系统硬件模块各个部分的更新和重利用。虽然快速模型平台是为基于ARM的嵌入式系统设计的，但是我们的方法是普遍适用的而且可以被广泛应用于其它各种类型的嵌入式系统。1介绍嵌入式系统的应用非常广泛，例如在手机、寻呼机、录像机、可携式摄像机、自动调温器、路边租用汽车的登记设备、自动售货机、用计算机处理存货清单的控制设备、数字体温计、电话应答机、打印机、便携式视频游戏、机顶盒还可列出很多。对于嵌入式系统的需求是巨大的，同样它的发展也是很快的。为了生产出满足复杂系统要求而且适应市场的正确的、第一手产品，设计的确认工作在整个设计过程中是非常关键的。对于确认，一个可能的选择是模仿已经设计出的系统。但是如果系统要求一个高水平的模型，那么模仿虽然快可就不可能非常准确，因为低水平的模型只能满足一般质量评估的要求。一旦实时系统的调试要考虑进去，目标系统、还有它的环境、及其运行信息就显得特别重要。因此，用模仿的方法来做的静态分析机会让人感觉效率太低。而且模仿不能揭示在实时物理系统方面更深层次的问题。一个硬件样机是最终设计的可考代表，它保证了实时行为。同时它也是发现硬件深层次问题的基础工具。正是由于这些原因，硬件样机设计成为整个设计流程中非常重要的一步。传统上，样机设计的都与它的目标系统的PCB版很相似。随着嵌入式系统变得越来越复杂，对于系统的测试就显得越来越重要。表面设置组件和多层PCB板的发展，导致了更小的板子和更紧凑的版面设计。这就使得传统的测试方法，例如：外部探测器和“钉板”测试装置，很难实现。结果，从板子上获得对硬件测试和软件开发有用的信号变得不可行，而且使在样机上查找错误变得越来越难。因此，样机的设计必须考虑可测试性。然而，简单的加一些测试点是不够的。如果样机上的错误被检测出来，比如信号的错误连接，那么那是不可能在多层且与各种设置都紧密相关的PCB板上纠正的。因为这些都会影响到样机上的其它设置，增加项目开发的时间同时会提高成本。除了可测试性，保持样机在开发过程中的高度灵活性也是非常重要的，因为设计规格是会经常改动的。目前复杂系统常常不是拼凑在一起的，而是会利用先前已经设计的一些模块，像是：处理器、存储器、或是外围电路。这样做是为了应付越来越激烈的市场竞争的压力。按照这些严密的方法论，我们就会明白设计时的大部分精力放在：将用户的需求拆分成合适的功能模块和再组成目标系统上。很多以前的研究结论建议：将FPLDs添加到最终的设计中以增加系统的灵活性，因为FPLDs可以在它们的管脚间提供可编程的连接而且还可以带来其他一些好处。然而，外加设备可能会增加产品的成本和电源的负担，减弱目标系统的市场竞争力。除了这些问题，还有一个建议的方法就是将FPLDs在硬件样机中最为中介手段，然而这种方法将会给样机的设计带来额外的工作。而且样机上的模块不能被直接重复利用。在市场上，有一些公司提供基于FPLDs的速成样机的商业解决方案。这些产品旨在对片上系统的功能检查，而不是以嵌入式系统的设计和发展为目标。在这篇论文里，我们将提供自行设计的基于ARM的嵌入式系统的速成样机平台，这是一种低成本的解决方案，并且符合在嵌入式系统样机发展方面对于灵活性和可测试性的要求。它同样支持系统硬件各个部分的更新和模块的再利用。论文剩下部分的结构是这样的：第二部分，我们将讨论自行设计的速成样机平台的细节。第三部分，将展示实验的结果，接下来的第四部分是全面的结论。2.速成样机平台设计A 总揽基于ARM的嵌入式处理器被广泛应用于嵌入式系统，这是由于它们的低成本，低功耗和高性能。基于ARM的嵌入式处理器是高度集成的片上系统，它包括一个ARM内核，和各种各样地外围设备。很多基于ARM的嵌入式处理器，比如：68采用一种简单的结构就像Fig.1 所示。集成存储器控制器提供外部存储器总线接口，这种接口支持各种各样的存储器芯片和各种操作模式（同步，异步，突发模式）。而且可以将扩展总线的外围芯片连接到存储器总线上。片上外围设备应该包括中断控制器，操作系统时钟，UART（通用异步收发器），I2C（两线式串行总线），PWM（脉宽调制），AC97（一种声卡）等等。其中一些外围设备的信号是多元的，它们都有多功能的数字I/O管脚来为用户提供方便，而其它的一些片上外围设备，例如：USB主机/客户机，就会提供专用的外围设备信号管脚。通过连接或是扩展这些管脚，用户可以利用这些片上外围设备。当片上外围设备不能满足目标系统的要求时，就得扩展额外的外围设备芯片。基于ARM的嵌入式系统结构如图2所示。整个系统由嵌入式处理器，存储器设备，外围设备组成。为了设计成速成样机，那么平台应该可由各个模块通过灵活的方式迅速组装成一个整体。我们的基本方法是插入一个可重新配置的互相连接的模块，然后用FPLD组成系统，并且使信号间的连接可调整，同时使其具有可测试性。在决定如何设置这样的模块之前，我们首先应该分析系统的结构。在图Fig.2中展示的嵌入式系统可以被分为两部分。一部分是由嵌入式处理器和存储器设备构成的小型系统。另一部分是由嵌入式处理器的片上外围接口扩展的外围设备和有总线扩展的外围芯片、电路组成。最小限度的系统是嵌入式系统的核心，它决定了嵌入式系统的处理能力。嵌入式处理器的时钟频率可以达到400MHz，而且可以达到更高。总线连接处理器和存储器的速度可以达到100MHz以上。因为FPLD的管脚间传播延时的数量级在十亿分之一秒，所以插入这样一个设备将会消弱系统的性能。外围设备可以使嵌入式系统与外界环境相通信和交互。一般来说，外围电路是高度模块化和独立化的。所以在它们之间几乎不需要设置什么灵活的连接手段。这里我们运用可重新配置的相互连接的模块来代替微型计算机和外围设备之间的连接，这种方法可以实现灵活的连接，使模块和外围电路的接口配置变得容易。由于外围设备和处理器间的数据交换速度比最小限度系统要慢很多，所以用FPLD的方法是可行的。按照这种思路，我们设计的速成样机平台如图3所示。我们在平台和载有最小限度嵌入式目标系统的嵌入式处理器核心开发板之间定义接口ICB。在平台和载有扩展的外围电路和模块的外围设备板之间定义接口IPB。这样做可以使我们同时更新嵌入式目标系统的各个模块，而且可以使它们快速组成一个样机，而且这种方法支持模块的再利用。ICB和IPB接口通过可重新配置的连接模块连接在一起。在结构图里也用到了一些外围模块，比如：RS-232模块，网口扩展模块，AC97，存储器卡槽等等。整个平台都通过可重新配置的连接模块来开发嵌入式系统。用FPLD这一艺术级的设备，我们设计了用于在最小限度系统和外围设备之间联接、管理、测试总线和I/O信号的可重新配置的连接模块。当符合具体协议的存取总线在控制信号来确认数据的传输方向时，我们可以通过在FPLDs里设计一个总线通信收发器连载监测这一行为。然而I/O管脚的这种互相连接会很复杂。由于I/O管脚的功能是复合，所以这会有拥有双向信号方向的I/O管脚，例如：给片上I2C（两线是串行总线）接口提供的信号，和给片上MMC（多媒体控制器）接口提供的信号。这些管脚上的数据传输方向再不需要外部信号的情况下是可以改变的，这就使得通过FPLD
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