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在第一次国际会议上新兴工程技术的趋势低功率2:1 MUX桶式移位器Prasad D Khandekar,Member IEEE, Assistant Professor-E&TC,Vishwakarma Institute ofInformation Technology, Punekhandekar.prasadDr. Mrs. Shaila SubbaramanProfessor and Dean AcademicsWalchand College of Engineering, Sangli.shailasubbaramanyahoo.co.in摘要 基于能量回收的绝热开关技术可以降低电路和逻辑电平的功耗，是创新的解决方案之一。许多研究人员采取了加法器作为基准电路，但绝热的优点只能用在大数字电路中。在处理器的设计中，桶式移位器是重要的一环，并没有花太多功夫降低它的功耗。因为桶式移位器需要nlog2n MUX来做n位转换,所以设计MUX为低功率，作为桶式移位器中一个重要的模块，这将大大降低仿真时间。本文比较了基于CMOS的传统绝热设计，它们都使用了以元件为基础的设计方法，并在Cadence中采用180纳米工艺。这项研究成果将为完成超低功耗MUX桶式移位器的设计提供方向。关键Words-绝热，能量回收，PAL，CAL，IPGL。1.简介 桶式移位器是一个重要的浮点运算块,通过n位转换数据。桶形移位器的设计几乎对称并且可以使用重复的组合逻辑块来完成。如果每个多路复用块在能量耗散方面得到优化，那么2：1的多路复用器可以有效地用于设计n位桶式移位器。桶形移位器的整体仿真时间减少log2 n的一个因素，是因为只用一个模拟多路复用器就足够估计整个能量的耗散和延时。这篇论文表明,如果桶式移位器的基础构造MUX采用绝热技术设计则可以降低桶式移位器整体的能量耗散。动态功耗是由于负载电容器在充放电过程中，输出在开关状态，最高达到了70%，同时静态功耗最低，只有10%。剩下的总功耗是由于短路电流引起的。 对于传统CMOS电路来说，负载电容CL的充放电可以用图1表示。可以看到负载电容器CL中，充电过程是由VDD端通过F端流向它，而放电过程是通过F端接地。在充电过程中，（1/2）CLVDD的能量在输出电路中丢失，而在放电过程中（1/2）CLVDD的能量（这是存储在电容器里）输出到地面。因此在一个充电和放电的循环中、能量CLVDD2是消散的。如果输出开关工作于频率f，开关在动作，那么动态功耗由下式给出， 电源上动态功率耗散的二次从属关系，提供了一个有吸引力的解决方案。通过S2与电源电压缩放因子S，来降低消耗。图1.传统CMOS 不幸的是,当电源电压降低时,电路延迟成倍增加。这可以看出，电源延时器对电压进行了优化，约等于2 vt。这限制了最小电压为2VT。 1一旦电源接通，将逐步减少电容值和工作电压。在传统CMOS逻辑电路中，如果放电期间流到地面的能量能够重新输给电源，那么将会节约大量的能源。如果回收的电能来自电源本身，逻辑电路中的能量效率还可以提高。绝热逻辑设计方法提供了这种可能性。2.绝热开关 一个典型的绝热开关电路如图2a所示。负载电容由恒定电流源供电，对应一个线性电压斜坡信号。传统的CMOS电路和绝热电路之间有明显的区别，在绝热电路中，恒流源为负载电容充电，在传统的CMOS电路中，恒压源为负载电容充电。如图所示，令R为电路中的上拉电阻。 a.绝热开关 b.电流图2.绝热开关当t = 0 到t = T，通过下式可以发现电阻R中的能量耗散有如下规律：从这个等式可以看出：1.如果充电时间大于2RC，电阻上消耗的功率将小于传统的CMOS电路中消耗的功率。 2.电阻消耗的能量与T成反比，这意味着可通过增加充电时间减少能量消耗。 3.电阻消耗的能量与R成正比，与此形成鲜明对比的是，传统CMOS电路中消耗的能量取决于负载电容和电压波动。 4.随着充电电阻减小,能量耗散减少。 图2b标明了绝热电路中电流的方向。上拉电路驱动绝热门输出，而下拉电路驱动节点输出。绝热电路充电时，输出电容放电。在周期结束时，能量流回到电源。这个电路的重要组成部分是脉冲增压电源而不是传统逻辑电路中的直流电源。 另外，在电容的充放电过程中，电源的输出一直变化时，可以用步进式稳压电源代替电源接线端钮。它消耗的能量正比于充电过程中的平均电压降,可以解释从逻辑0到逻辑1的变化。实验结果表明，当逆变器由恒压源充电时，消耗的能量达到9.17 X10-13，而当电压依次应用在这三个步骤上，消耗的能量仅为9.69 X10-173。3. 绝热逻辑的实现3.1绝热放大器的设计William Athas等人使用带有两个CMOS传输门和NMOS压板的绝热放大器证明了绝热的基本原理4。图3展示了绝热放大器和双电极输入输出端。图3a.绝热放大器图3b.能量回收原理右窗格图3b中的能量耗散波形演示了每个周期中输入端能量恢复的情况。3.2 基于绝热逻辑技术设计2:1 MUX建立桶式移位器有许多方法，例如基于MUX结构的数据转换技术，基于data-reversal结构的掩码技术，基于MUX结构的二进制补码技术。研究表明，在相同条件下，基于MUX结构的数据转换桶式移位器，只需要更小的面积却能提供更短的延迟。5因此，如果绝热多路复用器用于设计桶形移位器，它的耗能也能降到最低。绝热技术用于减少2：1MUX的功耗，因此选择了3种绝热逻辑方案，CMOS（绝热)逻辑(CAL)7,晶体管绝热逻辑(PAL)8和改进型晶体管逻辑门电路(IPGL)9。该设计采用了180纳米工艺，它在功能上模拟了Cadence工具并将仿真结果与传统的CMOS 2:1 MUX进行比较。4. 结果和分析所有的设计都经过严格的测试，并且研究了Vdd，工作频率（即选择信号的频率）以及负载电容上的能量消耗对它的影响。图4a标明了Vdd对能源消耗的影响。PAL只消耗最少的能量而IPGL要消耗最多的能量。在IPGL中，正因为该电路使用了更多的晶体管，非绝热能量损失就变得至关重要。在CMOS MUX中的耗能几乎和CAL相同，是PAL的三倍。 图4.能量耗散 图4b表明信号频率的选择和能量消耗的多少密切相关。相比较于CAL，IPGL和PAL MUX只消耗非常少的能量。这是因为CAL采用正弦电源而IPGL与PAL使用的是斜波电源。CMOS中的能耗最高的，约为PAL和CAL的三到五倍，是IPGL的40倍。图4c表明了能量消耗对负载电容的影响。在CMOS MUX中，负载电容是11.52fF，相比较于CMOS，PAL和PAL只消散非常少的能量，降低了30%到90%的能量消耗。 图5a和5b描述了信号频率的选择和负载电容的延迟对电路的影响。相比较于CMOS电路，所有的绝热逻辑电路都提供了更好的延迟效果，但在更高的频率上CAL的延迟效果与CMOS是相差不多的。在60MHz频率上，绝热电路的延迟效果约为CMOS电路延迟效果的20到30倍。负载电容上的延迟效果表明，CMOS更好用并且PAL拥有比CAL和IPGL更低的延迟。 每个逻辑电路所占用的区域示于图6。图5. 测量延迟效果图6. 根据晶体管划分区域5.结论 随着能量回收绝热开关的使用，电路中的能量得以保存下来，而不是作为热量耗散。这取决于系统应用和需求，在一定条件下也可以使用这种方法来设计超低功耗电路。这些条件显然受到频率、设备大小和硅用量的约束。 使用此处发布的低延时技术，桶式移位器的设计可以优化为低功耗。再为给定的数据频率选择特定逻辑模式并且重复使用它，那么将会大大减少仿真时间。在桶式移位器中使用个数为nlog2n的MUX，那么所有的三个参数面积，功率和延迟时间都可以缩放相同的量。对于单个的MUX，寄生参数可以计算测量。因此，如果用绝热多路复用器来设计桶形移位器，能量消耗也会减小。当VDD =1.2V，信号频率高于50MHz，负载电容大于11.52 fF时，PAL的原理提供了最佳解决方案，因为它的产品能量延迟是最低的。上述结果表明，总能量的耗散和延时将是它价值的nlog2n倍。6.参考文献1Jan Rabey, Massoud Pedram. Low Power Design Methodologies: 5-7. Kluwer Academic Publishers, 5th edition 2002.2Michael Frank. Energy-Power Basics. Lecture notes,University of Florida.3 P D Khandekar, S Subbaraman, Manish Patil, “Optimising 2:1 MUX for Low Power Using Adiabatic Logic” International Conference on VLSI Design ICVLSI08,VEC, Chennai, 14-16 Feb 2008, pp 145-150.4 William Athas et al, “Low-Power Digital Systems Based on Adiabatic-Switching Principles”, IEEE Transactions on VLSI Systems, Vol 2, no 4, pp398-407, December 1994.5 Mathew Pillmeier, Michael Schulte and E George Walters II, Design Alternatives for Barrel Shifter.6P D Khandekar, S Subbaraman, Manish Patil, “Low Power Digital Design Using Energy-Recovery Adiabatic Logic,” International Journal of Engineering Research and Industrial Applications, accepted for publication. Letter no IJERIA/Eng./V150 dt 01/28/20087 Dragan Maksimovic, Vojin G. Oklobdzija, Borivoje Nikolic, and K Wayne Current, “Clocked CMOS Adiabatic Logic With Integrated Single-Phase Power-Clock Supply”, IEEE Transactions on VLSI Systems, Vol8, no 4, pp460-464, August 2000.8Vojin G Oklobdzija, “ Pass-Transistor Adiabatic Logic Using Single Power-Clock Supply”, In IEEE Transactions on Circuits and Systems II, Vol. 44, No.10, October 1997.9 Laszlo Varga, Ferenc Kovacs, Gabor Hosszu, “An Improved Pass-Gate Adiabatic Logic ”, IEEE, 0-7803-6741-3/901, 2001, pp 208-211. Low Power 2:1 MUX for Barrel Shifter Prasad D Khandekar, Member IEEE, Assistant Professor-E&TC, Vishwakarma Institute of Information Technology, Pune khandekar.prasad Dr. Mrs. Shaila Subbaraman Professor and Dean Academics Walchand College of Engineering, Sangli. shailasubbaramanyahoo.co.in Abstract Adiabatic switching techniques based on energy recovery principle are one of the innovative solutions at circuit and logic level to achieve reduction in power. Many researchers had taken adder as a benchmark circuit but advantage of adiabatic can be taken only for a large digital circuit. Barrel Shifter is an important block in the processor design and not much effort has been done to minimize its power dissipation. A barrel shifter needs nlog2n MUX for n-bit shifting and therefore designing a MUX for low power to use it as a repetitive block in the barrel shifter will considerably reduce the simulation time. This paper compares conventional CMOS based design with adiabatic All the circuits are designed using cell based design approach and 180nm device size in Cadence. The outcome of this research work will provide guidelines for designing barrel shifter using ultra low power MUX . Key Words- Adiabatic, Energy-Recovery, PAL, CAL, IPGL. 1. Introduction A barrel shifter is an important block of a floating point arithmetic block and used to shift the data by n bits. The design of the barrel shifter is almost symmetric and can be done using repetitive combinational logic blocks. 2:1 multiplexer can be effectively used to design n bit barrel shifter, if each multiplexer block is optimized for energy dissipation. The simulation time of the entire barrel shifter is reduced by a factor of nlog2n times because simulation of only one multiplexer is enough to estimate the overall energy dissipation and delay. This paper shows that overall energy dissipation of barrel shifter can be reduced if its basic building block i.e. MUX is designed using adiabatic techniques. Dynamic power dissipation due to charging and discharging of load capacitor during the time the output is switching is the highest and is about 70% while that due to static power dissipation is the lowest and is about 10%. The remaining contribution to the total power dissipation is due to short circuit current dissipation. The charging and discharging of a load capacitor CL for a conventional CMOS circuit is represented in Fig. 1. It is seen that CL charges to VDD through F while discharges to ground through F. During charging an energy = (1/2) CLVDD2 is lost in the pull up circuit while during discharging energy = (1/2) CLVDD2 (which was stored in the capacitor) is lost to the ground. Thus in one cycle of charge and discharge, energy CLVDD2 is dissipated. If the output is switching at frequency f and the switching activity is , then the dynamic power dissipation is given by, P dynamic = CLVDD2 f (1) The quadratic dependence of dynamic power dissipation on supply voltage offers an attractive solution to reduce it by a factor of S2 with supply voltage scaling down by a factor of S. Figure 1. Conventional CMOS. Unfortunately, as supply voltage is reduced, the circuit delays increase exponentially. It can be proved analytically that the power-delay product is optimized for power supply voltage equal to 2Vt. This tends to limit the range of voltage supplies to a minimum of about 2Vt. 1 Once the supply has been fixed, it remains to tactfully minimize the physical capacitance and activity at that operating voltage. A considerable amount of energy saving can be obtained if the energy which is generally lost to the ground during discharging period in a conventional CMOS logic is returned back to the supply itself. If recycling of the energy drawn from the supply is done First International Conference on Emerging Trends in Engineering and Technology978-0-7695-3267-7/08 $25.00 2008 IEEEDOI 10.1109/ICETET.2008.47404then the energy efficiency of the logic circuits can be increased. Adiabatic logic design offers this possibility. 2. Adiabatic Switching A typical adiabatic switching circuit is as shown in Fig. 2a. Here, the load capacitance is charged by a constant current source, which corresponds to a linear voltage ramp. The main difference between the conventional CMOS circuits and the adiabatic circuits is that in adiabatic circuit the load capacitor is charged by a constant current source while in conventional CMOS circuit, it is charged by a constant voltage source. In the figure below, let R be the on-state resistance of pull-up network of the circuit. a. Adiabatic Switching b. Charge Flow Figure 2. Adiabatic Switching Assuming Vc(t)=0 at t=0 Vc(t) =tICsource1 Where, Isource = ttVCc)( Energy dissipated in the resistor R from t=0 to t=T can be found as Ediss = dtIRTsource02 = RTIsource2 =)(2TCVTRCc (2) From this equation it is observed that; 1. If charging time is greater than 2RC then the dissipated energy is smaller than that for conventional CMOS circuit. 2. Dissipated energy is inversely proportional to T, which means that dissipated energy can be made arbitrarily smaller by increasing the charging time. 3. Dissipated energy is proportional to R in contrast to conventional CMOS case wherein dissipated energy depends on load capacitor and voltage swing. 4. As charging resistance decreases, the energy dissipated decreases. Fig.2b depicts the charge flow in adiabatic circuit. Pull-up circuit drives the true output of the adiabatic gate while pull-down circuit drives the complementary output node. Both the networks in adiabatic charge up as well as charge down the output capacitor. At the end of the cycle, the energy flows back into the power supply. The important component in this circuit is the pulsed power supply with ramped voltage instead of a DC supply in conventional logic.2 Alternatively, a stepwise supply voltage can replace the ramped power supply where the output of a power supply varies in small steps during charging and discharging of a capacitor. The energy dissipated is proportional to average voltage drop traversed by the charge and it can be proved analytically that the total energy dissipated is inversely proportional to the total number of steps from logic 0 to logic 1 as explained in the section below. Experimental results showed that energy dissipation is 9.17 X10-13 J when inverter is charged by constant voltage whereas it is just 9.69 X 10-17 J when voltage is applied in three linear steps.3 3. Implementation of adiabatic logic 3.1 Design of adiabatic amplifier The fundamental concepts of adiabatic are experimentally proven with the help of adiabatic amplifier, which uses two CMOS transmission gates and two NMOS clamps, was discussed by William Athas et al 4. Figure 3a shows the adiabatic amplifier and its dual rail inputs and outputs. Figure 3a. Adiabatic Amplifier 405 Figure 3b. Energy-Recovery Principle The waveform of energy dissipation in the right pane of the fig 3b shows the energy being recovered after each cycle of input. 3.2. Design of 2:1 MUX Using Adiabatic Logic There are many ways to build a barrel shifter viz. Mux-based data reversal, Mask based data-reversal, Mask-based twos complement and Mask-based Ones complement. The study shows that Mux-based data reversal barrel shifter consumes less area than others and still gives better worst case delay. 5 Thus if adiabatic multiplexers are used in designing barrel shifter, the energy dissipation also can be minimized. Adiabatic techniques were used to reduce power consumption of 2:1 MUX6. Three adiabatic logic styles were selected Clocked CMOS Adiabatic) logic (CAL) 7, Pass Transistor Adiabatic Logic (PAL) 8 and Improved Pass Transistor Gate Logic (IPGL) 9. The designs were made using 180nm devices and functionally simulated in Cadence tool. The simulation results were compared with that of conventional CMOS 2:1 MUX. 4. Results and analysis All the designs were rigorously tested and effects of Vdd, frequency of operation i.e. select signal frequency, load capacitance on energy dissipation and delay were studied. Figure 4a shows the effect of Vdd on energy dissipation. PAL consumes the lowest energy and IPGL consumes the highest. Non-adiabatic energy losses are significant in IPGL as it uses more number of transistors. Energy dissipation in CMOS MUX is three times of PAL and almost same as CAL. Figure 4b shows the effect of select signal frequency on the energy dissipation. IPGL and PAL MUX dissipates very less amount of energy as compared to CAL. This is because CAL uses a sinusoidal power-clock supply and IPGL & PAL uses ramp type of power-clock supply. The energy dissipation is the highest in CMOS and is forty times that of IPGL and about three to five times that of PAL and CAL. Figure 4c shows the effect of load capacitance on energy dissipation. The load capacitance for CMOS Mux is 11.52fF for fan-out of 4. CAL and PAL dissipate very less energy as compared to CMOS i.e. 90% and 30% reduction in energy dissipation respectively. Figure 5a and 5b depict the effects of select signal frequency and load capacitance on delay respectively. All adiabatic logic circuits offer higher delays as compared to CMOS circuit but at higher frequencies CAL delays are comparable with CMOS. Adiabatic delays are about twenty to thirty times that of CMOS delays at frequencies greater than 60 MHz. The effect of load capacitance on the delay also shows that the CMOS is better and PAL gives less delay than CAL and IPGL. The area consumed by each logic circuit is shown in figure 6. a. Energy Dissipated verus VDD024681012141618201.201.501.802.10VDD (V)Energy Dissipated (pJ)CMOSCALPALIPGL b.Energy Dissipated versus Frequency of Select05000100001500020000250006.257.8110.4215.6331.2569.4489.29125.00208.33625.00Select Frequency (MHz)Energy Dissipated (pJ)CMOSCALPALIPGLc.Energy Dissipated versus CL0123456782.885.768.6411.5221.6043.2064.8086.40Load Capacitance (fF)Energy Dissipated (pJ)CMOSCALPALIPGL Figure 4. Energy dissipated 406a. Delay versus Select Frequency05101520256.256.947.818.9310.4212.5015.6320.8331.2562.5069.4478.1389.29104.17125.00156.25208.33312.50625.00Select Frequency(MHz)Delay (ns)CMOSCALPALIPGL b.Delay versus CL00.511.522.533.544.552.885.768.6411.5221.6043.2064.8086.40Load Capacitance (fF)Delay(ns)CMOSCALPALIPGL Figure 5. Delay Measurements Area051015202530CMOSCALPALIPGLLogic StyleNo of MOSFETSNo of PMOS No of NMOS Total no of MOSFETs Figure 6. Area in terms of Transistors 5. Conclusion With the energy-recovery adiabatic switching, the circuit energies are conserved within the system rather than dissipated as heat. Depending upon the system requirements and application, this approach may be used to design ultra low power under certain conditions. These conditions are obviously defined by frequency constraints, device sizes, and silicon area overhead. Barrel shifter design can be optimized for low power, low delay and area using the results published here. Simulation time can be considerably reduced now as the specific logic style can be selected for the given frequency of data and used repetitively. The number of MUX used in a barrel shifter is nlog2n and all the three parameters viz. area, power and delay can be scaled by the same amount. The parasitic effect can be also measured for individual MUX and scaled and subtracted. Thus, if adiabatic multiplexers are used in designing barrel shif