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KORUS2002 t 169 Information Systems and Technologies THE WAY OF LADDER DIAG RAM ANALYSIS FORSMALL COMPACT PROGRAMMABLE CONTROLLER i M Chmiel E Hrynkiewicz M Muszynski 1 Silesian University of Technology r ul Akademicka 16 44 I00 Gliwice Poland chmiel boss iele polsl gliwice pl eh boss iele polsl gliwice pl 1 I I Abstract The paper presents the consideratibns relating to the ways of analysis of laddei diagram created for small programmable controller PLC compact type which is equipped with simple keyboard for entry of such diagram Because of the fact that compact PLC was built with using of standard microcontroller which calculation i ower is small the authors met difficulties with translation of the control program to the binary code It was necessary to make decision that a ladder diagram will be not compiled but interpreted during program execution The method of column by column analysis of ladder diagram was chosen as the most effective The particular application of this method for small compact PLC is presented in details in the paper 1 Introduction In the middle of the eighties it was observed rapid development of a market of small programmable controllers small PLCs which are equipped with all necessary for normal operation components together with programmingunit 1 3 5 8 In the paper the authors focus their attention on the device which is a small programmable controller with 16 digital inputs and 8 digital outputs The controller performs all fundamental logic operations as well as timer operations and counter operations The control program is executed in serial cyclic way what is typical for PLCs At a beginning of the scan the state of the inputs is read in to the memory and next a control program logic is executed The outputs calculated by the control program are stored in the controller memory and they are transferred to the physical outputs at an end of the scan The controller is programmed by means of built in a keyboard and a display The control progr am is created in the form of ladder diagram LD The most important problem of the investigations was elaboration of an analysis method of stored ladder diagram The works were started from considerations of fundamental properties of LD language One of the main assumptions was a requirement that the designed controller should be built with using simple and not expensive components The next one was full autonomy of the controller It means that starting from writing of a control program up to a control program execution there are not needed any auxiliary devices Finally the compact PLC was designed with using standard microcontroller from MCS 51 family L 1 I I 2 The way of ladder diagram analysis and execution After review of the literature corresponding to the problem there were specifi ed three methods of ladder diagram analysis in LD connections of class H are not allowed and connection shown in fig 1 is treated asopen circuit 1 haIysis of a schematic row by row it me row should begin Next the branch row laying lower is analysed and so on 2 6 I n this method are simple requirements on CPU for bit operations monitoring debug mode state monitoring is easy to implement bhile there are complicated calculation of state in vertical 0 7803 7427 4 02 17 00 0 2002 IEEE KORUS 2002 170 Information Systems and Technologies connection executjon time depends on components placement on schematic sheet and the procedures for signal distribution in network are complicated 1 1 Analysis of a ladder diagram column by column 1 6 the diagram is scanned column by column vertically from top of the network segment to it bottom as it is shown in fig 3 When all procedures connected with currently analysed component are finished in opposite to horizontal analysis component placed below isanalysed When bottom of the column is reached analysis starts from top of next column Column analysis enables signal distribution into other rows gives freedom of vertical connection creation Signal can be forked or joined in diagram without any limitation while in row analysis it is impossible Presented method of a schematic representation has also disadvantages It s possible that developed schematic can behave differently than it was expected The reason is a sequence of value calculation of variables associated wiJh the coils which depends on a the position of the coils in the columns If the coil is placed nearer to the left supply rail a value of associated variable is calculated earlier then for the coils placed in upper rows but farther from left supply rail This behaviour we call as an effect of column analysis l i Fig l The connection treated in LD as open connection between output coil and left supply rail diagram diagram Fig 2 The order of row by row analysis of ladder Fig 3 The order of column by column analysis of ladder 1 1 1 A conversion of ladder diagram into Boolean equation written into controller memory is the third method of ladder diagram analysis Controller executes program written into memory in appropriate format 4 For this method program execution speed is independent from schematic graphical presentation if ideal translation methods are used execution speed can be compared to instruction list program execution but it characterizes with very high complexity of translation methods than high calculation power is needed 3 Column by column LD analysis for small compact PLC From all considered ideas we choose methods of column analysis This method was evaluated as the simplest and allows achieving satisfying results 7 This method also gives user freedom in creation of network connection User cm create any type of forked connection and join any number of branches together Signal and branch tracing debug for this method also can be realized relatively simple State of traced bra is displayed with appropriate selection on display Watching of current flow in circuit h o w for easier and faster detecting of functional mistakes in automation design Design effort was made in order to obtain Kigh quality debug system for rapid software development ind maintenance Each row rung of schematic diagram is assigned one bit variable V rownr Its value describes state of current flow in particular row during analysis stage while column is being analysed Wen this bit is set connection to power rail on the left side of schematic is available any route When bit is cleared connection to power rail is break KORUS 2002 171 Information Systems and Technologies At the beginning of analysis all V rownr variables are set Modification of V variables is done by service functions of particular network components Schematic scanning program iterates through all components in each column from its top to bottom When component is recognised appropriate service function is called Service function carry out required operation e g input state fetch and it result are placed in V rownr variable When the end of the first column is reached the second column is being analysed Column analysis is repeated till it reaches last column on the right When entire schematic has been analysed function assigned to serial cy Vertical connection counter timer Clear input counter1timer Empty logic diagram fI Contact code m a execution time PSI 20 30 70 0 25 35 80 25 ok 2 ms IF P 4 i i Coil code Address of variable register V rownr mask Mask of output variable Coil code Address of variable register V rownr mask Mask of output variable 1 I Addres of variable register 1 Mask of input variable Mask of V rownr Empty place code Mask of V rownr Vertical connection code Contact code Address of variable register Mask of input variable V rownr mask Tab 1 The execution time of individual procedures in non monitoring mode Fig 4 The imaging in program memory of the part of ladder diagram User program consists of up to 5 networks Each network contains up to 8 rows and 10 columns 400 element fields Assuming that one binary instruction operates on two contacts in serial connection AND instruction execution time of lk instructions is equal to 60ms For the program which consists of 8 timers 8 counters 16 clearing inputs 32 coils outputs 100 horizontal connections 50 vertical connections and 132 connectors execution time of one scan is equal to 1 lms 4 Conclusions Relatively long execution time of lk instructions on the one hand results from the way of elaboration of the controller software and on the other it is an effect of utilising of a simple and slow microcontroller For example the microcontroller 80C320 from Dallas Semiconductor is able to speed up our device about six times However it w a s assumed that this compact PLC was built rather for verification of general conceptions then for reach extreme parameters But it is necessary to remark that obtained scan time despite of using cheap standard components does KOR US 2002 173 Information Systems and Technologies not very differ from the value of this time for industrialry manufactured small compact PLCs 5 8 Such PLCs are devoted for simple tasks and they usually execute short control programs Due to this fact high speed of operation of these devices is not required They should be small handy and easy programmed It seems