Tiva_C_Series_LaunchPad.pptx

GettingStartedWiththeTiva CSeriesTM4C123GLaunchPadWorkshop Version1 04 Agenda Portfolio IntroductiontoARM Cortex M4FandPeripheralsCodeComposerStudioIntroductiontoTivaWare InitializationandGPIOInterruptsandtheTimersADC12HibernationModuleUSBMemoryFloating PointBoosterPacksandgrLibSynchronousSerialInterfaceUART DMA TIEmbeddedProcessingPortfolio TM4C123GMCU Tiva TM4C123GMicrocontroller Best in classpowerconsumptionAslowas370 A MHz500 swakeupfromlow powermodesRTCcurrentsaslowas1 7 AInternalandexternalpowercontrol CoreandFPU M4CoreandFloating PointUnit 32 bitARM Cortex M4coreThumb216 32 bitcode 26 lessmemory 25 fasterthanpure32 bitSystemclockfrequencyupto80MHz100DMIPS 80MHzFlexibleclockingsystemInternalprecisionoscillatorExternalmainoscillatorwithPLLsupportInternallowfrequencyoscillatorReal time clockthroughHibernationmoduleSaturatedmathforsignalprocessingAtomicbitmanipulation Read Modify Writeusingbit bandingSingleCyclemultiplyandhardwaredividerUnaligneddataaccessformoreefficientmemoryusageIEEE754compliantsingle precisionfloating pointunitJTWandSerialWireDebugdebuggeraccessETM EmbeddedTraceMacrocell availablethroughKeilandIARemulators Memory TM4C123GH6PMMemory 256KBFlashmemorySingle cycleto40MHzPre fetchbufferandspeculativebranchimprovesperformanceabove40MHz32KBsingle cycleSRAMwithbit bandingInternalROMloadedwithTivaWaresoftwarePeripheralDriverLibraryBootLoaderAdvancedEncryptionStandard AES cryptographytablesCyclicRedundancyCheck CRC errordetectionfunctionality2KBEEPROM fast savesboardspace Wear leveled500Kprogram erasecycles3216 wordblocksCanbebulkorblockerased10yeardataretention4clockcyclereadtime Peripherals 0 x00000000Flash 0 x01000000ROM 0 x20000000SRAM 0 x22000000Bit bandedSRAM 0 x40000000Peripherals EEPROM 0 x42000000Bit bandedPeripherals 0 xE0000000Instrumentation ETM etc TM4C123GH6PMPeripherals Battery backedHibernationModuleInternalandexternalpowercontrol throughexternalvoltageregulator Separatereal timeclock RTC andpowersourceVDD3ONmoderetainsGPIOstatesandsettingsWakeonRTCorWakepin1632 bitwordsofbatterybackedmemory5 AHibernatecurrentwithGPIOretention 1 7 AwithoutSerialConnectivityUSB2 0 OTG Host Device 8 UARTwithIrDA 9 bitandISO7816support6 I2C4 SPI MicrowireorTIsynchronousserialinterfaces2 CAN More TM4C123GH6PMPeripherals Two1MSPS12 bitSARADCsTwelvesharedinputsSingleendedanddifferentialmeasurementInternaltemperaturesensor4programmablesamplesequencersFlexibletriggercontrol SW Timers Analogcomparators GPIOVDDA GNDAvoltagereferenceOptionalhardwareaveraging2analogand16digitalcomparators DMAenabled0 43GPIOAnyGPIOcanbeanexternaledgeorleveltriggeredinterruptCaninitiateanADCsamplesequenceor DMAtransferdirectlyTogglerateuptotheCPUclockspeedontheAdvancedHigh PerformanceBus5 V tolerantininputconfigurationProgrammableDriveStrength 2 4 8mAor8mAwithslewratecontrol Programmableweakpull up pull down andopendrain More TM4C123GH6PMPeripherals MemoryProtectionUnit MPU GeneratesaMemoryManagementFaultonincorrectaccesstoregionTimers2WatchdogtimerswithseparateclocksSysTicktimer 24 bithighspeedRTOSandothertimerSix32 bitandSix64 bitgeneralpurposetimersPWMandCCPmodesDaisychainingUserenabledstallingonCPUHaltflagfromdebuggerforalltimers32channel DMABasic Ping pongandscatter gathermodesTwoprioritylevels8 16and32 bitdatasizesInterruptenabled More TM4C123GH6PMPeripherals Nested VectoredInterruptController NVIC 7exceptionsand71interruptswith8programmableprioritylevelsTail chainingDeterministic always12cyclesor6withtail chainingAutomaticsystemsaveandrestoreTwoMotionControlmodules Eachwith 8high resolutionPWMoutputs 4pairs H bridgedead bandgeneratorsandhardwarepolaritycontrolFaultinputforlow latencyshutdownQuadratureEncoderInputs QEI Synchronizationinandbetweenthemodules Board Tiva EK TM4C123GXLLaunchPad ARM Cortex M4F64 pin80MHzTM4C123GH6PMOn boardUSBICDI In CircuitDebugInterface MicroABUSBportDevice ICDIpowerswitchBoosterPackXLpinoutalsosupportsexistingBoosterPacks2userpushbuttonsResetbutton3userLEDs 1tri colordevice Currentmeasurementtestpoints16MHzMainOscillatorcrystal32kHzRealTimeClockcrystal3 3VregulatorSupportformultipleIDEs Lab Lab1 HardwareandSoftwareSetup InstallthesoftwareReviewthekitcontentsConnectthehardwareTesttheQuickStartapplication USBEmulationConnection Agenda Agenda IDEs IntroductiontoARM Cortex M4FandPeripheralsCodeComposerStudioIntroductiontoTivaWare InitializationandGPIOInterruptsandtheTimersADC12HibernationModuleUSBMemoryFloating PointBoosterPacksandgrLibSynchronousSerialInterfaceUART DMA DevelopmentToolsforTivaCSeriesMCUs TISWEcosystem High levelOSsupportandTI RTOSOSIndependentsupportandTI Waressoftwarepackages Run TimeSoftware DevelopmentTools TIDesignNetwork off the shelfsoftware toolsandservicesForums WikisIn personandonlinetraining Support Community CCStudio IntegratedDevelopmentEnvironment IDE andotherIDEsOptimizingcompilersDesignKits EvaluationModules TISoftwareandToolsEcosystem Run TimeSoftware TIWares minimizesprogrammingcomplexityw optimizeddrivers OSindependentsupportforTIsolutionsLow leveldriverlibrariesPeripheralprogramminginterfaceTool chainagnosticCcodeAvailabletoday TI RTOS providesanoptimizedreal timekernelatnochargethatworkswithTIWaresReal timekernel SYSBIOS optimizedforTIdevices SchedulingMemorymanagementUtilitiesFoundationalsoftwarepackages TIWares LibrariesandexamplesTIRTOSavailabletoday SYSBIOS TIWares SDK SoftwareDevelopmentKit TI RTOS FilesystemsNetworkstackUSB Run TimeSoftware CCSFunctionalOverview CodeComposerStudioFunctionalOverview Compiler Assembler Linker c asm obj asm Edit Debug Simulator Emulator LaunchPad TargetConfigFile IntegratedDevelopmentEnvironment IDE basedonEclipseContainsalldevelopmenttools compilers assembler linker debugger BIOSandincludesonetarget theSimulatorGELfilesinitializethedebuggersothatitunderstandswherememory peripherals etc are StandardRuntimeLibraries lib map User cmd SYS BIOSLibraries SYS BIOSConfig cfg Bios cmd out ccxml Stand AloneEmulator TargetBoard gel TargetconfigurationandEmulators TargetConfigurationandEmulators TheTargetConfigurationFilespecifies Connectiontothetarget SimulatororEmulatortype TargetdeviceGELfile ifapplicable forhardwaresetup Emulator Connection OptionsBuilt inandexternalemulatorsfromTI Blackhawk SpectrumDigitalandothersXDS100v1 v2 200 510 560 560v2 ProjectsandWorkspaces ProjectsandWorkspaces viewedinCCS WORKSPACE PROJECT Source ProjectsandWorkspaces ProjectsandWorkspaces PROJECTfoldercontains Buildandtoolsettings foruseinmanagedMAKEprojects FilescanbelinkedtoorresideintheprojectfolderDeletingalinkedfilewithintheProjectExploreronlydeletesthelink WorkspaceProject1Project2Project3Settings preferences ProjectSourceFilesHeaderFilesLibraryFilesBuild toolsettings SourceFilesCodeandData HeaderFilesDeclarations LibraryFilesCodeandData Link Link Link Link WORKSPACEfoldercontains IDEsettingsandpreferencesProjectscanresideintheworkspacefolderorbelinkedfromelsewhereWhenimportingprojectsintotheworkspace linkingisrecommendedDeletingaprojectwithintheProjectExploreronlydeletesthelink CreatingaNewProject CreatingaNewProject inEditperspective ProjectLocationDefault workspaceManual anywhereyoulike ProjecttemplatesEmptyEmptybutwithamain cAssemblyonlyBIOSothers ConnectionIftargetisspecified usercanchoose connection i e thetargetconfigurationfile AddingFilestoaProject AddingFilestoaProject UserscanADD copyorlink filesintotheirprojectSOURCEfilesaretypicallyCOPIEDLIBRARYfilesaretypicallyLINKED referenced COPYCopiesfilefromoriginallocationtoprojectfolder twocopies LINKReferences pointsto sourcefileintheoriginalfolderCanselecta reference point typicallyPROJECT LOC MakingaProjectPortable PortableProjects Whymakeyourprojects portable SimplifiesprojectsharingYoucaneasilyre locateyourprojectsAllowsimplechangestolinktonewreleasesofsoftwarelibraries Copiedfilesarenotaproblem theymovewiththeprojectfolder Linkedfilesmaybeanissue Theyarelocatedoutsidetheprojectfolderviaa absolutepath orrelativepath ThisisthePathVariableforarelativepath Thiscanbespecifiedforeverylinkedfile PathandBuildVariables PathVariablesandBuildVariables PathVariablesUsedbyCCS Eclipse tostorethebasepathforrelativelinkedfilesExample PROJECT LOCissettothepathofyourproject sayc Tiva LaunchPad Workshop lab2 projectUsedasareferencepointforrelativepaths e g PROJECT LOC files main c BuildVariablesUsedbyCCS Eclipse tostorebasepathforbuildlibrariesorfilesExample CG TOOL ROOTissettothepathforthecodegenerationtools compiler linker Usedtofind include hfiles orobjectlibraries e g CG TOOL ROOT includeor CG TOOL ROOT lib Howarethesevariablesdefined Thevariablesintheseexamplesareautomaticallydefinedwhenyoucreateanewproject PROJECT LOC andwhenyouinstallCCSwiththebuildtools CG TOOL ROOT WhataboutTivaWareoradditionalsoftwarelibraries Youcandefinesomenewvariablesyourself AddingVariables AddingVariables Whyarewedoingthis WecouldusePROJECT LOCforalllinkedresourcesorPROJECT ROOTasthebaseforbuildvariablesItis almost portable BUTifyoumoveorcopyyourproject youhavetoputitatthesame level inthefilesystemDefiningalinkandbuildvariableforTivaWarelocationgivesusarelativepaththatdoesNOTdependonlocationoftheproject muchmoreportable Also ifweinstallanewversionofTivaWare weonlyneedtochangethesevariables whichismucheasierthancreatingnewrelativelinks HowtoaddPathandBuildVariablesProject Properties expandtheResourcecategory clickonLinkedResources YouwillseeatabforPathVariables clickNewtoaddanewpathvariableProject Properties clickonBuildcategory clickontheVariablestab ClickNewtoaddanewbuildvariableInthelab we lladdapathvariableandbuildvariableTIVAWARE INSTALLtobethepathofthelatestTivaWarerelease Note Thismethoddefinesthevariablesaspartoftheproject finercontrol Youcanalsodefinevariablesaspartofyourworkspace doitonce BuildConfigurations BuildConfigurations CodeComposerhastwopre definedBUILDCONFIGURATIONS Debug symbols nooptimization greatforLOGICALdebugRelease nosymbols optimization greatforPERFORMANCEUserscancreatetheirowncustombuildconfigurationsRight clickontheprojectandselectPropertiesThenclick ProcessorOptions oranyothercategory CCSLicensingandPricing CCSv5LicensingandPricing LicensingWidevarietyofoptions nodelocked floating timebased Allversions full DSK freetools usethesameimageUpdatesreadilyavailableonline PricingIncludesFREEoptionsnotedbelowAnnualsubscription 99 159forfloatinglicense recommendedoption purchaseDevelopmentKit useXDS100v1 2 FreeCCSv5 495includesDVD 445isdownloadonly CCSFYI CCSv5 ForMoreInformation Lab Lab2 CodeComposerStudio CreateanewprojectExperimentwithsomeCCSfeaturesUsetheLMFlashProgrammer Agenda USBEmulationConnection Agenda TivaWare IntroductiontoARM Cortex M4FandPeripheralsCodeComposerStudioIntroductiontoTivaWare InitializationandGPIOInterruptsandtheTimersADC12HibernationModuleUSBMemoryFloating PointBoosterPacksandgrLibSynchronousSerialInterfaceUART DMA PeripheralDriverLibraryHigh levelAPIinterfacetocompleteperipheralsetLicense royaltyfreeuseforTICortex MpartsAvailableasobjectlibraryandassourcecodeProgrammedintotheon chipROM TivaWare forCSeriesFeatures GraphicsLibraryGraphicsprimitiveandwidgets153fontsplusAsianandCyrillicGraphicsutilitytools USBStacksandExamplesUSBDeviceandEmbeddedHostcompliantDevice Host OTGandWindows sideexamplesFreeVID PIDsharingprogram Ethernetlwipanduipstackswith1588PTPmodificationsExtensiveexamples ExtrasWirelessprotocolsIQmathexamplesBootloadersWindowssideapplications ISPOptions SensorLibraryAninterruptdrivenI2CmasterdriverforhandlingI2CtransfersAsetofdriversforI2CconnectedsensorsAsetofroutinesforcommonsensoroperationsThreelayers Transport SensorandProcessing InSystemProgrammingOptions TivaSerialFlashLoaderSmallpieceofcodethatallowsprogrammingoftheflashwithouttheneedforadebuggerinterface AllTivaCSeriesMCUsshipwiththeloaderinflashUARTorSSIinterfaceoptionTheLMFlashProgrammerinterfaceswiththeserialflashloaderSeeapplicationnoteSPMA029 TivaBootLoaderPreloadedinROMorcanbeprogrammedatthebeginningofflashtoactasanapplicationloaderCanalsobeusedasanupdatemechanismforanapplicationrunningonaTivamicrocontroller InterfaceviaUART default I2C SSI Ethernet USB DFUH D IncludedintheTivaPeripheralDriverLibrarywithfullapplicationsexamples FundamentalClocks FundamentalClockSources PrecisionInternalOscillator PIOSC 16MHz 3 MainOscillator MOSC using Anexternalsingle endedclocksourceAnexternalcrystalInternal30kHzOscillator30kHz 50 IntendedforuseduringDeep Sleeppower savingmodesHibernationModuleClockSource32 768HzcrystalIntendedtoprovidethesystemwithareal timeclocksource SysClkSources System CPU ClockSources TheCPUcanbedrivenbyanyofthefundamentalclocks Internal16MHzMainInternal30kHzExternalReal Time Plus TheinternalPLL 400MHz Theinternal16MHzoscillatordividedbyfour 4MHz 3 ClockTree TivaCSeriesClockTree driverLibAPISysCtlClockSet selects SYSDIVdividersettingOSCorPLLMainorInternaloscillatorCrystalfrequency GPIO GeneralPurposeIO AnyGPIOcanbeaninterrupt Edge triggeredonrising fallingorbothLevel sensitiveonhighorlowvaluesCandirectlyinitiateanADCsamplesequenceor DMAtransferTogglerateuptotheCPUclockspeedontheAdvancedHigh PerformanceBus CPUclockspeedontheStandard 5VtolerantininputconfigurationProgrammableDriveStrength 2 4 8mAor8mAwithslewratecontrol Programmableweakpull up pull down andopendrainPinstatecanberetainedduringHibernationmode PinMuxUtility PinMuxUtility Masking Allowstheusertographicallyconfigurethedevicepin outGeneratessourceandheaderfilesforusewithanyofthesupportedIDE s GPIOAddressMasking TheregisterwewanttochangeisGPIOPortD 0 x4005 8000 Currentcontentsoftheregisteris 0 0 0 1 1 1 0 1 InsteadofwritingtoGPIOPortDdirectly writeto0 x4005 8098 Bits9 2 shownhere becomeabit maskforthevalueyouwrite 0 0 1 1 1 0 1 1 1 1 1 0 1 0 1 1 Onlythebitsmarkedas 1 inthebit maskarechanged GPIOPortD 0 x4005 8000 Thevaluewewillwriteis0 xEB WriteValue 0 xEB NewvalueinGPIOPortD notethatonlytheredbitswerewritten EachGPIOporthasabaseaddress Youcanwritean8 bitvaluedirectlytothisbaseaddressandalleightpinsaremodified Ifyouwanttomodifyspecificbits youcanuseabit masktoindicatewhichbitsaretobemodified ThisisdoneinhardwarebymappingeachGPIOportto256addresses Bits9 2oftheaddressbusareusedasthebitmask GPIOPinWrite GPIO PORTD BASE GPIO PIN 5 GPIO PIN 2 GPIO PIN 1 0 xEB Note youspecifybaseaddress bitmask andvaluetowrite TheGIPOPinWrite functiondeterminesthecorrectaddressforthemask Lab Lab3 InitializationandGPIO ConfigurethesystemclockEnableandconfigureGPIOUseasoftwaredelaytotoggleanLEDontheevaluationboard Agenda USBEmulationConnection Agenda NVIC IntroductiontoARM Cortex M4FandPeripheralsCodeComposerStudioIntroductiontoTivaWare InitializationandGPIOInterruptsandtheTimersADC12HibernationModuleUSBMemoryFloating PointBoosterPacksandgrLibSynchronousSerialInterfaceUART DMA NestedVectoredInterruptController NVIC Handlesexceptionsandinterrupts8programmableprioritylevels prioritygrouping7exceptionsand71InterruptsAutomaticstatesavingandrestoringAutomaticreadingofthevectortableentryPre emptive NestedInterruptsTail chainingDeterministic always12cyclesor6withtail chaining t MotorcontrolISRs e g PWM ADC CommunicationISRs e g CAN Mainapplication foreground TailChaining PUSH POP ISR1 POP ISR2 PUSH ISR1 POP ISR2 12Cycles IRQ1 IRQ2 Typicalprocessor Cortex M4InterrupthandlinginHW 6Cycles InterruptLatency TailChaining HighestPriority Tail chaining Pre emption PUSH InterruptLatency Pre emption ISR1 ISR2 ISR1 POP ISR2 1 12Cycles IRQ1 IRQ2 Cortex M4 6Cycles HighestPriority POP Typicalprocessor Latearrival PUSH POP POP ISR2 InterruptLatency LateArrival IRQ1 IRQ2 ISR2 ISR1 PUSH POP Cortex M4 HighestPriority ISR1 Typicalprocessor Interrupthandling PUSH POP PUSH PUSH POP Interrupthandlingisautomatic Noinstructionoverhead EntryAutomaticallypushesregistersR0 R3 R12 LR PSR andPContothestackInparallel ISRispre fetchedontheinstructionbus ISRreadytostartexecutingassoonasstackPUSHcompleteExitProcessorstateisautomaticallyrestoredfromthestackInparallel interruptedinstructionispre fetchedreadyforexecutionuponcompletionofstackPOP Exceptiontypes Cortex M4 InterruptHandling Cortex M4 ExceptionTypes VectorTable Cortex M4 VectorTable Afterreset vectortableislocatedataddress0EachentrycontainstheaddressofthefunctiontobeexecutedThevalueinaddress0 x00isusedasstartingaddressoftheMainStackPointer MSP VectortablecanberelocatedbywritingtotheVTABLEregister mustbealignedona1KBboundary Openstartup ccs ctoseevectortablecoding GPTM GeneralPurposeTimerModule Six16 32 bitandSix32 64 bitgeneralpurposetimersTwelve16 32 bitandTwelve32 64 bitcapture compare PWMpinsTimermodes One shotPeriodicInputedgecountortimecapturewith16 bitprescalerPWMgeneration separatedonly Real TimeClock concatenatedonly CountupordownSimplePWM nodeadbandgeneration Supportfortimersynchronization daisy chains andstallingduringdebuggingMaytriggerADCsamplesorDMAtransfers Lab Lab4 InterruptsandtheGPTimer EnableandconfiguretheTimerEnableandconfigureInterruptsWritetheISRcodeandtestGenerateanexception Agenda USBEmulationConnection Agenda ADC IntroductiontoARM Cortex M4FandPeripheralsCodeComposerStudioIntroductiontoTivaWare InitializationandGPIOInterruptsandtheTimersADC12HibernationModuleUSBMemoryFloating PointBoosterPacksandgrLibSynchronousSerialInterfaceUART DMA Analog to DigitalConverter TivaTM4CMCUsfeaturetwoADCmodules ADC0andADC1 thatcanbeusedtoconvertcontinuousanalogvoltagestodiscretedigitalvaluesEachADCmodulehas12 bitresolutionEachADCmoduleoperatesindependentlyandcan ExecutedifferentsamplesequencesSampleanyofthesharedanaloginputchannelsGenerateinterrupts triggers ADC VIN VOUT InputChannels Triggers Interrupts Triggers Interrupts Triggers 12 VIN VOUT 000 001 011 010 100 101 t t ADC1 ADC0 Features TM4C123GH6PMADCFeatures Two12 bit1MSPSADCs12sharedanaloginputchannelsSingleended differentialinputconfigurationsOn chiptemperaturesensorMaximumsamplerateofonemillionsamples second 1MSPS Fixedreferences VDDA GNDA duetopin countlimitations4programmablesampleconversionsequencersperADCSeparateanalogpower groundpins FlexibletriggercontrolController softwareTimersAnalogcomparatorsGPIO2xto64xhardwareaveraging8Digitalcomparators perADC2AnalogcomparatorsOptionalphaseshiftinsampletime betweenADCmo