EDA实验报告OCMJ.docx

EDA实验报告数码管显示时钟 班级： 电技141 姓名： 吴世辉 学号： 2014301030128 一实验目的 1.学习OCMJ显示的译码方法 2.掌握如何利用系统时钟进行分频 3.学习掌握本次试验的程序 4.学习掌握对时钟的运用 5.掌握OCMJ的工作原理，各引脚的作用及编程语句 6.掌握EDA试验箱的使用方法二实验原理框图三VHDL清单分或秒：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity make_time isport(clk:in std_logic;data_out:out std_logic_vector(7 downto 0);clk_out:out std_logic);end;architecture WYB of make_time isbeginprocess(clk)variable temp:std_logic_vector(7 downto 0);beginif rising_edge(clk)thenif temp=x59thentemp:=X00;elseif temp(3 downto 0)=1001thentemp(7 downto 4):=temp(7 downto 4)+1;temp(3 downto 0):=0000;elsetemp(3 downto 0):=temp(3 downto 0)+1;end if;end if;end if;if temp=x59 thenclk_out=1;elseclk_out=0;end if;data_out=temp;end process;end WYB;时：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity make_time_24 isport(clk:in std_logic;data_out:out std_logic_vector(7 downto 0)-clk_out:out std_logic);end;architecture WYB of make_time_24 isbeginprocess(clk)variable temp:std_logic_vector(7 downto 0);beginif rising_edge(clk)thenif temp=x23thentemp:=X00;elseif temp(3 downto 0)=1001thentemp(7 downto 4):=temp(7 downto 4)+1;temp(3 downto 0):=0000;elsetemp(3 downto 0):=temp(3 downto 0)+1;end if;end if;end if;-if temp=x23 then-clk_out=1;-else-clk_out=0;-end if;data_out=temp;end process;end WYB;分频：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity make_clk isport(reset_n:in std_logic;sys_clk:in std_logic;-系统时钟 clk_1Hz: out std_logic);end make_clk;architecture WYB of make_clk isbeginprocess(sys_clk,reset_n)variable temp: integer range 0 to 50000000;-1Hzvariable clk: std_logic;beginif reset_n=0 then temp:=0;elsif rising_edge(sys_clk)thenif temp=50000000-1 thentemp:=0;elsetemp:=temp+1;end if;-end if;if temp=50000000/2-1 thenclk:=0; elseclk:=1; end if;-clk_1Hz=clk;end if;end process;end WYB;译码：library ieee;use ieee.std_logic_1164.all; entity data_decoder is port (sec:in std_logic_vector(7 downto 0);min:in std_logic_vector(7 downto 0);hour:in std_logic_vector(7 downto 0);sec_outL:out std_logic_vector(7 downto 0);min_outL:out std_logic_vector(7 downto 0);hour_outL:out std_logic_vector(7 downto 0);sec_outH:out std_logic_vector(7 downto 0);min_outH:out std_logic_vector(7 downto 0);hour_outH:out std_logic_vector(7 downto 0) ); end; architecture WYB of data_decoder is beginsec_outL=x30 when sec(3 downto 0)=0000else-0X31 when sec(3 downto 0)=0001else-1x32 when sec(3 downto 0)=0010else-2x33 when sec(3 downto 0)=0011else-3x34 when sec(3 downto 0)=0100else-4x35 when sec(3 downto 0)=0101else-5x36 when sec(3 downto 0)=0110else-6x37 when sec(3 downto 0)=0111else-7x38 when sec(3 downto 0)=1000else-8x39;sec_outH=x30 when sec(7 downto 4)=0000else-0 x31when sec(7 downto 4)=0001else-1 x32when sec(7 downto 4)=0010else-2 x33when sec(7 downto 4)=0011else-3 x34 when sec(7 downto 4)=0100else4 x”35”;min_outL=x30 when min(3 downto 0)=0000else-0X31 when min(3 downto 0)=0001else-1x32 when min(3 downto 0)=0010else-2x33 when min(3 downto 0)=0011else-3x34 when min(3 downto 0)=0100else-4x35 when min(3 downto 0)=0101else-5x36 when min(3 downto 0)=0110else-6x37 when min(3 downto 0)=0111else-7x38 when min(3 downto 0)=1000else-8x39;min_outH=x30 when min(7 downto 4)=0000else-0 x31when min(7 downto 4)=0001else-1 x32when min(7 downto 4)=0010else-2 x33when min(7 downto 4)=0011else-3 x34 when min(7 downto 4)=0100else4 x”35”;hour_outL=x30 when hour(3 downto 0)=0000else-0X31 when hour(3 downto 0)=0001else-1x32 when hour(3 downto 0)=0010else-2x33 when hour(3 downto 0)=0011else-3x34 when hour(3 downto 0)=0100else-4x35 when hour(3 downto 0)=0101else-5x36 when hour(3 downto 0)=0110else-6x37 when hour(3 downto 0)=0111else-7x38 when hour(3 downto 0)=1000else-8x39;hour_outH=x30 when hour(7 downto 4)=0000else-0 x31when hour(7 downto 4)=0001else-1 x32; end WYB;OCMJ显示程序：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity lcd_OCMJ_128_32 isport( reset_n:in std_logic;BUSY:in std_logic;sec_inL:in std_logic_vector(7 downto 0);min_inL:in std_logic_vector(7 downto 0);hour_inL:in std_logic_vector(7 downto 0);sec_inH: in std_logic_vector(7 downto 0);min_inH: in std_logic_vector(7 downto 0);hour_inH: in std_logic_vector(7 downto 0);REQ:out std_logic; DB:out std_logic_vector(7 downto 0) );end entity;architecture WYB of lcd_OCMJ_128_32 istype word is array(0 to 52) of std_logic_vector(7 downto 0);-定义数组用于显示北京时间和时、分、秒constant sin_data:word:=(-北-京XF4,XF0,X01,X00,X11,X11,XF0,X02,X00,X1E,-时 -间X09,XF0,X03,X00,X2A,X11,XF0,X04,X00,X1C,X44,XF9,X03,X10,Xff,Xf9,X04,X10,Xff,Xf9,-时X05,X10,X3a,Xf9,X06,X10,X