PC 机总线引脚定义.doc

USB 总线定义 USB 是 Universal Serial Bus 的缩写，由 Compaq, Digital, IBM, Intel, Microsoft, NEC, Northern Telecom 联合推出。外观上计算机一侧为 4 针公插，设备一侧为 4 针母插。 引脚定义PinNameDescription1VCC+5 VDC2D-Data -3D+Data +4GNDGroundAGP总线定义 AGP 是 Accelerated Graphics Port，是 Intel 推出的一种 3D 图形标准接口，它能够提供四倍于 PCI 的效率，AGP2X 的传输速率达到 533MB。有关 AGP 的说明可以在 Intel 的网站上找到。 引脚定义PinB面A面1Spare12V25.0VSpare35.0VReserved4USB+USB-5GroundGround6INTB#INTA#7ClockRST#8REQ#GNT#9Vcc3.3VVcc3.3V10ST0ST111ST2Reserved12RBF#PIPE#13GroundGround14SpareSpare15SBA0SBA116Vcc3.3VVcc3.3V17SBA2SBA318SB_STBReserved19GroundGround20SBA4SBA521SBA6SBA722KeyKey23KeyKey24KeyKey25KeyKey26Address31Address3027Address29Address2828Vcc3.3VVcc3.3V29Address27Address2630Address25Address2431GroundGround32AD_STB1Reserved33Address23C/BE3#34Vddq3.3Vddq3.335Address21Address2236Address19Address2037GroundGround38Address17Address1839C/BE2#Address1640Vddq3.3Vddq3.341IRDY#FRAME#4243GroundGround4445Vcc3.3VVcc3.3V46DEVSEL#TRDY#47Vddq3.3STOP#48Perr#Spare49GroundGround50SERR#PAR51C/BE1#Address1552Vddq3.3Vddq3.353Address14Address1354Address12Address1155GroundGround56Address10Address957Address8C/BE0#58Vddq3.3Vddq3.359AD_STB0Reserved60Address7Address661GroundGround62Address5Address463Address3Address264Vddq3.3Vddq3.365Address1Address066SMB0SMB1PCI总线定义 PCI 是 Peripheral Component Interconnect 的缩写 接口卡的外观PCI 标准 32位/64位 接口卡 -| PCI 元件侧 （B面） | | | | _ 32 位引脚部分 64 位引脚部分 _|_| |-|-|-| b01 b11 b14 b49 b52 b62 b63 b94PCI 5V 32/64位卡| optional | _ 32 位引脚部分 64 位引脚部分 _|_| |-|-|PCI 3.3V 32/64位卡| optional | _ 32 位引脚部分 64 位引脚部分 _|_| |-|-|引脚定义 Pin+5V+3.3VUniversalDescriptionA1TRSTTest Logic ResetA2+12V+12 VDCA3TMSTest Mde SelectA4TDITest Data InputA5+5V+5 VDCA6INTAInterrupt AA7INTCInterrupt CA8+5V+5 VDCA9RESV01Reserved VDCA10+5V+3.3VSignal Rail+V I/O (+5 V or +3.3 V)A11RESV03Reserved VDCA12GND03(OPEN)(OPEN)Ground or Open (Key)A13GND05(OPEN)(OPEN)Ground or Open (Key)A14RESV05Reserved VDCA15RESETResetA16+5V+3.3VSignal Rail+V I/O (+5 V or +3.3 V)A17GNTGrant PCI useA18GND08GroundA19RESV06Reserved VDCA20AD30Address/Data 30A21+3.3V01+3.3 VDCA22AD28Address/Data 28A23AD26Address/Data 26A24GND10GroundA25AD24Address/Data 24A26IDSELInitialization Device SelectA27+3.3V03+3.3 VDCA28AD22Address/Data 22A29AD20Address/Data 20A30GND12GroundA31AD18Address/Data 18A32AD16Address/Data 16A33+3.3V05+3.3 VDCA34FRAMEAddress or Data phaseA35GND14GroundA36TRDYTarget ReadyA37GND15GroundA38STOPStop Transfer CycleA39+3.3V07+3.3 VDCA40SDONESnoop DoneA41SBOSnoop BackoffA42GND17GroundA43PARParityA44AD15Address/Data 15A45+3.3V10+3.3 VDCA46AD13Address/Data 13A47AD11Address/Data 11A48GND19GroundA49AD9Address/Data 9A52C/BE0Command, Byte Enable 0A53+3.3V11+3.3 VDCA54AD6Address/Data 6A55AD4Address/Data 4A56GND21GroundA57AD2Address/Data 2A58AD0Address/Data 0A59+5V+3.3VSignal Rail+V I/O (+5 V or +3.3 V)A60REQ64Request 64 bit ?A61VCC11+5 VDCA62VCC13+5 VDCA63GNDGroundA64C/BE7#Command, Byte Enable 7A65C/BE5#Command, Byte Enable 5A66+5V+3.3VSignal Rail+V I/O (+5 V or +3.3 V)A67PAR64Parity 64 ?A68AD62Address/Data 62A69GNDGroundA70AD60Address/Data 60A71AD58Address/Data 58A72GNDGroundA73AD56Address/Data 56A74AD54Address/Data 54A75+5V+3.3VSignal Rail+V I/O (+5 V or +3.3 V)A76AD52Address/Data 52A77AD50Address/Data 50A78GNDGroundA79AD48Address/Data 48A80AD46Address/Data 46A81GNDGroundA82AD44Address/Data 44A83AD42Address/Data 42A84+5V+3.3VSignal Rail+V I/O (+5 V or +3.3 V)A85AD40Address/Data 40A86AD38Address/Data 38A87GNDGroundA88AD36Address/Data 36A89AD34Address/Data 34A90GNDGroundA91AD32Address/Data 32A92RESReservedA93GNDGroundA94RESReservedB1-12V-12 VDCB2TCKTest ClockB3GNDGroundB4TDOTest Data OutputB5+5V+5 VDCB6+5V+5 VDCB7INTBInterrupt BB8INTDInterrupt DB9PRSNT1ReservedB10RES+V I/O (+5 V or +3.3 V)B11PRSNT2?B12GND(OPEN)(OPEN)Ground or Open (Key)B13GND(OPEN)(OPEN)Ground or Open (Key)B14RESReserved VDCB15GNDResetB16CLKClockB17GNDGroundB18REQRequestB19+5V+3.3VSignal Rail+V I/O (+5 V or +3.3 V)B20AD31Address/Data 31B21AD29Address/Data 29B22GNDGroundB23AD27Address/Data 27B24AD25Address/Data 25B25+3.3V+3.3VDCB26C/BE3Command, Byte Enable 3B27AD23Address/Data 23B28GNDGroundB29AD21Address/Data 21B30AD19Address/Data 19B31+3.3V+3.3 VDCB32AD17Address/Data 17B33C/BE2Command, Byte Enable 2B34GND13GroundB35IRDYInitiator ReadyB36+3.3V06+3.3 VDCB37DEVSELDevice SelectB38GND16GroundB39LOCKLock busB40PERRParity ErrorB41+3.3V08+3.3 VDCB42SERRSystem ErrorB43+3.3V09+3.3 VDCB44C/BE1Command, Byte Enable 1B45AD14Address/Data 14B46GND18GroundB47AD12Address/Data 12B48AD10Address/Data 10B49GND20GroundB50(OPEN)GND(OPEN)Ground or Open (Key)B51(OPEN)GND(OPEN)Ground or Open (Key)B52AD8Address/Data 8B53AD7Address/Data 7B54+3.3V12+3.3 VDCB55AD5Address/Data 5B56AD3Address/Data 3B57GND22GroundB58AD1Address/Data 1B59VCC08+5 VDCB60ACK64Acknowledge 64 bit ?B61VCC10+5 VDCB62VCC12+5 VDCB63RESReservedB64GNDGroundB65C/BE6#Command, Byte Enable 6B66C/BE4#Command, Byte Enable 4B67GNDGroundB68AD63Address/Data 63B69AD61Address/Data 61B70+5V+3.3VSignal Rail+V I/O (+5 V or +3.3 V)B71AD59Address/Data 59B72AD57Address/Data 57B73GNDGroundB74AD55Address/Data 55B75AD53Address/Data 53B76GNDGroundB77AD51Address/Data 51B78AD49Address/Data 49B79+5V+3.3VSignal Rail+V I/O (+5 V or +3.3 V)B80AD47Address/Data 47B81AD45Address/Data 45B82GNDGroundB83AD43Address/Data 43B84AD41Address/Data 41B85GNDGroundB86AD39Address/Data 39B87AD37Address/Data 37B88+5V+3.3VSignal Rail+V I/O (+5 V or +3.3 V)B89AD35Address/Data 35B90AD33Address/Data 33B91GNDGroundB92RESReservedB93RESReservedB94GNDGroundISA 总线定义ISA 是 Industry Standard Architecture 的缩写 接口卡的外观插槽的外观引脚定义引脚定义方向说明A1/I/O CH CKI/O channel check; active low=parity errorA2D7Data bit 7A3D6Data bit 6A4D5Data bit 5A5D4Data bit 4A6D3Data bit 3A7D2Data bit 2A8D1Data bit 1A9D0Data bit 0A10I/O CH RDYI/O Channel ready, pulled low to lengthen memory cyclesA11AENAddress enable; active high when DMA controls busA12A19Address bit 19A13A18Address bit 18A14A17Address bit 17A15A16Address bit 16A16A15Address bit 15A17A14Address bit 14A18A13Address bit 13A19A12Address bit 12A20A11Address bit 11A21A10Address bit 10A22A9Address bit 9A23A8Address bit 8A24A7Address bit 7A25A6Address bit 6A26A5Address bit 5A27A4Address bit 4A28A3Address bit 3A29A2Address bit 2A30A1Address bit 1A31A0Address bit 0B1GNDGroundB2RESETActive high to reset or initialize system logicB3+5V+5 VDCB4IRQ2Interrupt Request 2B5-5VDC-5 VDCB6DRQ2DMA Request 2B7-12VDC-12 VDCB8/NOWSNo WaitStateB9+12VDC+12 VDCB10GNDGroundB11/SMEMWSystem Memory WriteB12/SMEMRSystem Memory ReadB13/IOWI/O WriteB14/IORI/O ReadB15/DACK3DMA Acknowledge 3B16DRQ3DMA Request 3B17/DACK1DMA Acknowledge 1B18DRQ1DMA Request 1B19/REFRESHRefreshB20CLOCKSystem Clock (67 ns, 8-8.33 MHz, 50% duty cycle)B21IRQ7Interrupt Request 7B22IRQ6Interrupt Request 6B23IRQ5Interrupt Request 5B24IRQ4Interrupt Request 4B25IRQ3Interrupt Request 3B26/DACK2DMA Acknowledge 2B27T/CTerminal count; pulses high when DMA term. count reachedB28ALEAddress Latch EnableB29+5V+5 VDCB30OSCHigh-speed Clock (70 ns, 14.31818 MHz, 50% duty cycle) B31GNDGroundC1SBHESystem bus high enable (data available on SD8-15)C2LA23Address bit 23C3LA22Address bit 22C4LA21Address bit 21C5LA20Address bit 20C6LA18Address bit 19C7LA17Address bit 18C8LA16Address bit 17C9/MEMRMemory Read (Active on all memory read cycles)C10/MEMWMemory Write (Active on all memory write cycles)C11SD08Data bit 8C12SD09Data bit 9C13SD10Data bit 10C14SD11Data bit 11C15SD12Data bit 12C16SD13Data bit 13C17SD14Data bit 14C18SD15Data bit 15D1/MEMCS16Memory 16-bit chip select (1 wait, 16-bit memory cycle)D2/IOCS16I/O 16-bit chip select (1 wait, 16-bit I/O cycle)D3IRQ10Interrupt Request 10D4IRQ11Interrupt Request 11D5IRQ12Interrupt Request 12D6IRQ15Interrupt Request 15D7IRQ14Interrupt Request 14D8/DACK0DMA Acknowledge 0D9DRQ0DMA Request 0D10/DACK5DMA Acknowledge 5D11DRQ5DMA Request 5D12/DACK6DMA Acknowledge 6D13DRQ6DMA Request 6D14/DACK7DMA Acknowledge 7D15DRQ7DMA Request 7D16+5 VD17/MASTERUsed with DRQ to gain control of systemD18GNDGroundEISA总线定义EISA 是 Extended Industry Standard Architecture 的缩写，由 Compaq, AST, Zenith, Tandy 等公司开发。 接口卡的外观+-+| 元件面 | |_ ISA-16bit _ ISA-8bit _| | | A1 正面/B1 反面 | | | | | | | | | | | | | | EISA: E1 正面/F1 反面 C1/D1 G1/H1A,C,E,G=元件面A,B,F,H=线路面引脚定义PinNameDescriptionE1CMD#Command PhaseE2START#Start PhaseE3EXRDYEISA ReadyE4EX32#EISA Slave Size 32E5GNDGroundE6KEYAccess KeyE7EX16#EISA Slave Size 16E8SLBURST#Slave BurstE9MSBURST#Master BurstE10W/R#Write/ReadE11GNDGroundE12RESReservedE13RESReservedE14RESReservedE15GNDGroundE16KEYAccess KeyE17BE1#Byte Enable 1E18LA31#Latchable Addressline 31E19GNDGroundE20LA30#Latchable Addressline 30E21LA28#Latchable Addressline 28E22LA27#Latchable Addressline 27E23LA25#Latchable Addressline 25E24GNDGroundE25KEYAccess KeyE26LA15Latchable Addressline 15E27LA13Latchable Addressline 13E28LA12Latchable Addressline 12E29LA11Latchable Addressline 11E30GNDGroundE31LA9Latchable Addressline 9F1GNDGroundF2+5V+5 VDCF3+5V+5 VDCF4-F5-F6KEYAccess KeyF7-F8-F9+12V+12 VDCF10M/IO#Memory/Input-OutputF11LOCK#Lock busF12RESReservedF13GNDGroundF14RESReservedF15BE3#Byte Enable 3F16KEYAccess KeyF17BE2#Byte Enable 2F18BE0#Byte Enable 0F19GNDGroundF20+5V+5 VDCF21LA29#Latchable Addressline 29F22GNDGroundF23LA26#Latchable Addressline 26F24LA24#Latchable Addressline 24F25KEYAccess KeyF26LA16Latchable Addressline 16F27LA14Latchable Addressline 14F28+5V+5 VDCF29+5V+5 VDCF30GNDGroundF31LA10Latchable Addressline 10G1LA7Latchable Addressline 7G2GNDGroundG3LA4Latchable Addressline 4G4LA3Latchable Addressline 3G5GNDGroundG6KEYAccess KeyG7D17Data 17G8D19Data 19G9D20Data 20G10D22Data 22G11GNDGroundG12D25Data 25G13D26Data 26G14D28Data 28G15KEYAccess KeyG16GNDGroundG17D30Data 30G18D31Data 31G19MREQxMaster RequestH1LA8Latchable Addressline 8H2LA6Latchable Addressline 6H3LA5Latchable Addressline 5H4+5V+5 VDCH5LA2Latchable Addressline 2H6KEYAccess KeyH7D16Data 16H8D18Data 18H9GNDGroundH10D21Data 21H11D23Data 23H12D24Data 24H13GNDGroundH14D27Data 27H15KEYAccess KeyH16D29Data 29H17+5V+5 VDCH18+5V+5 VDCPCMCIA引脚定义 PCMCIA 是 Personal Computer Memory Card International AssociationIndustry Standard Architecture 的缩写，是便携式计算机外扩卡的接口定义。 引脚定义PinNameDirDescription1GNDGround2D3Data 33D4Data 44D5Data 55D6Data 66D7Data 77/CE1Card Enable 18A10Address 109/OEOutput Enable10A11Address 1111A9Address 912A8Address 813A13Address 1314A14Address 1415/WE:/PWrite Enable : Program16/READY:/IREQReady : Busy (IREQ)17VCC+5V18VPP1Programming Voltage (EPROM)19A16Address 1620A15Address 1521A12Address 1222A7Address 723A6Address 624A5Address 525A4Address 426A3Address 327A2Address 228A1Address 129A0Address 030D0Data 031D1Data 132D2Data 233/WP:/IOIS16Write Protect : IOIS1634GNDGround35GNDGround36/CD1Card Detect 137D11Data 1138D12Data 1239D13Data 1340D14Data 1441D15Data 1542/CE2Card Enable 243/VS1Refresh44/IORD?I/O Read45/IOWR?I/O Write46A17Address 1747A18Address 1848A19Address 1949A20Address 2050A21Address 2151VCC+5V52VPP2Programmeing Voltage 2 (EPROM)53A22Address 2254A23Address 2355A24Address 2456A25Address 2557/VS2?RFU58RESET?RESET59/WAIT?WAIT60/INPACK?61/REGRegister Select62/BVD2:SPKRBattery Voltage Detect 2 : SPKR63/BVD1:STSCHGBattery Voltage Detect 1 : STSCHG64D8Data 865D9Data 966D10Data 1067/CD2Card Detect 268GNDGroundVESA总线定义 VESA 是 Video Electronics Standards Association 的缩写，本页列出的是扩展部分的引脚定义，非扩展部分请见 ISA 总线的定义。 接口卡的外观插槽的外观引脚定义PinNameDescriptionA1D1Data 1A2D3Data 3A3GNDGroundA4D5Data 5A5D7Data 7A6D9Data 9A7D11Data 11A8D13Data 13A9D15Data 15A10GNDGroundA11D17Data 17A12Vcc+5 VDCA13D19Data 19A14D21Data 21A15D23Data 23A16D25Data 25A17GNDGroundA18D27Data 27A19D29Data 2A20D31Data 31A21A30Address 30A22A28Address 28A23A26Address 26A24GNDGroundA25A24Address 24A26A22Address 22A27VCC+5 VDCA28A20Address 20A29A18Address