vhdl语言编程实例.doc

实现各种逻辑功能：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY louji1a ISPORT(S: IN STD_LOGIC_VECTOR(2 DOWNTO 0); C: IN STD_LOGIC; A: IN STD_LOGIC_VECTOR(4 DOWNTO 0); B: IN STD_LOGIC_VECTOR(4 DOWNTO 0); F: OUT STD_LOGIC_VECTOR(4 DOWNTO 0) );END ENTITY louji1a;ARCHITECTURE ONE OF louji1a ISBEGINF=A WHEN S=000 ELSE A-B WHEN S=001 ELSE A-1 WHEN (S=010 AND C=0) ELSE A+1 WHEN (S=011 AND C=0) ELSE A AND B WHEN S=100 ELSE A OR B WHEN S=101 ELSE A XOR B WHEN S=110 ELSE NOT A WHEN S=111 ELSE NULL;END ARCHITECTURE ONE;38译码器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY yimaqi1a ISPORT(A: IN STD_LOGIC_VECTOR(3 DOWNTO 0); B: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END ENTITY yimaqi1a;ARCHITECTURE one OF yimaqi1a IS-SIGNAL abc:STD_LOGIC_VECTOR(3 DOWNTO 0);-SIGNAL def:STD_LOGIC_VECTOR(6 DOWNTO 0);BEGIN-abc=A3&A2&A1&A0;-defBBBBBBBBBBBBBBBBNULL;END CASE ;END PROCESS;END ARCHITECTURE ONE;十进制计数器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY jishuqi1a ISPORT(CLK,EN,CTRL,CLR:IN STD_LOGIC; Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); CO:OUT STD_LOGIC);END ENTITY jishuqi1a;ARCHITECTURE BHV OF jishuqi1a ISSIGNAL QQ :STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK,EN,CTRL,CLR)-VARIABLE QQ :STD_LOGIC_VECTOR(3 DOWNTO 0); BEGINIF CLR=0 THEN QQ=0000;ELSIF CTRL=0 THEN QQ=0000;ELSIF CLKEVENT AND CLK=1 THEN IF EN=1 THEN IF QQ9 THEN QQ=QQ+1;ELSE QQ=0000;END IF;END IF;END IF;IF QQ=0000 THEN CO=1;ELSE CO=0;END IF;END PROCESS ;Q=QQ;END ARCHITECTURE BHV;实现六十进制计数器：1. 实现任何计数器:2.library ieee;use ieee.std_logic_1164.all;-use ieee.std_logic_unsigned.all;entity ncount isgeneric(n: integer :=6);port (clk: in std_logic;clr: in std_logic;-updown : in std_logic;en : in std_logic;ctrl : in std_logic;d : in INTEGER range n-1 downto 0;q : out INTEGER RANGE n-1 DOWNTO 0; C : OUT STD_LOGIC );end entity;architecture rtl of ncount is- Declare the shift register signalsignal qq : INTEGER RANGE n-1 DOWNTO 0;beginprocess (clk,en,ctrl,clr,qq)begin if (clr = 0) then qq = 0;elsif (rising_edge(clk) thenif (en = 1) thenif (ctrl = 1) then qq = d; -elsif (updown = 1) then else if ( qq n-1 ) then qq = qq+1; else qq 0 ) then- qq = qq-1; - else - qq = n-1; end if; end if;end if;if ( qq = 0 ) then c=1;else c=0;end if;q=qq;end process;end rtl;六进制：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity sixcount isgeneric(n: integer :=3);port (clk: in std_logic;clr: in std_logic;en : in std_logic;ctrl : in std_logic;d : in std_logic_vector (n-1 downto 0);q : out std_logic_vector (n-1 downto 0); C : OUT STD_LOGIC );end entity;architecture rtl of sixcount is- Declare the shift register signalsignal qq : std_logic_vector (n-1 downto 0);beginprocess (clk,en,ctrl,clr,qq)begin if (clr = 0) then qq = 000;elsif (rising_edge(clk) thenif (en = 1) thenif (ctrl = 1) then qq = d; -elsif (updown = 1) then else if ( qq 101 ) then qq = qq+1; else qq 0 ) then- qq = qq-1; - else - qq = n-1; end if; end if;end if;if ( qq = 000 ) then c=1;else c=0;end if;q=qq;end process;end rtl;十进制：generic(n: integer :=4);port (clk: in std_logic;clr: in std_logic;-updown : in std_logic;en : in std_logic;ctrl : in std_logic;d : in std_logic_vector (n-1 downto 0);q : out std_logic_vector (n-1 downto 0); C : OUT STD_LOGIC );end entity;architecture rtl of tencount is- Declare the shift register signalsignal qq : std_logic_vector (n-1 downto 0);beginprocess (clk,en,ctrl,clr,qq)begin if (clr = 0) then qq =0000;elsif (rising_edge(clk) thenif (en = 1) thenif (ctrl = 1) then qq = d; -elsif (updown = 1) then else if ( qq 1001 ) then qq = qq+1; else qq 0 ) then- qq = qq-1; - else - qq = n-1; end if; end if;end if;if ( qq = 0000 ) then c=1;else c=0;end if;q=qq;end process;end rtl;还需用译码器：library ieee ;use IEEE.STD_LOGIC_1164.ALL; ENTITY TRANS IS PORT( A3,A2,A1,A0 :IN STD_LOGIC; -A,B,C,D,E,F,G:OUT STD_LOGIC; Q :OUT STD_LOGIC_VECTOR(6 DOWNTO 0) );END ENTITY TRANS ;ARCHITECTURE A OF TRANS ISSIGNAL AA:STD_LOGIC_VECTOR(3 DOWNTO 0);-SIGNAL Q:STD_LOGIC_VECTOR(6 DOWNTO 0);BEGIN AA = A3&A2&A1&A0;-Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q NULL;END CASE;END PROCESS;END ARCHITECTURE A ;将十进制，六进制组成六十进制：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity stencount isport (clk1 : in std_logic;clr1 : in std_logic;-updown1 : in std_logic;en1 : in std_logic;ctrl1 : in std_logic;-ctrl2 : in std_logic; dd1 : in INTEGER RANGE 9 DOWNTO 0; dd2 : in INTEGER RANGE 5 DOWNTO 0;q1 : out INTEGER RANGE 59 DOWNTO 0; C1 : OUT STD_LOGIC );end entity;architecture rtl of stencount iscomponent ncountgeneric(n: integer );port (clk: in std_logic;clr: in std_logic;-updown : in std_logic;en : in std_logic;ctrl : in std_logic;d : in INTEGER range n-1 downto 0;q : out INTEGER RANGE n-1 DOWNTO 0; c : OUT STD_LOGIC );end component;- Declare the shift register signalsignal aa : std_logic;signal qq1 : INTEGER RANGE 9 DOWNTO 0;signal qq2 : INTEGER RANGE 5 DOWNTO 0;signal cctrl1,cctrl2 : std_logic;begincctrl1=ctrl1;cctrl2=ctrl1;-qq1=q1(3)&q1(2)&q1(1)&q1(0); -qq210)PORT MAP( clk=clk1,en=en1 ,c=aa,ctrl =cctrl1,clr=clr1,q=qq1,d=dd1);U2 :ncount GENERIC MAP(n=6)PORT MAP( clk=aa ,en=en1 ,ctrl =cctrl2,clr=clr1,q=qq2,d=dd2);q1=qq2*10+qq1; process (qq1,qq2)begin if ( qq2*10+qq1 = 0 ) then c1=1; else c1=0; end if; end process;end rtl;锁存器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY keep ISPORT (CTRL:IN STD_LOGIC; DIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0); DOUT: OUT STD_LOGIC_