微波炉定时系统.doc

微波炉定时器在开始具体设计之前，先对先对系统进行模块划分，具体划分如图1所示。图1 系统模块划分一、各模块程序Top模块：/ Top: 为顶层模块，包含三个模块:microwave ,display 和timer 。/clk: 为系统的同步时钟。/reset: 定时器timer 的复位控制端，如果复位为0，系统处于IDLE 等待状态；为1时定时器timer 开始计时。/test: 为灯测信号，用于检查LED 等是否正常；test 为1，LED 显示为8888./cook_time: 设置的加热时间。/set_time: 加热时间设置确定信号。如果set_time 为1，cook_time 将被加载到timer。/start_cook: 开始加热确定信号。Start_cook 为1 时开始加热。Cook_time 开始倒计时数秒。/min_msb_led,min_lsb_led,sec_msb_led,sec_lsb_led:为段数码管译码器的输出信号，用来驱动LED 灯。module top(clk, reset, test, set_time, start_cook, cook_time, min_msb_led, min_lsb_led, sec_msb_led, sec_lsb_led);input clk, reset, test, set_time, start_cook;input 15:0 cook_time;output 6:0 min_msb_led, min_lsb_led, sec_msb_led, sec_lsb_led;wire clk, reset, test, set_time, start_cook;wire 15:0 cook_time, time_load;wire 6:0 min_msb_led, min_lsb_led, sec_msb_led, sec_lsb_led;wire 3:0 min_msb_next, min_lsb_next, sec_msb_next, sec_lsb_next;microwave microwave(clk, reset, test, set_time, start_cook, done, cook_time, time_load, cook, load);timer timer(time_load, clk, cook ,load, min_msb_next, min_lsb_next, sec_msb_next, sec_lsb_next, done);display display( min_msb_next, min_lsb_next, sec_msb_next, sec_lsb_next , min_msb_led, min_lsb_led, sec_msb_led, sec_lsb_led);endmoduledisplay模块：/display ：为系统显示模块，使用七段led 数码管显示倒计时时间。module display( min_msb_next, min_lsb_next, sec_msb_next, sec_lsb_next , min_msb_led, min_lsb_led, sec_msb_led, sec_lsb_led);input 3:0 min_msb_next, min_lsb_next, sec_msb_next, sec_lsb_next;output 6:0 min_msb_led, min_lsb_led, sec_msb_led, sec_lsb_led;wire 3:0 min_msb_next, min_lsb_next, sec_msb_next, sec_lsb_next;wire 6:0 min_msb_led, min_lsb_led, sec_msb_led, sec_lsb_led;converter convmm(min_msb_next3, min_msb_next2, min_msb_next1, min_msb_next0, min_msb_led0, min_msb_led1, min_msb_led2, min_msb_led3, min_msb_led4, min_msb_led5, min_msb_led6);converter convml(min_lsb_next3, min_lsb_next2, min_lsb_next1, min_lsb_next0, min_lsb_led0, min_lsb_led1, min_lsb_led2, min_lsb_led3, min_lsb_led4,min_lsb_led5, min_lsb_led6);converter convsm(sec_msb_next3, sec_msb_next2, sec_msb_next1, sec_msb_next0, sec_msb_led0, sec_msb_led1, sec_msb_led2, sec_msb_led3, sec_msb_led4, sec_msb_led5, sec_msb_led6);converter convsl(sec_lsb_next3, sec_lsb_next2, sec_lsb_next1, sec_lsb_next0, sec_lsb_led0, sec_lsb_led1, sec_lsb_led2, sec_lsb_led3, sec_lsb_led4, sec_lsb_led5, sec_lsb_led6);endmodule图3 display模块converter模块：.design_name converter.inputnames I3 I2 I1 I0 .outputnames a b c d e f g0000 11111100001 11000000010 10110110011 11100110100 11001010101 01101110110 01111110111 11000101000 11111111001 11101111010 11110011011 01110011100 01010011101 00111111110 00011111111 0000001microwave模块： /microwave模块中包含着一个有限状态机micro_st，这个有限状态机负责产生控制信号。module microwave(clk, reset, test, set_time, start_cook, done, cook_time, time_load, cook, load);input clk, reset, test, set_time, start_cook, done;input 15:0 cook_time;output 15:0 time_load;output cook, load;micro_st micro_st(clk, reset, test, set_time, start_cook, done,cook,load_8888, load_clk, load_done);loader loader(cook_time, load_done, load_8888, load_clk, time_load, load);endmodule图4 Microwave模块microwave测试模块：define period 100module microwave_test;wire15:0 time_load;wire load;reg cook;reg15:0 cook_time;reg set_time,start_cook,clk,reset,test,done;initialclk=0;always #(period/2) clk=clk;initialbeginreset=0; done=0;test=0;start_cook=0;set_time=0;cook_time=0;#(period*1) start_cook=1;#(period*2) done=1;#(period*2) set_time=1; /IDLE状态，cook=0,load=1,time_load=8888#(period*2) reset=1;#(period*2) test=1; /IDLE状态，cook=0,load=1,time_load=8888 #(period*2) cook_time=12;#(period*2) test=0;#(period*2) set_time=1; /cook=0，load=1，time_load=cook_time=12#(period*1) set_time=0;#(period*2) done=0;#(period*2) start_cook=1; /timer模块开始倒计时#(period*20) $stop;endmicrowave a1(clk,reset,test,set_time,start_cook,done,cook_time,time_load,cook,load); endmoduleloader模块：/ loader : 用于给定时器timer 设置加热烘烤的时间cook_timer15:0; 定时器timer将进行数秒倒计时；/time_load,load_8888,load_done,load_clk用于top内部模块之间的通信。module loader(cook_time, load_done, load_8888, load_clk, time_load, load);input 15:0 cook_time;input load_done, load_8888, load_clk;output 15:0 time_load;output load;reg 15:0 time_load;parameter 15:0 led_8888 = 4d8, 4d8, 4d8, 4d8, led_done = 4hA, 4hB, 4hC, 4hD; /参数型assign load = (load_done | load_8888 | load_clk);always (load_8888 or load_done or cook_time)/等待load_8888,load_done,cook_time的变化。case(1b1) load_8888: time_load = led_8888;/load_8888=1，LED应显示8888，等待状态；load_done: time_load = led_done;/load_done=1，倒计时倒完；default: time_load = cook_time;/正在倒计时。endcaseendmoduleloader测试程序：define period 100module loader_test;wire15:0 time_load;wire load;reg15:0 cook_time;reg load_done,load_clk,load_8888;initialload_clk=0;always #(period/2) load_clk=load_clk;initialbeginload_done=0;load_8888=0;cook_time=0;#(period*2) load_done=1; / load=1,time_load=cook_time=0#(period*2) cook_time=4d12; /load=1,time_load=cook_time=12#(period*2) load_8888=1; /load=1,time_load=8888#(period*2) load_8888=0; #(period*2) load_done=1; /load=1,time_load=ABCD#(period*8) $stop;endloader a1(cook_time,load_done,load_8888,load_clk,time_load,load);endmoduletimer模块：module timer(time_load, clk, cook ,load, min_msb_next, min_lsb_next, sec_msb_next, sec_lsb_next, done);input 15:0 time_load;input clk, cook, load;output 3:0 min_msb_next, min_lsb_next, sec_msb_next, sec_lsb_next;output done;reg 3:0 min_msb_next, min_lsb_next, sec_msb_next, sec_lsb_next;reg 3:0 min_msb, min_lsb, sec_msb, sec_lsb;wire 15:0 time_leave;wire done;assign time_leave = (load = 1b1) ?time_load:min_msb_next,min_lsb_next,sec_msb_next,sec_lsb_next;always (time_leave or cook) beginmin_msb = time_leave15:12;/分的十位 min_lsb = time_leave11:8;/分的个位 sec_msb = time_leave7:4;/秒的十位sec_lsb = time_leave3:0;/秒的个位if (cook) beginif (sec_lsb 4b0)/秒的个位不为0beginsec_lsb = sec_lsb - 4b1; endelse if (sec_msb 4b0)/秒的十位不为0 beginsec_lsb = 4d9;sec_msb = sec_msb - 4b1;endelse if (min_lsb 4b0) /分的个位不为0beginsec_lsb = 4d9;sec_msb = 4d5;min_lsb = min_lsb - 4b1;endelse if (min_msb 4b0)/分的十位不为0beginsec_lsb = 4d9;sec_msb = 4d5;min_lsb = 4d9;min_msb = min_msb - 4b1;end/倒计时从秒的个位开始减1，秒的个位减到0后，秒的十位减1，秒的个位变为9，然后再从秒的个位开始减1。以此类推，知道定的时间被减完。elsebeginsec_lsb = 4d13; sec_msb = 4d12;min_lsb = 4d11;min_msb = 4d10;/ABCD，倒计时结束。endendendalways (posedge clk) begin min_msb_next = min_msb; min_lsb_next = min_lsb;sec_msb_next = sec_msb; sec_lsb_next = sec_lsb; endassign done = (min_msb_next, min_lsb_next, sec_msb_next, sec_lsb_next = 0);endmoduletimer的测试程序：define period 100module timer_test;reg 15:0 time_load;reg clk, cook, load;wire 3:0 min_msb_next, min_lsb_next, sec_msb_next, sec_lsb_next;wire done;initialclk=0;always#(period/2) clk = clk;initial begintime_load=0; cook=0; load=0;#(period*1) load=1; #(period*2) time_load=1;#(period*1) time_load=0; /load=1，时time_leave=time_load;#(period*2) load=0;#(period*1) time_load=1;#(period*2) time_load=0;/load=0,time_leave=min_msb_next,min_lsb_next,sec_msb_next,sec_lsb_next#(period*2) timer_load=4d23#(period*2) cook=1;/开始倒计时#(period*20) cook=0;#(period*40) $stop;endtimer a1(.time_load(time_load),.clk(clk),.cook(cook) ,.load(load), .min_msb_next(min_msb_next),.min_lsb_next(min_lsb_next),.sec_msb_next(sec_msb_next), .sec_lsb_next(sec_lsb_next), .done(done);endmodulemicro_st模块：module micro_st(clk, reset, test, set_time, start_cook, done,cook, load_8888, load_clk, load_done);input clk, reset, test, set_time, start_cook, done;output cook, load_8888, load_clk, load_done;reg cook, load_8888, load_clk, load_done;parameter 2:0 IDLE = 3d0, LAMP_TEST = 3d1, SET_CLOCK = 3d2, TIMER = 3d3, DONE_MSG = 3d4;reg 2:0 state, next_state;/初始状态为IDLE，当test=1时，next_state=LAMP_TEST，输出load_8888=1后回到 IDLE状态。/当test=0,set_time=1时，next_state=SET_CLOCK，输出load_clk=1后回到IDLE状态。/当test=0,set_time=0，start_cook&!done=1(start_cook=1,done=0)时，next_state=TIMER，输出cook=1，timer模块开始计时。进入TIMER状态后，若done任为0则继续倒计时；若done为1，则进入DONE_MSG状态，输出load_done=1，下个状态回到IDLE。/当reset=0时，从当前状态回到IDLE。always (state or test or done or set_time or start_cook)begin next_state = IDLE; load_8888, load_clk, cook, load_done = 4b0; case(state) IDLE: begin if (test) begin next_state = LAMP_TEST; load_8888 = 1b1; end else if (set_time) begin next_state = SET_CLOCK; load_clk = 1b1; end else if (start_cook & !done)begin next_state = TIMER; cook = 1b1; end else begin next_state = IDLE; load_8888, load_clk, cook, load_done = 4b0; end end LAMP_TEST: begin load_8888 = 1b1; next_state = IDLE; end SET_CLOCK: begin load_clk = 1b1; next_state = IDLE; end TIMER: begin if (!done) begin cook = 1b1; next_state = TIMER; end else begin next_state = DONE_MSG; load_done = 1b1; end end DONE_MSG: begin load_done = 1b1; next_state = IDLE; end endcaseendalways ( posedge clk or negedge reset)if (!reset) state = IDLE;else state = next_state;endmodulemicro_st测试程序define period 100module micro_st_test;reg clk, reset, test, set_time, start_cook, done;wire cook, load_8888, load_clk, load_done;initialclk=0;always#(period/2) clk = clk;initial beginreset=0; test=0; set_time=0; start_cook=0; done=0;#(period*1) reset=1;#(period*2) test=1;#(period*2) test=0;set_time=1;#(period*2) set_time=0;#(period*2) start_cook=1;#(period*2) done=1;#(period*2) start_cook=0;#(period*2) reset=0;#(period*20) $stop;endmicro_st a1(.reset(reset),.clk(clk),.test(test) ,.set_time(set_time), .start_cook(start_cook), .cook(cook), .load_8888(load_8888), .load_clk(load_clk), .done(done),.load_done(load_done);endmodule二、模块内部之间通信(1) reset=0或test=1时，回到等待状态IDLE，输出load_8888=1到loader模块。此时在loader模块中load=1，输出time_load=8888到timer模块中。在timer模块中cook=0，所以timer不进行倒计时，display模块中LED显示8888。(2) test=0，set_time=1时，下个状态为SET_CLOCK，输出load_clk=1到loader模块，cook_time被加载到loader模块。loader模块输出load=1到timer模块，而此时timer模块中cook=1，所以不进行倒计时，display模块直接输出设置的时间值。(3) test=0，set_time=0，start_time=1，done=0时，输出cook=1到timer模块。此时loader模块输出time_loader=cook_time到timer模块，timer模块开始倒计时。timer模块倒计时完成后，输出done=1，然后进入DONE_MSG状态，输出load_done=1到loader模块。此时loader模块中time_load=led_done=ABCD，load=1，所以timer模块中time_leave=ABCD,display模块显示数据，最后再次进入IDLE状态。三、脚本脚本 run_top.tclset SCRIPT_DIR ./scriptset MAPPED_DIR ./dbset NETLIST_DIR ./signoffset REPORT_DIR ./rptset SOURCE_DIR ./srcset active_design top set version _2010Sepsource ./script/read_src.tcl -v -esource ./script/set_cons.tcl -v -e#*#Compileredirect $REPORT_DIR/$active_design$version_check_design.rpt check_designredirect $REPORT_DIR/$active_design$version_check_timing.rpt check_timing#compilecurrent_design $active_design# seems costing too much# set_ultra_optimization true# set_dw_prefer_mc_inside trueset_structurecompileredirect $REPORT_DIR/$active_design$version.rpt report_constraint -all_violatorscompile -map_effort high -area_effort high -power_effort high -inc#*#write out rpt and netlist# change_names -rules BORG -hierarchywrite -hierarchy -output $NETLIST_DIR/$active_design$version.dbwrite -hierarchy -format verilog -output $NETLIST_DIR/$active_design$version.vwrite_sdf $NETLIST_DIR/$active_design$version.sdfwrite_sdc $NETLIST_DIR/$active_design$version.sdcredirect -append $REPORT_DIR/$active_design$version.rpt report_arearedirect -append $REPORT_DIR/$active_design$version.rpt report_cellredirect -append $REPORT_DIR/$active_design$version.rpt check_designredirect -append $REPORT_DIR/$active_design$version.rpt report_timing read_src.tcl#Read Design Fileread_fil