4选1多路选择器MUX41a Verlog HDL代码.doc

用共阴极7段数码管显示1,2，3，4 ，5， 6, 7， 8 ，9， A，b，c，d，E， F十六进制；根据数码管的显示特性可得以下对应关系；数字a b c d e f 数码管的显示1bc23456789AbCdEF0 verilog HDL代码如下module decode (data_in ,EN ,data_out );input 3:0 data_in ;input EN ;output 6:0 data_out ;reg 6:0 data_out ;always (data_in or EN )begin data_out = 7b000000; if (EN = 1) case (data_in ) 4b0000: data_out = 7b0111111; / 0 4b0001: data_out = 7b0000110; / 1 4b0010: data_out = 7b1011011; / 2 4b0011: data_out = 7b1001111; / 3 4b0100: data_out = 7b1100110; / 4 4b0101: data_out = 7b1101101; / 5 4b0110: data_out = 7b1111100; / 6 4b0111: data_out = 7b0000111; / 7 4b1000: data_out = 7b1111111; / 8 4b1001: data_out = 7b1100111; / 9 4b1010: data_out = 7b1110111; / A 4b1011: data_out = 7b1111100; / b 4b1100: data_out = 7b1011000; / c 4b1101: data_out = 7b1011110; / d 4b1110: data_out = 7b1111001; / E 4b1111: data_out = 7b1110001; / F default: data_out = 7b0000000; endcaseendendmodulemodule Decoder_7_seg(EN，D，C，B，A，a_，b_，c_，d_，e_，f_，g_);input EN;input D，C，B，A;output a_，b_，c_，d_，e_，f_，g_;reg a_，b_，c_，d_，e_，f_，g_;always (EN or D or C or B or A)beginif(EN = 1b0)a_，b_，c_，d_，e_，f_，g_ = 7b0;elsebegincase(D，C，B，A)4b0000 : a_，b_，c_，d_，e_，f_，g_ = 7b1111110;4b0001 : a_，b_，c_，d_，e_，f_，g_ = 7b0110000;4b0010 : a_，b_，c_，d_，e_，f_，g_ = 7b1101101;4b0011 : a_，b_，c_，d_，e_，f_，g_ = 7b1111001;4b0100 : a_，b_，c_，d_，e_，f_，g_ = 7b0110011;4b0101 : a_，b_，c_，d_，e_，f_，g_ = 7b1011011;4b0110 : a_，b_，c_，d_，e_，f_，g_ = 7b0011111;4b0111 : a_，b_，c_，d_，e_，f_，g_ = 7b1110000;4b1000 : a_，b_，c_，d_，e_，f_，g_ = 7b1111111;4b1001 : a_，b_，c_，d_，e_，f_，g_ = 7b1110011;4b1010 : a_，b_，c_，d_，e_，f_，g_ = 7b0001101;4b1011 : a_，b_，c_，d_，e_，f_，g_ = 7b0011001;4b1100 : a_，b_，c_，d_，e_，f_，g_ = 7b0100011;4b1101 : a_，b_，c_，d_，e_，f_，g_ = 7b1001011;4b1110 : a_，b_，c_，d_，e_，f_，g_ = 7b0001111;4b1111 : a_，b_，c_，d_，e_，f_，g_ = 7b0000000;default : a_，b_，c_，d_，e_，f_，g_ = 7b0000000;endcaseendendendmodulemodule YM_3_8 (A, data_out );input 2:0 A;output 7:0 data_out ;reg 7:0 data_out ;always ( A ) begin data_out = 7b0000_0001; case ( A ) 3b000: data_out = 7b0000_0001; / 0 3b001: data_out = 7b0000_0010; / 1 3b010: data_out = 7b0000_0100; / 2 3b011: data_out = 7b0000_1000; / 3 3b100: data_out = 7b0001_0000; / 4 3b101: data_out = 7b0010_0000; / 5 3b110: