飞思卡尔XS128单片机寄存器.doc

/* Based on CPU DB MC9S12XS256_112, version 3.00.008 (RegistersPrg V2.26) */* #* Filename : mc9s12xs128.h* Processor : MC9S12XS128CAL* FileFormat: V2.26* DataSheet : MC9S12XS256RMV1 Rev. 1.03 06/2008* Compiler : CodeWarrior compiler* Date/Time : 23.2.2009, 15:08* Abstract :* This header implements the mapping of I/O devices.* (c) Copyright UNIS, a.s. 1997-2009* UNIS, a.s.* Jundrovska 33* 624 00 Brno* Czech Republic* http : * mail : * CPU Registers Revisions:* - 20.02.2008, V3.00.0:* - Corrected registers address: ATD0DIENL 0x02CC = 0x02CD* - Removed bit FSTATRSVD.* - REASON: Changes in the data sheet (from Rev. 1.00 5/2007 to Rev. 1.01 8/2007).* - 17.04.2008, V3.00.1:* - Renamed registers TCNTH/L = TCNTHi/Lo, TCxH/L = TCxHi/Lo.* - REASON: Bug-fix (#6048 from the UNIS Issue Manager).* - 21.05.2008, V3.00.2:* - Added register VREGHTTR. Added interrupt vector Vhti.* - REASON: Changes in the data sheet (from Rev. 1.01 08/2007 to Rev. 1.02 02/2008).* - 23.02.2009, V3.00.3:* - Corrected definition of 16-bit Port AD0 registers to use properly AD0L/AD0H parts.* - REASON: Bug-fix (#7029 in UNIS Issue Manager).* File-Format-Revisions:* - 19.07.2007, V2.18 :* - Improved number of blanked lines inside register structures* - 06.08.2007, V2.19 :* - CPUDB revisions generated ahead of the file-format revisions.* - 11.09.2007, V2.20 :* - Added comment about initialization of unbonded pins.* - 02.01.2008, V2.21 :* - Changes have not affected this file (because they are related to another family)* - 13.02.2008, V2.22 :* - Changes have not affected this file (because they are related to another family)* - 20.02.2008, V2.23 :* - Termination of pragma V30toV31Compatible added, #5708* - 03.07.2008, V2.24 :* - Added support for bits with name starting with number (like 1HZ)* - 28.11.2008, V2.25 :* - StandBy RAM array declaration for ANSI-C added* - 1.12.2008, V2.26 :* - Duplication of bit (or bit-group) name with register name is not marked as a problem, is register is internal only and it is not displayed in I/O map.* Not all general-purpose I/O pins are available on all packages or on all mask sets of a specific* derivative device. To avoid extra current drain from floating input pins, the user抯 reset* initialization routine in the application program must either enable on-chip pull-up devices* or change the direction of unconnected pins to outputs so the pins do not float.* #*/#ifndef _MC9S12XS128_H#define _MC9S12XS128_H/* Types definition */typedef unsigned char byte;typedef unsigned int word;typedef unsigned long dword;typedef unsigned long dlong2;#define REG_BASE 0x0000 /* Base address for the I/O register block */#pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */#pragma OPTION ADD V30toV31Compatible -BfaGapLimitBits4294967295 /*this guarantee correct bitfield positions*/* interrupt vector numbers */#define VectorNumber_Vsi 119#define VectorNumber_Vsyscall 118#define VectorNumber_VReserved118 117#define VectorNumber_VReserved117 116#define VectorNumber_VReserved116 115#define VectorNumber_VReserved115 114#define VectorNumber_VReserved114 113#define VectorNumber_VReserved113 112#define VectorNumber_VReserved112 111#define VectorNumber_VReserved111 110#define VectorNumber_VReserved110 109#define VectorNumber_VReserved109 108#define VectorNumber_VReserved108 107#define VectorNumber_VReserved107 106#define VectorNumber_VReserved106 105#define VectorNumber_VReserved105 104#define VectorNumber_VReserved104 103#define VectorNumber_VReserved103 102#define VectorNumber_VReserved102 101#define VectorNumber_VReserved101 100#define VectorNumber_VReserved100 99#define VectorNumber_VReserved99 98#define VectorNumber_VReserved98 97#define VectorNumber_Vatd0compare 96#define VectorNumber_VReserved96 95#define VectorNumber_VReserved95 94#define VectorNumber_VReserved94 93#define VectorNumber_VReserved93 92#define VectorNumber_VReserved92 91#define VectorNumber_VReserved91 90#define VectorNumber_VReserved90 89#define VectorNumber_VReserved89 88#define VectorNumber_VReserved88 87#define VectorNumber_VReserved87 86#define VectorNumber_VReserved86 85#define VectorNumber_VReserved85 84#define VectorNumber_VReserved84 83#define VectorNumber_VReserved83 82#define VectorNumber_VReserved82 81#define VectorNumber_VReserved81 80#define VectorNumber_VReserved79 79#define VectorNumber_VReserved78 78#define VectorNumber_VReserved77 77#define VectorNumber_VReserved76 76#define VectorNumber_VReserved75 75#define VectorNumber_VReserved74 74#define VectorNumber_VReserved73 73#define VectorNumber_VReserved72 72#define VectorNumber_VReserved71 71#define VectorNumber_VReserved70 70#define VectorNumber_Vpit3 69#define VectorNumber_Vpit2 68#define VectorNumber_Vpit1 67#define VectorNumber_Vpit0 66#define VectorNumber_Vhti 65#define VectorNumber_Vapi 64#define VectorNumber_Vlvi 63#define VectorNumber_VReserved62 62#define VectorNumber_VReserved61 61#define VectorNumber_VReserved60 60#define VectorNumber_VReserved59 59#define VectorNumber_VReserved58 58#define VectorNumber_Vpwmesdn 57#define VectorNumber_Vportp 56#define VectorNumber_VReserved55 55#define VectorNumber_VReserved54 54#define VectorNumber_VReserved53 53#define VectorNumber_VReserved52 52#define VectorNumber_VReserved51 51#define VectorNumber_VReserved50 50#define VectorNumber_VReserved49 49#define VectorNumber_VReserved48 48#define VectorNumber_VReserved47 47#define VectorNumber_VReserved46 46#define VectorNumber_VReserved45 45#define VectorNumber_VReserved44 44#define VectorNumber_VReserved43 43#define VectorNumber_VReserved42 42#define VectorNumber_VReserved41 41#define VectorNumber_VReserved40 40#define VectorNumber_Vcan0tx 39#define VectorNumber_Vcan0rx 38#define VectorNumber_Vcan0err 37#define VectorNumber_Vcan0wkup 36#define VectorNumber_Vflash 35#define VectorNumber_Vflashfd 34#define VectorNumber_VReserved33 33#define VectorNumber_VReserved32 32#define VectorNumber_VReserved31 31#define VectorNumber_VReserved30 30#define VectorNumber_Vcrgscm 29#define VectorNumber_Vcrgplllck 28#define VectorNumber_VReserved27 27#define VectorNumber_VReserved26 26#define VectorNumber_Vporth 25#define VectorNumber_Vportj 24#define VectorNumber_VReserved23 23#define VectorNumber_Vatd0 22#define VectorNumber_Vsci1 21#define VectorNumber_Vsci0 20#define VectorNumber_Vspi0 19#define VectorNumber_Vtimpaie 18#define VectorNumber_Vtimpaaovf 17#define VectorNumber_Vtimovf 16#define VectorNumber_Vtimch7 15#define VectorNumber_Vtimch6 14#define VectorNumber_Vtimch5 13#define VectorNumber_Vtimch4 12#define VectorNumber_Vtimch3 11#define VectorNumber_Vtimch2 10#define VectorNumber_Vtimch1 9#define VectorNumber_Vtimch0 8#define VectorNumber_Vrti 7#define VectorNumber_Virq 6#define VectorNumber_Vxirq 5#define VectorNumber_Vswi 4#define VectorNumber_Vtrap 3#define VectorNumber_Vcop 2#define VectorNumber_Vclkmon 1#define VectorNumber_Vreset 0/* interrupt vector table */#define Vsi 0x0000FF10#define Vsyscall 0x0000FF12#define VReserved118 0x0000FF14#define VReserved117 0x0000FF16#define VReserved116 0x0000FF18#define VReserved115 0x0000FF1A#define VReserved114 0x0000FF1C#define VReserved113 0x0000FF1E#define VReserved112 0x0000FF20#define VReserved111 0x0000FF22#define VReserved110 0x0000FF24#define VReserved109 0x0000FF26#define VReserved108 0x0000FF28#define VReserved107 0x0000FF2A#define VReserved106 0x0000FF2C#define VReserved105 0x0000FF2E#define VReserved104 0x0000FF30#define VReserved103 0x0000FF32#define VReserved102 0x0000FF34#define VReserved101 0x0000FF36#define VReserved100 0x0000FF38#define VReserved99 0x0000FF3A#define VReserved98 0x0000FF3C#define Vatd0compare 0x0000FF3E#define VReserved96 0x0000FF40#define VReserved95 0x0000FF42#define VReserved94 0x0000FF44#define VReserved93 0x0000FF46#define VReserved92 0x0000FF48#define VReserved91 0x0000FF4A#define VReserved90 0x0000FF4C#define VReserved89 0x0000FF4E#define VReserved88 0x0000FF50#define VReserved87 0x0000FF52#define VReserved86 0x0000FF54#define VReserved85 0x0000FF56#define VReserved84 0x0000FF58#define VReserved83 0x0000FF5A#define VReserved82 0x0000FF5C#define VReserved81 0x0000FF5E#define VReserved79 0x0000FF60#define VReserved78 0x0000FF62#define VReserved77 0x0000FF64#define VReserved76 0x0000FF66#define VReserved75 0x0000FF68#define VReserved74 0x0000FF6A#define VReserved73 0x0000FF6C#define VReserved72 0x0000FF6E#define VReserved71 0x0000FF70#define VReserved70 0x0000FF72#define Vpit3 0x0000FF74#define Vpit2 0x0000FF76#define Vpit1 0x0000FF78#define Vpit0 0x0000FF7A#define Vhti 0x0000FF7C#define Vapi 0x0000FF7E#define Vlvi 0x0000FF80#define VReserved62 0x0000FF82#define VReserved61 0x0000FF84#define VReserved60 0x0000FF86#define VReserved59 0x0000FF88#define VReserved58 0x0000FF8A#define Vpwmesdn 0x0000FF8C#define Vportp 0x0000FF8E#define VReserved55 0x0000FF90#define VReserved54 0x0000FF92#define VReserved53 0x0000FF94#define VReserved52 0x0000FF96#define VReserved51 0x0000FF98#define VReserved50 0x0000FF9A#define VReserved49 0x0000FF9C#define VReserved48 0x0000FF9E#define VReserved47 0x0000FFA0#define VReserved46 0x0000FFA2#define VReserved45 0x0000FFA4#define VReserved44 0x0000FFA6#define VReserved43 0x0000FFA8#define VReserved42 0x0000FFAA#define VReserved41 0x0000FFAC#define VReserved40 0x0000FFAE#define Vcan0tx 0x0000FFB0#define Vcan0rx 0x0000FFB2#define Vcan0err 0x0000FFB4#define Vcan0wkup 0x0000FFB6#define Vflash 0x0000FFB8#define Vflashfd 0x0000FFBA#define VReserved33 0x0000FFBC#define VReserved32 0x0000FFBE#define VReserved31 0x0000FFC0#define VReserved30 0x0000FFC2#define Vcrgscm 0x0000FFC4#define Vcrgplllck 0x0000FFC6#define VReserved27 0x0000FFC8#define VReserved26 0x0000FFCA#define Vporth 0x0000FFCC#define Vportj 0x0000FFEE/#define VReserved23 0x0000FFD0#define Vatd0 0x0000FFD2#define Vsci1 0x0000FFD4#define Vsci0 0x0000FFD6#define Vspi0 0x0000FFD8#define Vtimpaie 0x0000FFDA#define Vtimpaaovf 0x0000FFDC#define Vtimovf 0x0000FFDE#define Vtimch7 0x0000FFE0#define Vtimch6 0x0000FFE2#define Vtimch5 0x0000FFE4#define Vtimch4 0x0000FFE6#define Vtimch3 0x0000FFE8#define Vtimch2 0x0000FFEA#define Vtimch1 0x0000FFEC#define Vtimch0 0x0000FFCE#define Vrti 0x0000FFF0#define Virq 0x0000FFF2#define Vxirq 0x0000FFF4#define Vswi 0x0000FFF6#define Vtrap 0x0000FFF8#define Vcop 0x0000FFFA#define Vclkmon 0x0000FFFC#define Vreset 0x0000FFFE/* registers I/O map */* PORTAB - Port AB Data Register; 0x00000000 */typedef union word Word; /* Overlapped registers: */ struct /* PORTA - Port A Data Register; 0x00000000 */ union byte Byte; struct byte PA0 :1; /* Port A Bit 0 */ byte PA1 :1; /* Port A Bit 1 */ byte PA2 :1; /* Port A Bit 2 */ byte PA3 :1; /* Port A Bit 3 */ byte PA4 :1; /* Port A Bit 4 */ byte PA5 :1; /* Port A Bit 5 */ byte PA6 :1; /* Port A Bit 6 */ byte PA7 :1; /* Port A Bit 7 */ Bits; PORTASTR; #define PORTA _PORTAB.Overlap_STR.PORTASTR.Byte #define PORTA_PA0 _PORTAB.Overlap_STR.PORTASTR.Bits.PA0 #define PORTA_PA1 _PORTAB.Overlap_STR.PORTASTR.Bits.PA1 #define PORTA_PA2 _PORTAB.Overlap_STR.PORTASTR.Bits.PA2 #define PORTA_PA3 _PORTAB.Overlap_STR.PORTASTR.Bits.PA3 #define PORTA_PA4 _PORTAB.Overlap_STR.PORTASTR.Bits.PA4 #define PORTA_PA5 _PORTAB.Overlap_STR.PORTASTR.Bits.PA5 #define PORTA_PA6 _PORTAB.Overlap_STR.PORTASTR.Bits.PA6 #define PORTA_PA7 _PORTAB.Overlap_STR.PORTASTR.Bits.PA7 #define PORTA_PA0_MASK 1 #define PORTA_PA1_MASK 2 #define PORTA_PA2_MASK 4 #define PORTA_PA3_MASK 8 #define PORTA_PA4_MASK 16 #define PORTA_PA5_MASK 32 #define PORTA_PA6_MASK 64 #define PORTA_PA7_MASK 128 /* PORTB - Port B