第1章 对外围硬件的访问(EDA技术).doc

EDA技术第六章 对外围硬件的访问第一节 LED一、电路结构共阴极4位LED数码管（点亮电平为高电平有效）循环点亮模式：依次点亮4个数码管，每次选通一位数码管，点亮持续一段时间后，选通下一位数码管，依次点亮一次后循环，实现循环点亮。二、VerilogHDL代码/-/ Module : led/ Filename : led.v/ Author : Wu Bin/ Date : Jul.25,2006/ Version : 1.0/ Discription: Function: 4 LED /* 注：1、pin6，8，9，12为位选择引角，低电平有效 2、采用循环点亮方式*/-timescale 10ns/10nsdefine DELAY 18h3ffff/shift every 5ms（时钟50MHz）define LED 4 /LED单元数量define DIGIT1 8b01101011/udefine DIGIT2 8b11101011/odefine DIGIT3 8b01111010 /ydefine DIGIT4 8b11111111/8./-/ Module/-module led( reset, clock, led_active_in, /启动信号 led_select_out, /选择当前点亮的LED单元 led_data_out /当前点亮的LED所显示的内容);/-/ Interface Declaration/- input reset; input clock; input led_active_in; output 3:0 led_select_out; output 7:0 led_data_out;/-/ Interface Declaration/- wire reset; wire clock; wire led_active_in; wire 3:0 led_select_out; wire 7:0 led_data_out;/-/ Internal Declaration/- reg 2:0 state; reg 2:0 cnt; /count 4 times（4 LEDs） reg 17:0 DelayCnt;/显示delay 5ms reg 3:0 select; /显示位选择 reg 7:0 data; /显示数据/-/ Parameter Declaration/- parameter IDLE = 3h0,STAT_DISP = 3h1, /cnt计数次数判断，判断是否循环显示了一次DISP= 3h2, /数据输出送显DELAY= 3h3, /显示持续5msDISP_END= 3h4; /结束循环显示一次/-/ Main Block/- /state machine always (posedge clock or posedge reset) begin if (reset) state = IDLE; else begin case (state) IDLE: if (led_active_in) state = STAT_DISP; STAT_DISP: begin if (cnt = LED) state = DISP_END;else state =DISP; end/先在前一状态更新cnt，再在下一状态根据cnt的值确定select和data取值 DISP: state = DELAY; DELAY: if (DelayCnt = DELAY) state = STAT_DISP;/在DISP_END时才对select和data清零，使二变量在DISP和DELAY一值保持 DISP_END: state = IDLE; endcase end end /DelayCnt always (posedge clock or posedge reset) begin if (reset) DelayCnt = 0; else begin case (state) DELAY: begin if (DelayCnt = DELAY) DelayCnt = 0;else DelayCnt = DelayCnt + 1; end endcase end end /cnt always (posedge clock or posedge reset) begin if (reset)cnt = 0; else begin case (state) STAT_DISP: begin if (cnt = LED)cnt = 0;elsecnt = cnt + 1; end endcase end end /select随cnt改变而改变，选择4次（每次5ms）后清零 always (posedge clock or posedge reset) begin if (reset)select = 0; else begin case (state) IDLE:select = 0; DISP: begin case (cnt) 3h1:select = 4b0001; 3h2:select = 4b0010; 3h3:select = 4b0100; 3h4:select = 4b1000;endcase end DISP_END:select = 0; endcase end end /data：随cnt改变而改变，显示4次（每次5ms）后清零 always (posedge clock or posedge reset) begin if (reset)data = 0; else begin case (state) IDLE:data = 0; DISP: begin case (cnt) 3h1:data = DIGIT1; 3h2:data = DIGIT2; 3h3:data = DIGIT3; 3h4:data = DIGIT4;endcase end DISP_END:data = 0; endcase end end assign led_select_out = select; /位选择为低电平有效 assign led_data_out = data;endmodule 第二节 SRAM一、芯片说明1SRAMSRAM是英文Static RAM的缩写，它是一种具有静止存取功能的内存，不需要刷新电路即能保存它内部存储的数据。不像DRAM内存那样需要刷新电路，每隔一段时间，固定要对DRAM刷新充电一次，否则内部的数据即会消失，因此SRAM具有较高的性能，但是SRAM也有它的缺点，即它的集成度较低，相同容量的DRAM内存可以设计为较小的体积，但是SRAM却需要很大的体积。2IS61LV51216-10T说明高速8M-bit静态RAM，响应时间：10ns形式：512k个16bit位宽存储单元（5121024=219寻址空间）地址线：19位数据线：16位片选：#CE高位字节选通：#UB低位字节选通：#LB写使能：#WE读使能：#OE电源：DC3.3V3读时序读时序开关特性：tRC读周期Read Cycle TimeMin=10nstAA地址接入时间Adress Access TimeMax=10 nstACE#CE 接入时间#CE Access TimeMax=10 nstDOE#OE 接入时间#OE Access TimeMax=4 nstOHA输出保持时间Output Hold TimeMin=3 nstHZCE#CE到高阻输出#CE to High-Z OutputMin=4 nstHZOE#OE到高阻输出#OE to High-Z OutputMin=4 ns4写时序写时序开关特性：tWC写周期Write Cycle TimeMin=10nstSCE#CE到写结束时间#CE to Write EndMin=8nstSA地址建立时间Address Setup TimeMin=0nstHA写结束后地址保持时间Address Hold from Write EndMin=0nstAW地址建立到写结束时间Address Setup Time to Write EndMin=8nstPWE#WE宽度#WE Pulse WidthMin=10 nstSD数据建立到写结束Data Setup to Write EndMin=6 nstHD写结束后数据保持时间Data Hold from Write EndMin=0nstHZWE#WE置低到高阻输出#WE LOW to High-Z OutputMax=5nstLZWE#WE置高到低阻输出#WE HIGH to Low-Z OutputMin=2ns二、电路结构说明1每两片sram并联成32位数据位宽，片选/CE作为地址输出最高位，地址最高位为1，ce1有效并置低，最高位为0，ce2有效并置低；2读使能oe、写使能we、数据线、地址线均以总线形式相连接。3sram的LB和UB电路上直接接地。三、SRAM接口代码/-/ Module : sram/ Filename : sram.v/ Author : Wu Bin/ Date : Jul.7,2006/ Version : 1.0/ Discription: Function: sram 公司:ISSI 型号:IS61LV51216/*注：1、每两片sram并联成32位数据位宽，片选/CE由地址输出最高位决定，最高位为1，ce1有效并置低，最高位为0，ce2有效并置低2、读使能oe和写使能we都为低电平有效3、sram的LB和UB电路上已经直接接地4、读周期：2，第一个周期给读使能，第二个周期锁存数据clock: _|_|_|_ sram_re_in: _|_sram_rdata_out: - 锁存时间： _|_5、写周期：3，由于双向口的输出内部有缓存，所以实际写数据输出会延时一个周期 clock: _|_|_|_sram_we_in: _|_ sram_wdata_in: _sram_data_inout: _(data)这里考虑了FPGA的IO端口输出和输入延时，一般在3-5ns左右，一个来回10ns左右,还需考虑PCB布线产生的延时*/-timescale 10ns/10nsmodule sram( reset, clock, /IO port to external sram sram_addr_out, sram_data_inout, sram_nce1_out, sram_nce2_out, sram_nwe_out, sram_noe_out, /IO port to internal module sram_waddr_in, sram_wdata_in, sram_we_in, sram_raddr_in, sram_rdata_out, sram_re_in);/-/ Interface Declaration/- input reset; input clock; /IO port to external sram output 18:0 sram_addr_out; inout 31:0 sram_data_inout; output sram_nce1_out; output sram_nce2_out; output sram_nwe_out; output sram_noe_out; /IOport to internal module input 19:0 sram_waddr_in; input 31:0 sram_wdata_in; input sram_we_in; input 19:0 sram_raddr_in; output 31:0 sram_rdata_out; input sram_re_in;/-/ Interface Declaration/- wire reset; wire clock; /IO port to external sram wire 18:0 sram_addr_out; wire 31:0 sram_data_inout; wire sram_nce1_out; wire sram_nce2_out; wire sram_nwe_out; wire sram_noe_out; /IOport to internal module wire 19:0 sram_waddr_in; wire 31:0 sram_wdata_in; wire sram_we_in; wire 19:0 sram_raddr_in; wire 31:0 sram_rdata_out; wire sram_re_in;/-/ Internal Declaration/- wire ce1; wire ce2; reg 19:0 addr; reg 31:0 data;/-/ Parameter Declaration/-/-/ Main Block/- /addr always (sram_waddr_in or sram_we_in or sram_raddr_in or sram_re_in) begin if (sram_we_in) addr = sram_waddr_in; else if (sram_re_in) addr = sram_raddr_in; else addr = 0; end assign sram_addr_out = addr18:0; /ce assign ce1 = (addr19 = 0) ? 1b1 : 0; assign ce2 = (addr19 = 1) ? 1b1 : 0; /inout data port always (posedge clock or posedge reset) begin if (reset) data = 32h0; else data = sram_wdata_in; end assign sram_data_inout = (sram_we_in) ? data : 32hz; assign sram_rdata_out = sram_data_inout;/- assign sram_nce1_out = ce1; assign sram_nce2_out = ce2; assign sram_nwe_out= sram_we_in; assign sram_noe_out = sram_re_in;endmodule四、SRAM访问代码1模块之间的镶嵌关系2模块的镶嵌格式功能描述：写入4个数据（1-4）到地址1-4，读出后送入串口/-/ Module : SramTest/ Filename : SramTest.v/ Author : Wu Bin/ Date : Jul.10,2006/ Version : 1.0/ Discription: Function: sram test program/-timescale 10ns/10nsdefine DATA_NUM3d4module SramTest( reset, clock, SramTest_active_in, /SramTest_end_out, /IO port to external sram SramTest_addr_out, SramTest_data_inout, SramTest_nce1_out, SramTest_nce2_out, SramTest_nwe_out, SramTest_noe_out, /serial port SramTest_RxD_in, SramTest_TxD_out);/-/ Interface Declaration/- input reset; input clock; input SramTest_active_in; /output SramTest_end_out; /IO port to external sram output 18:0 SramTest_addr_out; inout 31:0 SramTest_data_inout; output SramTest_nce1_out; output SramTest_nce2_out; output SramTest_nwe_out; output SramTest_noe_out; /serial port input SramTest_RxD_in; output SramTest_TxD_out;/-/ Interface Declaration/- wire reset; wire clock; wire SramTest_active_in; /wire SramTest_end_out; /IO port to external sram wire 18:0 SramTest_addr_out; wire 31:0 SramTest_data_inout; wire SramTest_nce1_out; wire SramTest_nce2_out; wire SramTest_nwe_out; wire SramTest_noe_out; /serial port wire SramTest_RxD_in; wire SramTest_TxD_out;/-/ Internal Declaration/- /IO port to sram module wire 19:0 SramTest_sram_waddr_out; /写地址输出到sram wire 31:0 SramTest_sram_wdata_out; /写数据输出到sram wire SramTest_sram_we_out; /写使能输出到sram wire 19:0 SramTest_sram_raddr_out; /读地址输出到sram wire 31:0 SramTest_sram_rdata_in; /从sram返回读数据 wire SramTest_sram_re_out; /读使能输出到sram /IO to serial port module /receive data for tranmitting to serial port wire SramTest_SerialPort_DataInValid_out; /串口发送模式启动信号to串口 wire 7:0 SramTest_SerialPort_DataIn_out; /串口待发送数据to串口 wire SramTest_SerialPort_DataInEnd_in; /发送结束返回信号from串口 /send receiving serial data to fpga wire SramTest_SerialPort_DataOutValid_in; /串口接收数据结束from串口 wire 7:0 SramTest_SerialPort_DataOut_in; /串口接收的数据from串口 / reg 3:0 state; /状态机 reg 19:0 cnt; /数据读写次数计数 reg 31:0 io_buf; /从sram读入数据缓冲 reg 7:0 SramTest_SerialPort_DataIn; /串口待发送数据缓冲/-/ Parameter Declaration/- parameter IDLE = 4h1, STAT_WR =4h2, /写状态判断 WR_DATA1 =4h3,/给写使能、地址，数据赋值 WR_DATA2 =4h4,/数据输出 STAT_WR_END =4h5, STAT_RD_SD =4h6, /读及发送状态判断 RD_DATA1 =4h7, /给读使能、地址，锁存数据 START_SD_DATA = 4h8, /数据发送开始 SD_DATA1 =4h9, /最高位 SD_DATA2 =4ha, SD_DATA3 =4hb, SD_DATA4 =4hc, /最低位 STAT_RD_SD_END = 4hd, /数据发送结束 BLOCK_END =4he; /块结束，并锁死/-/ Main Block/- /state machine always (posedge clock or posedge reset) begin if (reset) state = IDLE; else begin case (state) IDLE: begin if (SramTest_active_in) state = STAT_WR; end /write STAT_WR: begin if (cnt = DATA_NUM) state = STAT_WR_END;else state = WR_DATA1; end WR_DATA1: state = WR_DATA2; WR_DATA2: state = STAT_WR; STAT_WR_END: state = STAT_RD_SD; /read & send STAT_RD_SD: begin if (cnt = DATA_NUM) state = STAT_RD_SD_END;else state = RD_DATA1; end RD_DATA1: state = START_SD_DATA; /send 4 times START_SD_DATA: state = SD_DATA1; SD_DATA1: if (SramTest_SerialPort_DataInEnd_in) state = SD_DATA2; SD_DATA2: if (SramTest_SerialPort_DataInEnd_in) state = SD_DATA3; SD_DATA3: if (SramTest_SerialPort_DataInEnd_in) state = SD_DATA4; SD_DATA4: if (SramTest_SerialPort_DataInEnd_in) state = STAT_RD_SD; STAT_RD_SD_END: state = BLOCK_END; /end BLOCK_END: state = BLOCK_END; /stop here endcase end end /cnt always (posedge clock or posedge reset) begin if (reset)cnt = 0; else begin case (state) IDLE:cnt = 0; STAT_WR: begin if (cnt = DATA_NUM) cnt = 0;else cnt = cnt + 1; end STAT_RD_SD: begin if (cnt = DATA_NUM) cnt = 0;else cnt = cnt + 1; end endcase end end/- /sram /we assign SramTest_sram_we_out = (state = WR_DATA1 | state = WR_DATA2) ? 1b1 : 0; /SramTest_sram_waddr_out assign SramTest_sram_waddr_out = (state = WR_DATA1 | state = WR_DATA2) ? cnt : 0; /SramTest