WarningFound201outputpinswithout.doc

Warning： Found 201 output pins without output pin load capacitance assignmentOutput Pin Load logic optionA logic option that specifies the load of an output pin in picofarads (pF). Specifying this option changes the tCO of the output pin. You use this option when you want the board load to be different than the default value reported by the QuartusII software in the Output Pin Load for Reported TCO section of the Compilation report.This option is useful for accurate modeling of tCO and power usage.For more information on device specific output delay derating factors and tCO loads, refer to individual device family data sheets, which are available from the Literature section of the Altera web site.The value entered for the output pin load should be the loading value for the board trace capacitance and target load capacitance. The Altera device pin/package capacitance is already factored in the output pin load value.This option is ignored if it is applied to anything other than an output or bidirectional pin. This option can be set in the Assignment Editor (Assignments menu). This option is available for Cyclone, CycloneII, HardCopyII, HardCopyStratix, MAX3000, MAX7000AE, MAX7000B, MAXII, Stratix, Stratix II, Stratix II GX, and StratixGX devices. This option is used for power-calculation purposes only with MAX 3000, MAX 7000A, MAX 7000AE, and MAX 7000B devicesThe following equation is used to determine the changes in the output delay and depends on the Output Pin Load option:output_delay = default_output_delay + (output_load - default_output_load) * derating factor)The following output delay derating factors, per I/O standard, are available for Stratix and Stratix GX devices:I/O Standard2 mA4 mA8 mA12 mA16 mA24 mA1.5 V160 ps/pF80 ps/pF35 ps/pFN/AN/AN/A1.5-V HSTL Class I25 ps/pF25 ps/pF25 ps/pF25 ps/pF25 ps/pF25 ps/pF1.5-V HSTL Class II20 ps/pF20 ps/pF20 ps/pF20 ps/pF20 ps/pF20 ps/pF1.5-V PCML (Stratix GX devices only)12 pF12 pF12 pF12 ps/pF12 ps/pF12 ps/pF1.8 V120 ps/pFN/A40 ps/pF25 ps/pFN/AN/A1.8-V HSTL Class I & II25 ps/pF for Class I, 20 ps/pF for Class II25 ps/pF for Class I, 20 ps/pF for Class II25 ps/pF for Class I, 20 ps/pF for Class II25 ps/pF for Class I, 20 ps/pF for Class II25 ps/pF for Class I, 20 ps/pF for Class II25 ps/pF for Class I, 20 ps/pF for Class II2.5 V75 ps/pFN/A35 ps/pF25 ps/pF18 ps/pFN/A3.3-V PCI20 ps/pF20 ps/pF20 ps/pF20 ps/pF20 ps/pF20 ps/pF3.3-V PCI-X20 ps/pF20 ps/pF20 ps/pF20 ps/pF20 ps/pF20 ps/pF3.3-V PCML12 ps/pF12 ps/pF12 ps/pF12 ps/pF12 ps/pF12 ps/pFAGP 1x20 ps/pF20 ps/pF20 ps/pF20 ps/pF20 ps/pF20 ps/pFAGP 2x20 ps/pF20 ps/pF20 ps/pF20 ps/pF20 ps/pF20 ps/pFCompact PCI20 ps/pF20 ps/pF20 ps/pF20 ps/pF20 ps/pF20 ps/pFCTT25 ps/pF25 ps/pF25 ps/pF25 ps/pF25 ps/pF25 ps/pF1.5-V Differential HSTL Class I25 ps/pF25 ps/pF25 ps/pF25 ps/pF25 ps/pF25 ps/pFDifferential SSTL-2 Class I & II20 ps/pF20 ps/pF20 ps/pF20 ps/pF20 ps/pF20 ps/pFGTL18 ps/pF for 2.5 V and 3.3 V18 ps/pF for 2.5 V and 3.3 V18 ps/pF for 2.5 V and 3.3 V18 ps/pF for 2.5 V and 3.3 V18 ps/pF for 2.5 V and 3.3 V18 ps/pF for 2.5 V and 3.3 VGTL+15 ps/pF for 2.5 V, 18 ps/pF for 3.3 V15 ps/pF for 2.5 V, 18 ps/pF for 3.3 V15 ps/pF for 2.5 V, 18 ps/pF for 3.3 V15 ps/pF for 2.5 V, 18 ps/pF for 3.3 V15 ps/pF for 2.5 V, 18 ps/pF for 3.3 V15 ps/pF for 2.5 V, 18 ps/pF for 3.3 VHyperTransport12 ps/pF12 ps/pF12 ps/pF12 ps/pF12 ps/pF12 ps/pFLVCMOS60 ps/pF30 ps/pF20 ps/pF15 ps/pFN/A8 ps/pFLVDS12 ps/pF12 ps/pF12 ps/pF12 ps/pF12 ps/pF12 ps/pFLVPECL12 ps/pF12 ps/pF12 ps/pF12 ps/pF12 ps/pF12 ps/pFLVTTLN/A60 ps/pF50 ps/pF30 ps/pF25 ps/pF15 ps/pFSSTL-2 Class I & II25 ps/pF for Class I, 20 ps/pF for Class II25 ps/pF for Class I, 20 ps/pF for Class II25 ps/pF for Class I, 20 ps/pF for Class II25 ps/pF for Class I, 20 ps/pF for Class II25 ps/pF for Class I, 20 ps/pF for Class II25 ps/pF for Class I, 20 ps/pF for Class IISSTL-3 Class I & II25 ps/pF25 ps/pF25 ps/pF25 ps/pF25 ps/pF25 ps/pFSSTL-18 Class I & II25 ps/pF25 ps/pF25 ps/pF25 ps/pF25 ps/pF25 ps/pFThe following output delay derating factors, per I/O standard, are available for Cyclone devices:I/O Standard2 mA4 mA8 mA12 mA16 mA24 mA1.5 V200 ps/pF110 ps/pF60 ps/pFN/AN/AN/A1.8 V150 ps/pFN/A60 ps/pF40 ps/pFN/AN/A2.5 V105 ps/pFN/A50 ps/pF25 ps/pF20 ps/pFN/A3.3-V PCI25 ps/pF25 ps/pF25 ps/pF25 ps/pF25 ps/pF25 ps/pFDifferential SSTL-2 Class I & II23 ps/pF23 ps/pF23 ps/pF23 ps/pF23 ps/pF23 ps/pFLVCMOS80 ps/pF50 ps/pF28 ps/pF20 ps/pFN/AN/ALVDS20 ps/pF20 ps/pF20 ps/pF20 ps/pF20 ps/pF20 ps/pFLVTTLN/A100 ps/pF70 ps/pF40 ps/pF30 ps/pF20 ps/pFSSTL-2 Class I & II23 ps/pF23 ps/pF23 ps/pF23 ps/pF23 ps/pF23 ps/pFSSTL-3 Class I & II25 ps/pF25 ps/pF25 ps/pF25 ps/pF25 ps/pF25 ps/pFThe following default tCO loads, per I/O standard, are available for Cyclone, Stratix, and Stratix GX devices:I/O StandardCyclone DevicesStratix DevicesStratix GX Devices1.5 V10 ps/pF10 ps/pF10 ps/pF1.5-V HSTL Class IN/A20 ps/pF20 ps/pF1.5-V HSTL Class IIN/A20 ps/pF20 ps/pF1.5-V PCMLN/AN/A4 ps/pF1.8 V10 ps/pF10 ps/pF10 ps/pF1.8-V HSTL Class I & IIN/A20 ps/pF20 ps/pF2.5 V10 ps/pF10 ps/pF10 ps/pF3.3-V PCI10 ps/pF10 ps/pF10 ps/pF3.3-V PCI-XN/A8 ps/pF8 ps/pF3.3-V PCMLN/A4 ps/pF4 ps/pFAGP 1xN/A10 ps/pF10 ps/pFAGP 2xN/A10 ps/pF10 ps/pFCompact PCIN/A10 ps/pF10 ps/pFCTTN/A30 ps/pF30 ps/pF1.5-V Differential HSTL Class IN/A20 ps/pF20 ps/pFDifferential SSTL-2 Class I & II30 ps/pF30 ps/pF30 ps/pFGTLN/A30 ps/pF for 2.5 V and 3.3 V30 ps/pF for 2.5 V and 3.3 VGTL+N/A30 ps/pF for 2.5 V and 3.3 V30 ps/pF for 2.5 V and 3.3 VHyperTransportN/A4 ps/pF4 ps/pFLVCMOS10 ps/pF10 ps/pF10 ps/pFLVDS4 ps/pF4 ps/pF4 ps/pFLVPECLN/A4 ps/pF4 ps/pFLVTTL10 ps/pF10 ps/pF10 ps/p