EDA程序改错题.doc

程序改错题1.已知sel为STD_LOGIC_VECTOR(1 DOWNTO 0)类型的信号，而a、b、c、d、q均为STD_LOGIC类型的信号，请判断下面给出的CASE语句程序片段：l CASE sel ISl WHEN“00”=qqqq=d；l END CASE；l 答案：CASE语句缺“WHEN OTHERS”语句。2. 已知data_in1, data_in2为STD_LOGIC_VECTOR(15 DOWNTO 0) 类型的输入端口，data_out为STD_LOGIC_VECTOR(15 DOWNTO 0)类型的输出端口，add_sub为STD_LOGIC类型的输入端口，请判断下面给出的程序片段：l LIBRARY IEEE；l USE IEEE.STD_LOGIC_1164.ALL；l ENTITY add ISl PORT（data_in1, data_in2：IN INTEGER；l data_out：OUT INTEGER）；l END add； l ARCHTECTURE add_arch OF add ISl CONSTANT a:INTEGER=2；l BEGINl data_out=( data_in1+ data_in2) * a；l END addsub_arch；答案：常量声明时赋初值的“=”符号应改用“:=”符号。3. 已知Q为STD_LOGIC类型的输出端口，请判断下面的程序片段：l ARCHITECTURE test_arch OF test ISl BEGINl SIGNAL B：STD_LOGIC；l QQQ Q Q = 0 ； END CASE ； END test ； 【参考答案】： CASE语句应该存在于进程PROCESS内。2 已知start为STD_LOGIC类型的信号，sum是INTEGER类型的信号，请判断下面的程序片断： PROCESS (start) BEGIN FOR i IN 1 TO 9 LOOP sum := sum + i ； END LOOP ； END PROCESS ； 【参考答案】： sum是信号，其赋值符号应该由“:=”改为“=”。3 已知Q为STD_LOGIC类型的输出端口，请判断下面的程序片断： ARCHITECTURE test OF test IS BEGIN SIGNAL B ：STD_LOGIC ； Q = B ； END test ； 【参考答案】： 信号SIGNAL的申明语句应该放在BEGIN语句之前。4 已知A和B均为STD_LOGIC类型的信号，请判断下面的语句： A = 0 ； B = x ； 【参考答案】： 不定态符号应该由小写的x改为大写的X。5 已知A为INTEGER类型的信号，B为STD_LOGIC类型的信号，请判断下面的程序片断： ARCHITECTURE test OF test IS BEGIN B q q q q = d ； END CASE ； 【参考答案】： CASE语句缺“WHEN OTHERS”语句。 四、判断下面程序中是否有错误，若有错误请改正；1、SIGNAL A,EN:STD_LOGIC;PROCESS(A,EN)VARIABLE B:STD_LOGIC;BEGIN IF EN=1 THEN B=A;END ;END PROCESS;2、 RCHITECTURE ONE OF SAMPLE ISVARIABLE A，B，C：INTEGER；BEGIN C=A+B；END ;五、判断下列程序是否有错误，如有则指出错误所在（10分）程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY zyt12 IS PORT(R,EN,CP: IN bit; Q: BUFFER STD_LOGIC_VECTOR(0 DOWNTO 3); CO: OUT STD_LOGIC);END zyt;ARCHITECTURE c10 OF zyt12 BEGIN CO=1 WHEN(EN=1 AND Q=1011) ELSE； 0; PROCESS(R,CP) BEGIN IF R=1 THEN Q=0000; ELSIF (CPEVENT AND CP=1) THEN IF EN=0 THEN Q=Q; ELSIF Q=1011 THEN Q=0000; ELSE Q:=Q+1; END IF; END PROCESS; END one;仔细阅读下列程序，回答问题LIBRARY IEEE;- 1USE IEEE.STD_LOGIC_1164.ALL;- 2ENTITY LED7SEG IS- 3PORT (A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);- 4CLK : IN STD_LOGIC;- 5LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);- 6END LED7SEG;- 7ARCHITECTURE one OF LED7SEG IS- 8SIGNAL TMP : STD_LOGIC;- 9BEGIN- 10SYNC : PROCESS(CLK, A)- 11BEGIN- 12IF CLKEVENT AND CLK = 1 THEN- 13TMP LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S = 00000001、LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4B ISPORT (CLK，RST，ENA: IN STD_LOGIC;OUTY : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);COUT : OUT STD_LOGIC );END CNT4B;ARCHITECTURE behav OF CNT4B ISSIGNAL CQI : STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK, RST, ENA)BEGINIF RST = 1 THEN CQI = 0000;0000ELSIF CLKEVENT AND CLK = 1 THENIF ENA = 1 THEN CQI = CQI + 1;1ELSE CQI = 0000;END IF;END IF;OUTY = CQI ;END PROCESS;COUT=CQI(0) AND CQI(1) AND CQI(2) AND CQI(3);END behav; 2、LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CLK_6D ISPORT (CLK,RST: IN STD_LOGIC; CLK_OUT: OUT STD_LOGIC);END CLK_6D;ARCHITECTURE ONE OF CLK_6D ISVARIABLE TEMP:STD_LOGIC; SIGNAL BEGIN PROCESS(CLK)VARIABLE CNT6D: INTEGER RANGE 0 TO 3;CONSTANT SIGN: INTEGER:=2; BEGINIF (RST = “1”) THEN TEMP = “0”; 1 , 0ELSIF CLKEVENT AND CLK=1 THEN (CLKEVENT AND CLK=1) IF (CNT6D = SIGN) THENCNT6D := 0;TEMP = NOT TEMP;ELSE CNT6D := CNT6D+1;END IF;END IF;END PROCESS;CLK_OUT yyyyyyyy null;end case;end process;end one;4、LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY counter ISPORT ( reset: IN STD_LOGIC;clock: IN STD_LOGIC;num: buffer integer range 0 to 3； 多一个“；” ); END;ARCHITECTURE behav OF jishu IS jishu改为 counter BeginProcess(reset,clock)BeginIf reset=1 thennum=0;Elsif rising_edge(clock) thenIf num=3 thennum=0;elsenum=num+1;少end if;end if;end process;end; 5、LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED;STD_LOGIC_UNSIGNED.ALLENTITY LX3_2 ISPORT(CLK,CLR,OE:IN BIT;D:IN STD_LOGIC_VECTOR(7 DOWNTO 0);Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END LX3_2;ARCHITECTURE struc OF LX3_2 ISVARIABLE Q_TEMP:STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNALBEGIN PROCESS(CLR) PROCESS(CLK) BEGIN IF CLR=0 THEN Q_TEMP=00000000;00000000ELSIF CLK=1 THENQ_TEMP=D;ELSE Q_TEMP=Q_TEMP;END IF;END PROCESS;Q=Q_TEMP WHEN OE=1 ELSEZZZZZZZZ;END struc; 6、LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY LX3_2 ISPORT( A :IN STD_LOGIC_VECT