乘法器.doc

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;entity cnt20 is port(stop,start,reset,clk:in std_logic; q:out std_logic_vector(7 downto 0); yellow,green,red:out std_logic);end cnt20;architecture behavioral of cnt20 issignal cao_v:std_logic_vector(1 downto 0);beginprocess(stop,reset,clk)variable tmp1:integer;variable tmp2:integer;variable ca:integer;beginif reset=1 then tmp1:=0; tmp2:=1; ca:=0;elsif(clkevent and clk=1)then if(stop=0)then if(start=1)then if(tmp1=0)then if(tmp2=0)then ca:=1; else tmp2:=tmp2-1; tmp1:=9; end if; else tmp1:=tmp1-1; end if; end if; end if;end if;cao_v=conv_std_logic_vector(ca,2);yellow=cao_v(0);q(7 downto 4)=conv_std_logic_vector(tmp2,4);q(3 downto 0)=conv_std_logic_vector(tmp1,4);end process;green=stop and start;red=stop and (not start);end behavioral;library ieee;use ieee.std_logic_1164.all;entity first is port(reset:in std_logic; a:in std_logic_vector(3 downto 0); lockout:out std_logic; firstman:out std_logic_vector(2 downto 0);end first;architecture behavioral of first issignal clk,lock:std_logic;signal c:std_logic_vector(3 downto 0);beginclk=1when a(3)=1 or a(2)=1 or a(1)=1 else 0;lockout=lock;process_label:process(clk)beginif reset=1then c=0000; lock=0;elsif clk=1 then if lock=0 then c=a; lock=1; end if;end if;end process process_label;firstman=001 when c=1000 else 010 when c=