武汉理工大学EDA考试大全.doc

1、八进制计数器的VHDL设计library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity counter8 is port(clk:in std_logic; counter:out std_logic_vector(2 downto 0);end entity counter8;architecture bhv of counter8 is signal counter1:std_logic_vector(2 downto 0); begin process (clk) begin if clkevent and clk=1 then if counter1=111 then counter1=000; else counter1=counter1 +1; end if; end if; end process; countersegoutsegoutsegoutsegoutsegoutsegoutsegoutsegoutsegoutsegoutsegoutsegoutsegoutsegoutsegoutsegoutsegout=00000000; end case; end process;end architecture bhv;3、分频library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity fenpin is generic(N:integer); port(clk:in std_logic; q:buffer std_logic);end entity fenpin;architecture bhv of fenpin is begin process (clk) variable a1:integer:=N-1 ; begin if rising_edge(clk) then if a1=N-1 then a1 :=0;q32000) port map(clk,clk1); M2 :counter8 port map(clk1,counter); M3 :decl7s port map(bcdin,segout); end bhv; 2 实验中数码管上将轮流产生0-F，间隔时间为1s的顶层文件。library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity shumaguan is port (clk:in std_logic; bcdin:buffer std_logic_vector(3 downto 0); segout:out std_logic_vector(7 downto 0); counter:out std_logic_vector(2 downto 0) );end shumaguan;architecture bhv of shumaguan is component fenpin generic(N:integer); port(clk:in std_logic; q:buffer std_logic); end component ; component decl7s port(bcdin:in std_logic_vector(3 downto 0); segout:out std_logic_vector(7 downto 0) ); end component ; component counter8 port(clk:in std_logic; counter:out std_logic_vector(2 downto 0) ); end component ; signal clk1: std_logic; signal clk2: std_logic; begin M1 :fenpin generic map(N=32000) port map(clk,clk1); M2 :fenpin generic map(N=20000000) port map(clk,clk2); M3 :counter8 port map(clk1,counter); M4 :decl7s port map(bcdin,segout); process(clk,clk2) begin if rising_