双通路信号源发生器设计程序.doc

*管脚定义（config.h）*#define DATAP1sbit RS=P3.2;sbit RW=P3.1;sbit En =P3.0;sbit BUSY= DATA7;sbit key_5=P3.7;sbit key_4=P3.6;sbit key_3=P3.5;sbit key_2=P3.4;sbit key_1=P3.3;sbit F_Ph=P2.0;#define EDA_DATAP0sbit EDA_E = P2.5;sbit EDA_E0 = P2.6;sbit EDA_E1 = P2.7;*主程序（main.c）*#include#includestdlib.h#includeconfig.h#includefun.h#includekey_fun.hbit key_en;unsigned int hz=50000;unsigned short int phase=0;char *hs=Fr:,*ps=Ph:;char Hzs=00000,Phs=000,*h,*pha;void send_EDA_data(bit a,bit b,int dat)EDA_E0=a;EDA_E1=b;EDA_DATA=dat;EDA_E=1;EDA_E=0;bit key_fun()bit z=0;if(key_5=0&key_4=1&key_3=1&key_2=1&key_1=1&F_Ph=1&key_en=0)key_en=1;hz=hz-10000;if(hz50000)hz=50000;z=0;if(key_5=1&key_4=0&key_3=1&key_2=1&key_1=1&F_Ph=1&key_en=0)key_en=1;hz=hz-1000;if(hz50000)hz=50000;z=0;if(key_5=1&key_4=1&key_3=0&key_2=1&key_1=1&F_Ph=1&key_en=0)key_en=1;hz=hz-100;if(hz50000)hz=50000;z=0;if(key_5=1&key_4=1&key_3=1&key_2=0&key_1=1&F_Ph=1&key_en=0)key_en=1;hz=hz-10;if(hz50000)hz=50000;z=0;if(key_5=1&key_4=1&key_3=1&key_2=1&key_1=0&F_Ph=1&key_en=0)key_en=1;hz=hz-1;if(hz50000)hz=50000;z=0;if(key_5=1&key_4=1&key_3=1&key_2=0&key_1=1&F_Ph=0&key_en=0)key_en=1;phase=phase+9;if(phase=72)phase=0;z=0;if(key_5=1&key_4=1&key_3=1&key_2=1&key_1=0&F_Ph=0&key_en=0)key_en=1;phase=phase+1;if(phase=72)phase=0;z=0;if(key_5=1&key_4=1&key_3=1&key_2=1&key_1=1&key_en=1)key_en=0;z=1;return z;void main()h=&Hzs0;pha=&Phs0;EDA_E=0;loop:lcd_init();wr_com(0x80);conv_tostring(50000-hz,h);conv_tostring1(phase*5,pha);lcd_string(hs);lcd_string(h);wr_data(0);wr_data(H);wr_data(z);wr_com(0xc0);lcd_string(ps);lcd_string(pha);send_EDA_data(1,1,phase);send_EDA_data(0,1,hz/256);send_EDA_data(1,0,hz%256);send_EDA_data(0,0,0);while(1)if(key_fun()goto loop;*液晶显示LCD1602的读写子程序（fun.h）*void rd_b()DATA = 0XFF;RS = 0;RW = 1;while(BUSY=1)En = 0;En = 1;En = 0;void wr_com(char a)rd_b();RS = 0;RW = 0;DATA = a;En = 1;En = 0;void wr_data(char a)rd_b();RS = 1;RW = 0;DATA = a;En = 1;En = 0;void lcd_init()wr_com(0x38);wr_com(0x0f);wr_com(0x06);wr_com(0X01);void lcd_string(char *p)while(1)if(*p=0)break;wr_data(*p);p+;*整型转字符串的子程序（stdlib.h）*char numc=48,49,50,51,52,53,54,55,56,57;int nbit=1,1,10,100,1000,10000;void conv_tostring(unsigned int n,char *p)short maxbit=5;for(;maxbit0;maxbit-)*(p+maxbit-1)=0;if(n9999)maxbit=5;else if(n999)maxbit=4;else if(n99)maxbit=3;else if(n9)maxbit=2;else maxbit=1;for(;maxbit0;maxbit-)*(p+5-maxbit)=numcn/nbitmaxbit;n=n%nbitmaxbit;void conv_tostring1(unsigned short int n,char *p)short maxbit=3;for(;maxbit0;maxbit-)*(p+maxbit-1)=0;if(n99)maxbit=3;else if(n9)maxbit=2;else maxbit=1;for(;maxbit0;maxbit-)*(p+3-maxbit)=numcn/nbitmaxbit;n=n%nbitmaxbit;1 EDA程序-*地址选择（selec_addr.vhd）*library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity selec isport(e0:in std_logic;e1_2:in std_logic_vector(1 downto 0);data:in std_logic_vector(7 downto 0);clk:in std_logic;out_addr1,out_addr2:out integer range 0 to 360);end selec;architecture behav of selec issignal tar:std_logic_vector(15 downto 0);signal ph:integer range 0 to 255;begin process(clk)variable sum:integer range 0 to 100000;variable addr1_m,addr2_m:integer range 0 to 360;beginif clk=1 thensum:=conv_integer(sum+tar);if sum50000 thenaddr1_m:=addr1_m+1;if addr1_m=360 thenaddr1_m:=0;end if;addr2_m:=addr1_m+5*ph;else sum:=sum-50000; end if; end if; out_addr1=addr1_m; out_addr2tar(15 downto 8)tar(7 downto 0)ph null;end case;end if;end process; end behav;-*ROM(rom_data.vhd)*library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity rom isport( addr1,addr2:in integer range 0 to 360; data1,data2:out std_logic_vector(7 downto 0);end rom;architecture behav of rom istype mem_block is array(0 to 360) of std_logic_vector(7 downto 0);constant rom_data:mem_block:=(x80,x82,x84,x86,x88,x8b,x8d,x8f,x91,x93,x96,x98,x9a,x9c,x9e,xa0,xa3,xa5,xa7,xa9,xab,xad,xaf,xb1,xb3,xb5,xb7,xb9,xbb,xbd,xbf,xc1,xc3,xc5,xc7,xc9,xca,xcc,xce,xd0,xd1,xd3,xd5,xd6,xd8,xda,xdb,xdd,xde,xe0,xe1,xe3,xe4,xe5,xe7,xe8,xe9,xea,xec,xed,xee,xef,xf0,xf1,xf2,xf3,xf4,xf5,xf6,xf7,xf7,xf8,xf9,xf9,xfa,xfb,xfb,xfc,xfc,xfd,xfd,xfd,xfe,xfe,xfe,xff,xff,xff,xff,xff,xff,xff,xff,xff,xff,xff,xfe,xfe,xfe,xfd,xfd,xfd,xfc,xfc,xfb,xfb,xfa,xf9,xf9,xf8,xf7,xf7,xf6,xf5,xf4,xf3,xf2,xf1,xf0,xef,xee,xed,xec,xea,xe9,xe8,xe7,xe5,xe4,xe3,xe1,xe0,xde,xdd,xdb,xda,xd8,xd6,xd5,xd3,xd1,xd0,xce,xcc,xca,xc9,xc7,xc5,xc3,xc1,xbf,xbd,xbb,xb9,xb7,xb5,xb3,xb1,xaf,xad,xab,xa9,xa7,xa5,xa3,xa0,x9e,x9c,x9a,x98,x96,x93,x91,x8f,x8d,x8b,x88,x86,x84,x82,x80,x7d,x7b,x79,x77,x74,x72,x70,x6e,x6c,x69,x67,x65,x63,x61,x5f,x5c,x5a,x58,x56,x54,x52,x50,x4e,x4c,x4a,x48,x46,x44,x42,x40,x3e,x3c,x3a,x38,x36,x35,x33,x31,x2f,x2e,x2c,x2a,x29,x27,x25,x24,x22,x21,x1f,x1e,x1c,x1b,x1a,x18,x17,x16,x15,x13,x12,x11,x10,x0f,x0e,x0d,x0c,x0b,x0a,x09,x08,x08,x07,x06,x06,x05,x04,x04,x03,x03,x02,x02,x02,x01,x01,x01,x00,x00,x00,x00,x00,x00,x00,x00,x00,x00,x00,x01,x01,x01,x02,x02,x02,x03,x03,x04,x04,x05,x06,x06,x07,x08,x08,x09,x0a,x0b,x0c,x0d,x0e,x0f,x10,x11,x12,x13,x15,x16,x17,x18,x1a,x1b,x1c,x1e,x1f,x21,x22,x24,x25,x27,x29,x2a,x2c,x2e,x2f,x31,x33,x35,x36,x38,x3a,x3c,x3e,x40,x42,x44,x46,x48,x4a,x4c,x4e,x50,x52,x54,x56,x58,x5a,x5c,x5f,x61,x63,x65,x67,x69,x6c,x6e,x70,x72,x74,x77,x79,x7b,x7d,x7f);begindata1=rom_data(addr1); data2=rom_data(addr2); end behav;-*(altp110.vhd)*LIBRARY ieee;USE ieee.std_logic_1164.all;LIBRARY altera_mf;USE altera_mf.all;ENTITY altpll0 ISPORT(inclk0: IN STD_LOGIC := 0;c0: OUT STD_LOGIC );END altpll0;ARCHITECTURE SYN OF altpll0 ISSIGNAL sub_wire0: STD_LOGIC_VECTOR (5 DOWNTO 0);SIGNAL sub_wire1: STD_LOGIC ;SIGNAL sub_wire2: STD_LOGIC ;SIGNAL sub_wire3: STD_LOGIC_VECTOR (1 DOWNTO 0);SIGNAL sub_wire4_bv: BIT_VECTOR (0 DOWNTO 0);SIGNAL sub_wire4: STD_LOGIC_VECTOR (0 DOWNTO 0);COMPONENT altpllGENERIC (clk0_divide_by: NATURAL;clk0_duty_cycle: NATURAL;clk0_multiply_by: NATURAL;clk0_phase_shift: STRING;compensate_clock: STRING;inclk0_input_frequency: NATURAL;intended_device_family: STRING;lpm_type: STRING;operation_mode: STRING;port_activeclock: STRING;port_areset: STRING;port_clkbad0: STRING;port_clkbad1: STRING;port_clkloss: STRING;port_clkswitch: STRING;port_configupdate: STRING;port_fbin: STRING;port_inclk0: STRING;port_inclk1: STRING;port_locked: STRING;port_pfdena: STRING;port_phasecounterselect: STRING;port_phasedone: STRING;port_phasestep: STRING;port_phaseupdown: STRING;port_pllena: STRING;port_scanaclr: STRING;port_scanclk: STRING;port_scanclkena: STRING;port_scandata: STRING;port_scandataout: STRING;port_scandone: STRING;port_scanread: STRING;port_scanwrite: STRING;port_clk0: STRING;port_clk1: STRING;port_clk2: STRING;port_clk3: STRING;port_clk4: STRING;port_clk5: STRING;port_clkena0: STRING;port_clkena1: STRING;port_clkena2: STRING;port_clkena3: STRING;port_clkena4: STRING;port_clkena5: STRING;port_extclk0: STRING;port_extclk1: STRING;port_extclk2: STRING;port_extclk3: STRING);PORT (inclk: IN STD_LOGIC_VECTOR (1 DOWNTO 0);clk: OUT STD_LOGIC_VECTOR (5 DOWNTO 0);END COMPONENT;BEGINsub_wire4_bv(0 DOWNTO 0) = 0;sub_wire4 = To_stdlogicvector(sub_wire4_bv);sub_wire1 = sub_wire0(0);c0 = sub_wire1;sub_wire2 = inclk0;sub_wire3 1,clk0_duty_cycle = 50,clk0_multiply_by = 9,clk0_phase_shift = 0,compensate_clock = CLK0,inclk0_input_frequency = 50000,intended_device_family = Cyclone II,lpm_type = altpll,operation_mode = NORMAL,port_activeclock = PORT_UNUSED,port_areset = PORT_UNUSED,port_clkbad0 = PORT_UNUSED,port_clkbad1 = PORT_UNUSED,port_clkloss = PORT_UNUSED,port_clkswitch = PORT_UNUSED,port_configupdate = PORT_UNUSED,port_fbin = PORT_UNUSED,port_inclk0 = PORT_USED,port_inclk1 = PORT_UNUSED,port_locked = PORT_UNUSED,port_pfdena = PORT_UNUSED,port