一个基于C8051F120的SPWM输出C程序.docx

/*2010年12月13日17:27:48* 内部系统时钟98M * 测试： CEX0中断用于输出所需SPWM波形，CEX2中断用于计算CEX0翻转值最小脉宽0.63us 左右*/-/ Includes/-#include / SFR declarations/-/ Global Constants/-#define uchar unsigned char#define uint unsigned short int#define N 0X4096#define T 0x1324 /0.05*98*103 载波周期 T=50ussbit SPWM_H=P00;/SPWM_H用于高低电平判断uint count2=0,s0=0,s2=0,cpl2=0,cph2=0,cpl1=0,cph1=0,cpl0=0,cph0=0;/查表值/测试值 高电平 0.1 0.2 0.4 0.6 0.8 0.8 0.6 0.4 0.2 0.1 /uint s_code_num=10,s_code=0,0xd7,0x1ea,0x3d4,0x50a,0x7a8,0x7a8,0x50a,0x3d4,0x1ae,0xd7;/测试值 1usuint s_code_num=10,s_code=0X00,0x62,0x62,0x62,0x62,0x62,0x62,0x62,0x62,0x62,0x62,0x62;/测试值 0.62us OK/uint s_code_num=9,s_code=0X3D,0X3D,0X3D,0X3D,0X3D,0X3D,0X3D,0X3D,0X3D,0X3D,0X3D;/测试值 0.05us 无法通过/uint s_code_num=9,s_code=0X31,0X31,0X31,0X31,0X31,0X31,0X31,0X31,0X31,0X31,0X31,;/-/ Function Prototypes/-void OSCILLATOR_Init (void);void PORT_Init (void);void PCA0_Init (void);void pca_isr(void);/-/ main() Routine/-void main (void) / Disable watchdog timer WDTCN = 0xde; WDTCN = 0xad; EIP1|=0x08; /设置为高优先级 EIE1=0x08; /PAC中断允许 /EIE1=0x10; /由于软件原因，软件仿真的时候EIE1需改为0X10! EA=1; PORT_Init (); / Initialize crossbar and GPIO OSCILLATOR_Init (); / Initialize oscillator PCA0_Init (); / Initialize PCA0 SFRPAGE = PCA0_PAGE; / Change to PCA0 page while (1) if(count2=s_code_num) count2=0; P0=0X00; s0=0X00; s2=0X00; PCA0L=0X00; PCA0H=0X00; /每个周期结束，必须清零PCA0计时器， CCF2=1; /-/ OSCILLATOR_Init/-void OSCILLATOR_Init (void) int loop; / Software timer char SFRPAGE_save = SFRPAGE; / Save Current SFR page SFRPAGE = CONFIG_PAGE; / Set SFR page OSCICN = 0x83; / Set internal oscillator to run / at its maximum frequency CLKSEL = 0x00; / Select the internal osc. as / the SYSCLK source /Turn on the PLL and increase the system clock by a factor of M/N = 2 SFRPAGE = CONFIG_PAGE; PLL0CN = 0x00; / Set internal osc. as PLL source SFRPAGE = LEGACY_PAGE; FLSCL = 0x10; / Set FLASH read time for 98MHz clk / or less SFRPAGE = CONFIG_PAGE; PLL0CN |= 0x01; / Enable Power to PLL PLL0DIV = 0x01; / Set Pre-divide value to N (N = 1) PLL0FLT = 0x01; / Set the PLL filter register for / a reference clock from 19 - 30 MHz / and an output clock from 45 - 80 MHz PLL0MUL = 0x04; / Multiply SYSCLK by M (M = 4) for (loop=0; loop 8; cpl2