EDA(Veriolg)代码.doc

硬件知识：有位选和段选才能找到你要让他亮的数码管就像坐标有横坐标和纵坐标。16x16点阵1.数码管显示0fmodule count16(clk,y1,y2);input clk;output7:0 y2;output 7:0 y1;reg 7:0 y1;reg 3:0 en;reg 7:0 y2;always(posedge clk)beginen=en+1b1;case(en)4b0000: begin y1=8b00111111;y2=8b00001000;end4b0001: begin y1=8b00000110;y2=8b00001000;end4b0010: begin y1=8b01011011;y2=8b00001000;end4b0011: begin y1=8b01001111;y2=8b00001000;end4b0100: begin y1=8b01100110;y2=8b00001000;end4b0101: begin y1=8b01101101;y2=8b00001000;end4b0110: begin y1=8b01111101;y2=8b00001000;end4b0111: begin y1=8b00000111;y2=8b00001000;end4b1000: begin y1=8b01111111;y2=8b00001000;end4b1001: begin y1=8b01101111;y2=8b00001000;end4b1010: begin y1=8b01110111;y2=8b00001000;end4b1011: begin y1=8b01111100;y2=8b00001000;end4b1100: begin y1=8b00111001;y2=8b00001000;end4b1101: begin y1=8b01011110;y2=8b00001000;end4b1110: begin y1=8b01111001;y2=8b00001000;end4b1111: begin y1=8b01110001;y2=8b00001000;end endcase endendmodule2.数码管显示学号module xxx(seg,sl,clk); output 7:0 seg; output7:0 sl; input clk; reg 7:0 seg_reg;reg 7:0 sl_reg; reg 3:0 disp_dat; reg 2:0 count; always(posedge clk) begin count=count+1b1; endalways(posedge clk) begin case(count) 3b000:disp_dat=4b0001; /显示个位数为1 3b001:disp_dat=4b0000; /显示十位数为0 3b010:disp_dat=4b0010; /显示百位数为2 3b011:disp_dat=4b0000; /显示千位数为0 3b100:disp_dat=4b0001;/1 3b101:disp_dat=4b0000;/0 3b110:disp_dat=4b0110;/6 3b111:disp_dat=4b0000;/0 endcase case(count) /选择数鹿芟允疚? 3b111:sl_reg=8b00000001; /选择个位数码管 3b110:sl_reg=8b00000010; /选择十位数码管 3b101:sl_reg=8b00000100; /选择百位数码管 3b100:sl_reg=8b00001000; /选择千位数码管 3b011:sl_reg=8b00010000; 3b010:sl_reg=8b00100000; 3b001:sl_reg=8b01000000; 3b000:sl_reg=8b10000000; endcase endalways(disp_dat) /显示译码输出 begin case(disp_dat) /选择输出数据 4b0000:seg_reg=8b00111111; /显示0 4b0001:seg_reg=8b00000110; /显示1 4b0010:seg_reg=8b01011011; /显示2 4b0011:seg_reg=8b01001111; /显示3 4b0100:seg_reg=8b01100110; /显示4 4b0101:seg_reg=8b01101101; /显示5 4b0110:seg_reg=8b01111101; /显示6 endcaseend assign seg=seg_reg; assign sl=sl_reg; endmodule3.100进制099module xxx(clk,wela,dula);input clk;output 7:0wela;reg 7:0wela;output 7:0dula;reg 7:0dula;reg 3:0count;reg a;reg 3:0 i;reg 3:0 j;reg 7:0 RAM0:9;always(posedge clk)beginRAM0=8H3F;RAM1=8H06;RAM2=8H5B;RAM3=8H4F;RAM4=8H66;RAM5=8H6D;RAM6=8H7D;RAM7=8H07;RAM8=8H7F;RAM9=8H6F; endalways(posedge clk)begincount=count+4b0001;a=a+1;if(count=4b1001)begin i=i+1; if(i=10) begin j=j+1; i=0; a=1; if(j=10) begin j=0; a=1; end end end endalways (a)case(a)0:begin wela=8H02;dula=RAMi;end1:begin wela=8H01;dula=RAMj;endendcaseendmodule4.用点阵显示姓名module xx(hang,lie,clk); output 15:0hang ; output3:0 lie; input clk; reg 15:0 hang;reg 3:0 lie; reg 3:0 count;reg 15:0 dis;reg 1:0a; always(posedge clk) begincount=count+4b0001;if(count=4b1111)count=4b0000;dis=dis+1;if(dis=0)a=a+2b01;if(a=2b11)a=0;end always( a or count) case(a)2b00: /表示选显那一个字 case(count)4b0000:begin lie=4b0000;hang=16h0000;end/字的点阵代码（可以下一个软件自己生成）4b0001:begin lie=4b0001;hang=16h4f80;end4b0010:begin lie=4b0010;hang=16h4882;end4b0011:begin lie=4b0011;hang=16h4881;end4b0100:begin lie=4b0100;hang=16h78fe;end4b0101:begin lie=4b0101;hang=16h0000;end4b0110:begin lie=4b0110;hang=16h03e1;end4b0111:begin lie=4b0111;hang=16h7a21;end4b1000:begin lie=4b1000;hang=16h4a21;end4b1001:begin lie=4b1001;hang=16h4fff;end4b1010:begin lie=4b1010;hang=16h4a22;end4b1011:begin lie=4b1011;hang=16h4a22;end4b1100:begin lie=4b1100;hang=16h7a2a;end4b1101:begin lie=4b1101;hang=16h03e7;end4b1110:begin lie=4b1110;hang=16h0002;end4b1111:begin lie=4b1111;hang=16h0000;end endcase2b10: case(count)4b0000:begin lie=4b0000;hang=16h0000;end4b0001:begin lie=4b0001;hang=16h7fc0;end4b0010:begin lie=4b0010;hang=16h4440;end4b0011:begin lie=4b0011;hang=16h4440;end4b0100:begin lie=4b0100;hang=16h4440;end4b0101:begin lie=4b0101;hang=16h7fc2;end4b0110:begin lie=4b0110;hang=16h0004;end4b0111:begin lie=4b0111;hang=16h0018;end4b1000:begin lie=4b1000;hang=16hffe0;end4b1001:begin lie=4b1001;hang=16h8880;end4b1010:begin lie=4b1010;hang=16h8880;end4b1011:begin lie=4b1011;hang=16h8882;end4b1100:begin lie=4b1100;hang=16h8881;end4b1101:begin lie=4b1101;hang=16hfffe;end4b1110:begin lie=4b1110;hang=16h0000;end4b1111:begin lie=4b1111;hang=16h0000;endendcase 2b01:case(count)4b0000:begin lie=4b0000;hang=16h0000;end4b0001:begin lie=4b0001;hang=16h8001;end4b0010:begin lie=4b0010;hang=16h8005;end4b0011:begin lie=4b0011;hang=16hbf89;end4b0100:begin lie=4b0100;hang=16haaf2;end4b0101:begin lie=4b0101;hang=16haaaa;end4b0110:begin lie=4b0110;hang=16heaaa;end4b0111:begin lie=4b0111;hang=16haaaa;end4b1000:begin lie=4b1000;hang=16haaa4;end4b1001:begin lie=4b1001;hang=16haaaa;end4b1010:begin lie=4b1010;hang=16haab2;end4b1011:begin lie=4b1011;hang=16hbfa2;end4b1100:begin lie=4b1100;hang=16h8001;end4b1101:begin lie=4b1101;hang=16h8001;end4b1110:begin lie=4b1110;hang=16h0000;end4b1111:begin lie=4b1111;hang=16h0000;endendcase endcaseendmodule5.可调时钟（时为加，分加）module mmm(clk,bitcase,stop,k1,k2,seg);input clk,k1,k2;input stop;output 7:0seg;output 7:0bitcase;reg 7:0seg;reg 7:0bitcase;reg 2:0a;reg 2:0t;reg 8:0b;reg 3:0s1;reg 3:0s2;reg 3:0m3;reg 3:0m4;reg 3:0h5;reg 3:0h6;reg 7:0NUM0:9;always beginNUM0=8b00111111;NUM1=8b00000110;NUM2=8b01011011;NUM3=8b01001111;NUM4=8b01100110;NUM5=8b01101101;NUM6=8b01111101;NUM7=8b00000111;NUM8=8b01111111;NUM9=8b01101111;endalways (posedge clk)begin b=b+8h01; a=a+1;if(b=0)beginif(stop=1)begins1=s1+4b0001;if(s1=4b1010)begins1=4b0000;s2=s2+4b0001;endif(s2=4b0110)begins2=4b0000;m3=m3+4b0001;endif(m3=4b1010)beginm3=4b0000;m4=m4+4b0001;end if(m4=4b0110) begin m4=4b0000; h5=h5+4b0001; endif(h5=4b1010)beginh5=4b0000;h6=h6+4b0001;end if(h6=4b0010&h5=4b0100)begin h6=4b0000; h5=4b0000; end end else if(k1=0) begin m3=m3+4b0001; if(m3=4b1010) begi