EDA电子设计自动化-电子钟.doc

电子设计自动化EDA课程设计题目 电 子 钟 设 计 专业 电子工程系 班级 学号 姓名 二一一年十二月二十三日目录1、设计要求11.1基本功能要求：11.2扩展功能要求：12、总体设计方案13数字钟的基本组成14、功能说明：25、RTL门级网表：26、PIN截图：67、源程序代码：67.1顶层例化：67.2时钟模块：97.2.1时钟顶层：97.2.2、60进制计数器（分钟，秒模块）：107.2.3、24进制计数器（小时模块）：107.3、闹钟模块117.4、跑表模块：127.4.1、跑表顶层：127.4.2、跑表60进制计数器：137.4.3、跑表100进制计数器：147.5、LED信号选择模块（MUX31A）：157.6、数码管扫描模块：167.7、分频模块：187.8、按键指向选择模块：197.9、调整选择模块：208、收获与体会219、明细清单2110、参考文献2111、附图221、设计要求1.1基本功能要求：设计一个电子时钟，要求可以显示时、分、秒，用户可以设置时间。1.2扩展功能要求：秒表功能，闹钟功能，调整数码管的亮度。2、总体设计方案本数字系统实现数字钟的基本的计时功能，输入10MHz的时钟，通过分频产生1Hz的时钟信号，采用24小时制计时，能显示时、分、秒。本系统还具有校正功能，可以进行时分的校时，另外还可以设定闹钟，秒表和调节数码管亮度的功能。 3数字钟的基本组成本数字钟的实现可分为以下几个模块：1、 秒、分计数模块：秒计数，在频率为1Hz的时钟下以60次为循环计数，并产生进位信号影响分计数。2、 时计数模块：时计数，在分进位信号为高电平时，计数一次，以24次为一个循环计数。3、 毫秒计数模块：时计数，在分进位信号为高电平时，计数一次，以100次为一个循环计数。4、 频率产生模块：产生1Hz,100Hz的计数频率 和10000Hz的扫描频率。5、 显示模块：数码管通过动态显示，同时进行一定频率的扫描显示时，分，秒，并且通过调节扫描占空比调节数码管亮度。7、 闹钟模块：在设定闹钟闹铃时间后，可在闹铃时间闹铃。8、 跑表模块：将毫秒计数模块与秒计数模块进行例化。9、 调整选择模块：在特定的状态下对输入的按键信号进行选择，使调整信号分别传输到时间、闹钟调整端和秒表使能和复位端。10、显示选择模块：将时钟、跑表、闹钟的输出信号在特定的状态下分别输出，并且可以输出本模块内定的显示代码。4、功能说明：本电子钟采用三个物理按键操作。键1：模式转换键按下键1，数码管依次显示时钟信号闹钟信号跑表。（跑表分钟位采用100进制。）如图： 图1、模式转换示意图键4：调整模式转换键在时间模式按下键4，依次可以调整时间的分钟、小时，闹钟的分钟、小时，亮度。在跑表模式下，为跑表的复位键。 图2、调整模式转换图键8：时钟和亮度模式调整按键，跑表模式的开始与暂停键。5、RTL门级网表：图3、总体RTL门级网表_PART 1图4、总体RTL门级网表_PART2图6、跑表模块RTL门级网表图5、时钟模块RTL门级网表6、PIN截图：图7、引脚锁定7、源程序代码：7.1顶层例化：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CLOCK_TOP IS PORT(CLK_10M,KEY1,KEY4,KEY8:IN STD_LOGIC; CLOCK_DK: OUT STD_LOGIC_VECTOR(6 DOWNTO 0); CLOCK_WK: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); SPEAKER:OUT STD_LOGIC);END ENTITY;ARCHITECTURE ONE OF CLOCK_TOP ISCOMPONENT FENPIN 图8、总体例化结构 PORT (CLK : IN STD_LOGIC;CLK_10000 : OUT STD_LOGIC;CLK_100 : OUT STD_LOGIC;CLK_1 : OUT STD_LOGIC);END COMPONENT;COMPONENT CLOCK PORT(CLK_1:IN STD_LOGIC;-电子钟的时钟信号； SET_H,SET_M:IN STD_LOGIC;-电子钟的小时与分钟设置； SET_EN:IN STD_LOGIC; -电子钟的调节使能 CLOCK_H:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);-电子钟的小时输出； CLOCK_M:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);-电子钟的分钟输出； CLOCK_S:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);-电子钟的秒输出：END COMPONENT;COMPONENT ALARM 闹钟模块 PORT(CLK,SET_M,SET_H: IN STD_LOGIC; CLOCK_H, CLOCK_M:IN STD_LOGIC_VECTOR(7 DOWNTO 0);时间信号输入 ALARM_H ,ALARM_M:INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);闹钟时间信号输出 SPK_OUT:OUT STD_LOGIC);END COMPONENT;COMPONENT STOP_W -跑表模块 PORT(CLK_W,EN_W,RST_W:IN STD_LOGIC;-CLK_W接100HZ STOP_MS:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);-跑表的输出端 STOP_S :OUT STD_LOGIC_VECTOR(7 DOWNTO 0); STOP_M :OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END COMPONENT;COMPONENT MUX21A 按键分配PORT(STATE_IN:INTEGER RANGE 0 TO 2;-接从MUX31A的状态信号 KEY_4,KEY_8:IN STD_LOGIC; ADJUST_OUT,SELECT_OUT:OUT STD_LOGIC;-调整端输出 EN_OUT,RST_OUT:OUT STD_LOGIC);-跑表使能，复位END COMPONENT;COMPONENT MUX31A -显示选择 PORT(CLK:IN STD_LOGIC; L: IN INTEGER RANGE 0 TO 5;-接从ADJUST_EN的状态信号SET_EN:OUT STD_LOGIC;-时间调整使能，用于在调时时锁定低级进位信号 STATE_OUT: OUT INTEGER RANGE 0 TO 2;-显示状态反馈端 CLOCK_H,CLOCK_M,CLOCK_S:IN STD_LOGIC_VECTOR(7 DOWNTO 0);-各显示信号输入端 ALARM_H,ALARM_M:IN STD_LOGIC_VECTOR(7 DOWNTO 0); SPORT_M,SPORT_S,SPORT_MS:IN STD_LOGIC_VECTOR(7 DOWNTO 0); OUT_H,OUT_M,OUT_L:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);-显示输出END COMPONENT;COMPONENT ADJUST_EN PORT(EN_SELECT,ADJUST:IN STD_LOGIC;CLOCK_M,CLOCK_H,ALARM_M,ALARM_H,L:OUT STD_LOGIC;COMB_OUT:OUT INTEGER RANGE 0 TO 5);END COMPONENT;COMPONENT SCAN_LED PORT( CLK,SET_L:IN STD_LOGIC; H_IN,M_IN,L_IN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);-高位，低位，中位显示信号 SG:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);-段控制信号 BT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);-位控制信号?END COMPONENT;SIGNAL MUX21A_A,MUX21A_E,EN_S,RST_S,SPORT_CLK,CLOCK_CLK,ALARM_CLK,H_1,M_1,H_2,M_2,L_SET,SET:STD_LOGIC;SIGNAL M3_M2:INTEGER RANGE 0 TO 2;SIGNAL M3_ADJUST:INTEGER RANGE 0 TO 5;SIGNAL CH_S,CM_S,CS_S,AH_S,AM_S,SM,SS,SMS,H_H,M_M,L_L :STD_LOGIC_VECTOR(7 DOWNTO 0);BEGINU1:FENPIN PORT MAP(CLK=CLK_10M,CLK_10000=ALARM_CLK,CLK_100=SPORT_CLK,CLK_1=CLOCK_CLK);U2:MUX21A PORT MAP(KEY_8=KEY8,KEY_4=KEY4,STATE_IN=M3_M2,ADJUST_OUT=MUX21A_A,SELECT_OUT=MUX21A_E,EN_OUT=EN_S,RST_OUT=RST_S);U3:ADJUST_EN PORT MAP (ADJUST=MUX21A_A,EN_SELECT=MUX21A_E,COMB_OUT=M3_ADJUST,CLOCK_H=H_1,CLOCK_M=M_1,ALARM_H=H_2,ALARM_M=M_2,L=L_SET);U4:CLOCK PORT MAP(CLK_1=CLOCK_CLK,SET_EN=SET,SET_H=H_1,SET_M=M_1,CLOCK_H=CH_S,CLOCK_M=CM_S,CLOCK_S=CS_S);U5:ALARM PORT MAP(CLK=ALARM_CLK,SET_H=H_2,SET_M=M_2,CLOCK_H=CH_S,CLOCK_M=CM_S,ALARM_H=AH_S,ALARM_M=AM_S,SPK_OUT=SPEAKER);U6:STOP_W PORT MAP(CLK_W=SPORT_CLK,EN_W=EN_S,RST_W=RST_S,STOP_MS=SMS,STOP_S=SS,STOP_M=SM);U7:MUX31A PORT MAP(CLK=KEY1,SET_EN=SET,L=M3_ADJUST,CLOCK_H=CH_S,CLOCK_M=CM_S,CLOCK_S=CS_S,ALARM_H=AH_S,ALARM_M=AM_S,SPORT_M=SM,SPORT_S=SS,SPORT_MS=SMS,STATE_OUT=M3_M2,OUT_H=H_H,OUT_M=M_M,OUT_L=L_L);U8:SCAN_LED PORT MAP(CLK=ALARM_CLK,SET_L=L_SET,H_IN=H_H,M_IN=M_M,L_IN=L_L,SG=CLOCK_DK,BT=CLOCK_WK);END;7.2时钟模块：7.2.1时钟顶层：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CLOCK IS PORT(CLK_1:IN STD_LOGIC;-电子钟的时钟信号； SET_H,SET_M:IN STD_LOGIC;-电子钟的小时与分钟设置； SET_EN:IN STD_LOGIC; -电子钟的小时与分钟调节 CLOCK_H:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);-电子钟的小时输出； CLOCK_M:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);-电子钟的分钟输出； CLOCK_S:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);-电子钟的秒输出：END;ARCHITECTURE EXAMPLE OF CLOCK ISCOMPONENT CNT60 -分秒声明； PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; COUT: OUT STD_LOGIC; CQ : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END COMPONENT;COMPONENT CNT24 -小时声明；PORT ( CLK : IN STD_LOGIC;RST : IN STD_LOGIC;COUT: OUT STD_LOGIC;CQ : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END COMPONENT;SIGNAL S_M,M_H:STD_LOGIC; SIGNAL S_M0,S_M1,S_M2:STD_LOGIC; SIGNAL M_H0,M_H1,M_H2:STD_LOGIC;BEGINS_M1=S_M AND (NOT SET_EN); -实现信号的选择；S_M2=SET_M;S_M0=S_M1 OR S_M2;M_H1=M_H AND (NOT SET_EN);M_H2=SET_H;M_H0CLK_1,COUT=S_M,CQ=CLOCK_S,RST=0);U2:CNT60 PORT MAP(CLK=S_M0,COUT=M_H,CQ=CLOCK_M,RST=0);U3:CNT24 PORT MAP(CLK=M_H0,CQ=CLOCK_H,RST=0);END EXAMPLE;7.2.2、60进制计数器（分钟，秒模块）：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT60 ISPORT ( CLK : IN STD_LOGIC;RST : IN STD_LOGIC;COUT: OUT STD_LOGIC;CQ : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END ;ARCHITECTURE BEHAV OF CNT60 ISSIGNAL COUNT : STD_LOGIC_VECTOR(7 DOWNTO 0);BEGIN PROCESS(CLK,RST)BEGIN IF RST= 1 THEN COUNT=00000000; ELSIF CLKEVENT AND CLK=1 THEN IF COUNT(3 DOWNTO 0)=1001 THENCOUNT(3 DOWNTO 0)=0000;COUNT(7 DOWNTO 4)=COUNT(7 DOWNTO 4)+1; ELSECOUNT(3 DOWNTO 0)=COUNT(3 DOWNTO 0)+1; END IF; IF COUNT=01011001 THENCOUNT=00000000;COUT=1; ELSE COUT=0; END IF;END IF; END PROCESS;CQ = COUNT;END BEHAV;7.2.3、24进制计数器（小时模块）：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT24 ISPORT ( CLK : IN STD_LOGIC;RST : IN STD_LOGIC;COUT: OUT STD_LOGIC;CQ : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END ;ARCHITECTURE BEHAV OF CNT24 ISSIGNAL COUNT : STD_LOGIC_VECTOR(7 DOWNTO 0);BEGIN PROCESS(CLK,RST)BEGIN IF RST= 1 THEN COUNT=00000000; ELSIF CLKEVENT AND CLK=1 THEN IF COUNT(3 DOWNTO 0)=1001 THENCOUNT(3 DOWNTO 0)=0000;COUNT(7 DOWNTO 4)=COUNT(7 DOWNTO 4)+1; ELSECOUNT(3 DOWNTO 0)=COUNT(3 DOWNTO 0)+1; END IF; IF COUNT=00100011 THENCOUNT=00000000;COUT=1; ELSE COUT=0; END IF;END IF; END PROCESS;CQ = COUNT;END BEHAV;7.3、闹钟模块LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ALARM IS PORT(CLK,SET_M,SET_H: IN STD_LOGIC; CLOCK_H, CLOCK_M:IN STD_LOGIC_VECTOR(7 DOWNTO 0); ALARM_H ,ALARM_M:INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); SPK_OUT:OUT STD_LOGIC);END;ARCHITECTURE ONE OF ALARM ISSIGNAL SQ,FQ:STD_LOGIC_VECTOR(7 DOWNTO 0);-传递小时位和分钟位的LED信号SIGNAL COUNT :STD_LOGIC;BEGIN ADJUST:PROCESS(SET_M,SET_H) BEGIN IF SET_MEVENT AND SET_M=1 THEN -分钟设置 IF SQ(3 DOWNTO 0)1001 THEN SQ(3 DOWNTO 0)=SQ(3 DOWNTO 0)+1; ELSE SQ(3 DOWNTO 0)=0000;SQ(7 DOWNTO 4)=SQ(7 DOWNTO 4)+1; END IF; IF SQ=01011001 THEN-60进制实现 SQ=00000000; END IF; END IF; IF SET_HEVENT AND SET_H=1 THEN -小时设置 IF FQ(3 DOWNTO 0)1001 THEN FQ(3 DOWNTO 0)=FQ(3 DOWNTO 0)+1; ELSE FQ(3 DOWNTO 0)=0000;FQ(7 DOWNTO 4)=FQ(7 DOWNTO 4)+1; END IF; IF FQ=00100011 THEN-24进制 FQ=00000000; END IF; END IF; END PROCESS ADJUST; ALARM_M=SQ;ALARM_H=FQ;COM:PROCESS(CLOCK_M, CLOCK_H, ALARM_M, ALARM_H,CLK) BEGIN IF CLOCK_M=ALARM_M AND CLOCK_H=ALARM_H THEN-把时钟信号和储存的闹钟时间比对SPK_OUTCLK_W,EN=EN_W,RST=RST_W,COUT=MS_S,CQ=STOP_MS);U2:CNT60_W PORT MAP(CLK=MS_S,RST=RST_W,COUT=S_M,CQ=STOP_S);U3:CNT100_W PORT MAP(CLK=S_M,RST=RST_W,CQ=STOP_M,EN=1);END;7.4.2、跑表60进制计数器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT60_W ISPORT ( CLK : IN STD_LOGIC;RST : IN STD_LOGIC;COUT: OUT STD_LOGIC;CQ : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END ;ARCHITECTURE BEHAV OF CNT60_W ISSIGNAL COUNT : STD_LOGIC_VECTOR(7 DOWNTO 0);BEGIN PROCESS(CLK,RST)BEGIN IF RST= 1 THEN COUNT=00000000; ELSIF CLKEVENT AND CLK=1 THEN IF COUNT(3 DOWNTO 0)=1001 THENCOUNT(3 DOWNTO 0)=0000;COUNT(7 DOWNTO 4)=COUNT(7 DOWNTO 4)+1; ELSECOUNT(3 DOWNTO 0)=COUNT(3 DOWNTO 0)+1; END IF; IF COUNT=01011001 THENCOUNT=00000000;COUT=1; ELSE COUT=0; END IF;END IF; END PROCESS;CQ = COUNT;END BEHAV;7.4.3、跑表100进制计数器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT60_W ISPORT ( CLK : IN STD_LOGIC;RST : IN STD_LOGIC;COUT: OUT STD_LOGIC;CQ : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END ;ARCHITECTURE BEHAV OF CNT60_W ISSIGNAL COUNT : STD_LOGIC_VECTOR(7 DOWNTO 0);BEGIN PROCESS(CLK,RST)BEGIN IF RST= 1 THEN COUNT=00000000; ELSIF CLKEVENT AND CLK=1 THEN IF COUNT(3 DOWNTO 0)=1001 THENCOUNT(3 DOWNTO 0)=0000;COUNT(7 DOWNTO 4)=COUNT(7 DOWNTO 4)+1; ELSECOUNT(3 DOWNTO 0)=COUNT(3 DOWNTO 0)+1; END IF; IF COUNT=01011001 THENCOUNT=00000000;COUT=1; ELSE COUT=0; END IF;END IF; END PROCESS;CQ = COUNT;END BEHAV;7.5、LED信号选择模块（MUX31A）：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY MUX31A IS PORT(CLK:IN STD_LOGIC;SET_EN:OUT STD_LOGIC; L: IN INTEGER RANGE 0 TO 5; STATE_OUT: OUT INTEGER RANGE 0 TO 2; CLOCK_H,CLOCK_M,CLOCK_S:IN STD_LOGIC_VECTOR(7 DOWNTO 0); ALARM_H,ALARM_M:IN STD_LOGIC_VECTOR(7 DOWNTO 0); SPORT_M,SPORT_S,SPORT_MS:IN STD_LOGIC_VECTOR(7 DOWNTO 0); OUT_H,OUT_M,OUT_L:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END ENTITY;ARCHITECTURE ONE OF MUX31A IS SIGNAL G1,G2,G3:STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL Q: INTEGER RANGE 0 TO 2;BEGIN PROCESS(CLK)BEGINIF CLKEVENT AND CLK=1 THEN IF Q2 THEN Q=Q+1;ELSE Q=0;END IF;END IF;STATE_OUT=Q;-SHUCHUXIANSHIZHHUANGTAIIF L=1 THENG2=10101010;G3=CLOCK_M;G1=01011111;SET_EN=1;-显示调整状态一SE- - - -00ELSIF L=2 THENG2=CLOCK_H;G3=10101010;G1=01011111;SET_EN=1;ELSIF L=3 THENG1=10111100;G2=10101010;G3=ALARM_M;SET_EN=0;ELSIF L=4 THENG1=10111100;G2=ALARM_H;G3=10101010;SET_EN=0;ELSIF L=5 THENG1=11000101;G2=10001000;G3=10001000;SET_ENG1=CLOCK_H;G2=CLOCK_M;G3=CLOCK_S;SET_ENG2=ALARM_H;G3=ALARM_M;G1=10111100;SET_ENG1=SPORT_M;G2=SPORT_S;G3=SPORT_MS;SET_EN=0;END CASE;END IF;END PROCESS;OUT_H=G1;OUT_M=G2;OUT_L=G3;END ONE;7.6、数码管扫描模块：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY SCAN_LED IS PORT( CLK,SET_L:IN STD_LOGIC; H_IN,M_IN,L_IN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);-高位，低位，中位显示信号 SG:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);-段控制信号 BT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);-位控制信号?END;ARCHITECTURE SCAN OF SCAN_LED IS SIGNAL SCANLED:STD_LOGIC_VECTOR(2 DOWNTO 0); -扫描信号；SIGNAL S_IN: STD_LOGIC_VECTOR(3 DOWNTO 0);-外部输入信号?SIGNAL L:STD_LOGIC;-传递占空比信号SIGNAL L_LEVEL:STD_LOGIC_VECTOR(1 DOWNTO 0);SIGNAL LEVEL_1,LEVEL_2,LEVEL_3:INTEGER RANGE 0 TO 6;BEGINP1:PROCESS(CLK) BEGIN IF CLKEVENT AND CLK=1 THEN IF SCANLED111 THEN SCANLED=SCANLED+1; ELSE SCANLED BT=0000000&L;S_IN BT=000000&L&0;S_IN BT=00000&L&00;S_IN BT=0000&L&000;S_IN BT=000&L&0000;S_IN BT=00&L&00000;S_IN BT=0&L&000000;S_IN BT=L&0000000;S_IN SG SG SG SG SG SG SG SG SG SG SG SG SG SG NULL; END CASE; END PROCESS P3;P4:PROCESS(SET_L) BEGIN IF SET_LEVENT AND SET_L=1 THEN IF L_LEVEL3 THEN L_LEVEL=L_LEVEL+1; ELSE L_LEVEL L IF LEVEL_1=2 THEN L=1 ;LEVEL_1=0;ELSE L=0 ;LEVEL_1 IF LEVEL_2=4 THEN L=1 ;LEVEL_2=0;ELSE L=0 ;LEVEL_2 IF LEVEL_3=6 THEN L=1 ;LEVEL_3=0;ELSE L=0 ;LEVEL_3=LEVEL_3+1;END IF;END CASE;END IF;END PROCESS P5;END;7.7、分频模块：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY FENPIN IS PORT (CLK : IN STD_LOGIC;CLK_10000 : OUT STD_LOGIC;CLK_100 : OUT STD_LOGIC;CLK_1 : OUT STD_LOGIC);END ENTITY;ARCHITECTURE BEH OF FENPIN ISSIGNAL CNT_5M:INTEGER RANGE 0 TO 4999999;SIGNAL CNT_50000:INTEGER RANGE 0 TO 49999;SIGNAL CNT_500:INTEGER RANGE 0 TO 499;SIGNAL CLK1: STD_LOGIC;SIGNAL CLK100:S