2006031459 黄德荣 5位逐级进位和超前进位加法器设计.doc

深 圳 大 学 实 验 报 告 课程名称： VHDL数字电路设计教程 实验项目名称： 5位逐级进位和超前进位加法器设计 学院： 信息工程学院 专业： 电子信息工程 指导教师： 梁松海 报告人：黄德荣 学号：20006031459 班级： 1班 实验时间： 2008.10.22 实验报告提交时间： 2008.11.5 教务处制实验目的与要求：用XILINX ISE 7.1i实现逐级进位和超前进位加法器方法、步骤：1，逐级进位加法器对每一位都使用了全加器FAU，图中a和b是输入位，cin是进位输入位。S是求和的结果，cout是进位输出位。C是进位矢量。图中每个全加器的输出结果都依赖于前一级产生的进位。由全加器的特性，可以写出如下的逻辑表达式：S=a XOR b XOR cincout=(a AND)（AND cin）OR（b AND cin）2，超前进位加法器电路实现是需要两个非常重要的中间信号：generate和propagate，分别由g和p表示。加法器两个输入位是a和b，则generate和propagate信号定义如下：g=a AND bp=a XOR b这两个信号与进位无关，只根据当前的输入计算。现在两个输入矢量是：a=a(4)a(3)a(2)a(1)a(0)和b=b(4)b(3)b(2)b(1)b(0),那么相应的generate矢量为g=g(4)g(3)g(2)g(1)g(0)，相应的propagate矢量为p=p(4)p(3)p(2)p(1)p(0)。其中： g(j)=a (j) AND b(j)p(j)=a (j)XOR b(j) 同时，进位矢量用c=c(4)c(3)c(2)c(1)c(0)。进位可由g和p按照下面的方法计算得到: c(0) = cin; c(1) = c(0)p(0)+g(0); c(2) = c(0)p(0)p(1)+g(0)p(1)+g(1); c(3) = c(0)p(0)p(1) p(2)+g(0)p(1)p(2)+(g(1) p(2)+g(2); c(4) = c(0)p(0) p(1) p(2) p(3)+g(0) p(1) p(2) p(3)+g(1) p(2) p(3)+g(2) p(3)+g(3);c(5) =c(0)p(0) p(1) p(2) p(3) p(4)+g(0) p(1) p(2)p(3) p(4)+g(1) p(2) p(3) p(4)+g(2) p(3) p(4)+g(4); 可见超前进位加法器的每个全加器不依赖与前一级进位输出的计算结果，有利于提高电路执行速度。实验过程及内容：1， 逐级进位加法器VHDL代码- Company: - Engineer:- Create Date: 02:59:18 10/22/08- Design Name: - Module Name: adder - Behavioral- Project Name: - Target Device: - Tool versions: - Description:- Dependencies:- - Revision:- Revision 0.01 - File Created- Additional Comments:- -library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents.all;entity adder isport(a,b:in std_logic_vector(4 downto 0);cin:in std_logic;s: out std_logic_vector(4 downto 0);cout:out std_logic);end adder;architecture Behavioral of adder is signal c:std_logic_vector(4 downto 0);beginc(0)=cin;s(0)=a(0) xor b(0) xor c(0);c(1)=(a(0)and b(0)or (a(0)and c(0)or (b(0)and c(0);s(1)=a(1) xor b(1) xor c(1);c(2)=(a(1)and b(1)or (a(1)and c(1)or (b(1)and c(1);s(2)=a(2) xor b(2) xor c(2);c(3)=(a(2)and b(2)or (a(2)and c(2)or (b(2)and c(2);s(3)=a(3) xor b(3) xor c(3);c(4)=(a(3)and b(3)or (a(3)and c(3)or (b(3)and c(3);s(4)=a(4) xor b(4) xor c(4);cout=(a(4)and b(4)or (a(4)and c(4)or (b(4)and c(4); end Behavioral;仿真波形2， 超前进位加法器VHDL代码- Company: - Engineer:- Create Date: 14:51:14 11/05/08- Design Name: - Module Name: sd - Behavioral- Project Name: - Target Device: - Tool versions: - Description:- Dependencies:- - Revision:- Revision 0.01 - File Created- Additional Comments:- -library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents.all;entity sd is port (a,b: in std_logic_vector (4 downto 0); cin: in std_logic;s: out std_logic_vector(4 downto 0);cout: out std_logic);end sd;architecture Behavioral of sd is signal c:std_logic_vector(5 downto 0); signal p:std_logic_vector(4 downto 0); signal g:std_logic_vector(4 downto 0); beginp(0)=a(0) xor b(0);g(0)=a(0) and b(0);c(0)=cin;s(0)=p(0) xor c(0);p(1)=a(1) xor b(1);g(1)=a(1) and b(1);c(1)=(cin and p(0) or g(0);s(1)=p(1) xor c(1);p(2)=a(2) xor b(2);g(2)=a(2) and b(2);c(2)=(cin and p(0) and p(1) or (g(0)and p(1) or g(1);s(2)=p(2) xor c(2); p(3)=a(3) xor b(3);g(3)=a(3) and b(3);c(3)=(cin and p(0) and p(1)and p(2) or (g(0)and p(1) and p(2) or (g(1)and p(2) or g(2);s(3)=p(3) xor c(3);p(4)=a(4) xor b(4);g(4)=a(4) and b(4);c(4)=(cin and p(0) and p(1)and p(2)and p(3) or (g(0)and p(1) and p(2) and p(3) or (g(1)and p(2) and p(3) or (g(2)and p(3) or g(3);s(4)=p(4) xor c(4); c(5)=(cin and p(0) and p(1) and p(2)and p(3) and p(4) or (g(0)and p(1) and p(2) and p(3)and p(4) or (g(1)and p(2) and p(3) and p(4) or (g(2)and g(3) and p(4) or