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DZ251多路数据采集、显示、存储系统,毕业设计
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1 8 位 CMOS 微控制器 GMS97C1051、 L1051 特点： 1 与 MCS 51TM 产品相容 2 1000 字节的电可编程序只读存储器 3 工作电压范围 4.25V 5.5V（ GMS97C1051）， 2.7V 3.6V（ GMS97C1051） 4 工作频率说明 12MHZ、 24MHZ（ GMS97C1051） 12MHZ（ GMS97L1051） 5 两种带有加密配置的程序存储器 6 64 字节 SRAM 7 15 个可编程的 I、 O 8 一个 16 位计数器、计时器 9 三个中断源 10 直接发光二极管驱动输出 11 片上逻辑比较电路 描述： 1 GMS97C1051、 L1051 是带有 1000 字节的电可编程序只读存储器的高级 8 位 CMOS做控制器 2 这种芯片与工业标准 MCS 51 的程序的启动与管脚引出线相一 致 3 HYUNDAI 做电子 GMS97C1051、 L1051 是一种强有力的做控制器 4 能够提供一种有效的高强度伸缩性嵌入式控制应用方法 GMS97C1051、 L1051 具有以下典型特点： 1 1000 字节的电可编程只读存储器 2 64K 的 RAM 3 15 个 I、 O 4 16 位的计时器、定时器， 1 个带有三个矢量两个中断， 1 个精确逻辑编辑器，一个时钟晶振输入 5 支持两种可选择节省方式的软件 6 当允许 RAM，定时器 ，计数器，并中口和中断系统继续起做用的时候 IDLE MODE将关闭 CPU 7 直到下一个硬件命令到来之前，低功耗模式将只让工 RAM 的内容得以存储，其它的芯片功能将被停止 nts 2 芯片引脚外形： 芯片引脚描述： 1 VCC 提供电压 2 GND 接地 3 PORT1 8 位双向 I、 O 口， P1.2 P1.7 提供内部上拉源。 P1.0 P1.1 需要外部上拉源，P1.0 P1.1 也提供正向输入和负向输入，特别是片上逻辑比较器。 PORT1 可以输入10MA，也可以直接驱动 LED 显示。当对 PORT1 进行写入的时候，它们可以做为输入端。因为上拉源的存在，当 PORT1.0 1.1 做为输入并被外部拉低的时候，它们会被提供。当对 EPROM 进行编程各程序确认的时候， PORT1 也接收数据 4 PORT3 P3.0 P3.5， P3.7 是七个带内部上拉源的双向 I、 O 口。这 P3.6 是被硬件 化的做为片上逻辑比较器输出的输入口，是不能用做通用 I、 O 口。它们的输出缓冲可达到 10MA。当对它进行写入的时候，它们就被内部上拉源拉高，也可做为输入口。做为输入。它提供的并行口功能被列在下表中： 它也接收 EPROM 和确认控制信号。 5 RST 复位输入。当它被输入高电平时，所有的端口都被复位。这个端口在 EPROM 编程时提供 12.75V 的电压。 nts 3 6 XTAL1 输入晶振放大器和输入内部时钟电路 7 XTAL2 从晶振输出 推荐的反相电路： XTAL1 和 XTAL2 是输入量和输出量，特别的它可以做为反相器的数，为了从外部锁存器 驱动此装置， XTAL2 应该在 XTAL2 应该在 XTAL1 指示 FIGURE2 不连接。 特殊功能寄存器： 片上存储单元被称为特殊功能寄存器。被用到的地址都被记录下，没有用到的在片上没有被实行。读这些输入口地 址将同时返回确认信息，输入口的地址会有不确定的信息。用户软件不应该把未被写入的地址用上，因为它们将被用在未来其它新功能的应用。如果那样的话，升级和改进将没有可能。 TIMER COUNTER 0： GM89TC1051 L1051 有一个 16 位的计时器 计数器： TIMER 0。作为计时器，这种寄存器每次机械循环便增加一次，因为一个机械循环包括 12 个振荡周期，计数速率是振荡频率的 1/12。 作为计数器，这种寄存器在外部 P3.4、 T0 输入的 1 0 的转变与它相一致时才增加一次。 因为 2 个机械周期被规定为 1 0 转变，最大的计数速率是振动频率的 1/24。外部输入 P3.2 INT0 P3.3 INT1 能够编程人为脉冲宽度测量 计时器 计数 器能被用在四种工作方式中。 中断系统： GMS97C1051 L1051 提供了 3 个中断源（ 2 个外部中断和一个计时器中断）。低优先权中断本身被高优先权中断，但不能被其它低优先权中断。高优先权中断不能被其它优先权中断。如果两种相同等级的中断同时发出请求，一种内部的定时询问顺序决定执行哪个。 关于某些程序的限制： GMS97C1051 L1051 是一种经济有效的 HYUNDAI 微 电子家族成长的一员。包含有1KB 的 EPROM 程序存储器，与 MCS 51 产品相容，能够用于 MCS 51 程序启动。然而，在某种场合下使用时谨慎注意以下几点： 1 分支指令程序 LCALL LJMP ACALL AJMP SJMP JMP A DPTR 这些无条件的分支指令程序超出存储器的边界时，程序将被 错误的执行（ GMS97C1051 L1051 的地址是 00H 3FFH）违反物理地址限制将引起不可知的程序出错。 CJNE DJNX JB JNB JC JNC JBC JZ JNZ nts 4 这些有条件的分支指令程序与上面请求的规则一致。违反存储边界，将引起不可知道的错误。因为运用中断程序， 8051 的中断服务地址将补被保留。 2 MOVX GMS97C1051 L1051包括 64字节的内部数据存储器，并且它只限于 64B的 RAM，外部 KATA 数据存储器不支持，因此，一种典型的 8051 计算机语言将汇编语言程序即使违反了上述约定也可以被写入。微处理器的使用者有责任了解芯片的功能和对其编程时的调节及使用。 IDLE MODE： 当芯片处于 IDLE 模式时，当外部设备处于活动状态时， CPU 也会使其处在睡眠状态 ,这种方式一般用在软件部分。片上 RMAR 内容和所用特殊功能寄存器，在此方式下均无改变。 IDLE 方式会被中断或外部复位所中止。如果没有外部上拉源或置 1，P1.0 P1.1，会被置 0。 被外部硬件中止的 IDLE 将被记忆， 设备一般 会从中断的地方继续执行， 但在执行之前会运行 2 个机器周期。 在这个事件中， 片上的硬件会制止对于 RAM 的操作。 但对于管脚的操作不会制止 。 在 IDLE 被外 部硬件所中断时，为了减少不可控制的写入，结构规定可以有 IDLE 模式的是不 可以向端口和外部存储器操作的。 POWER DOWM MODE： GMS97C1051 L1051 有两种电源节约方式，即 IDLE 和 POWER DOWN 方式。 寄存器 PCON 来选择是用 PD 和 IDLE 方式。如果被写入 PD 和 IDLE 是同时的， PD 优先级较高 。 在 POWER DOWN 运行方式下， VCC 被减小到最低功耗。这一点一定会被 确保，然而， VCC 在 POWER DOWN 方式被运用时才减小， VCC 在 POWER DOWN 方 式被终止时恢复到它的正常运行标准。复位信号终止 POWER DOWN 方式的同时， 也重启动振荡器。直到 VCC 恢复到正常工 作标准复位才正常，但需要一段时间， 这期间用于使振荡器复位和稳定。 PROGRAMMING THE EPROM： GMS97C1051 执行程序时被用于修改 PUICK PULSE PROGRAMMING TM 算法。 它在用于 VPP（程序供给电压）和 P3.2 的宽度的价值上不同于旧的方式。 GMS97C1051 L1051 包含两个字节能够多用于读操作各 EPROM 程序执行系统的确 认。这种确认被作为这种芯片作为 HME 的大规模制成品之一。 EPROM PROGRAMMING 和确认： GMS97C1051 L1051 包含了一个内部 EPROM 计数器地址，启动地址是 RST 的 边 界 03FFH 之后，是 P3.0 到应用到连续的电平转换到 P3.0。 PROGRAMMING 算法： 为了执行 GMS971051L1051 推荐如 下 顺序 ： 1 POWER UP 顺序：提供电压范围在 VCC 和带有振荡器的 GND 之间启动 P3.0 到 H， nts 5 2 复位 RST 到 GND 随着所有其它管脚改变，等待时间超过 10MS。 3 应用这种适合的高低逻辑电平相结合对于管脚 P3.4 P3.5， P3.7 在 EPROM 程序方式下来此选择程序运行的方式之一。 4 P3.0 被内部上拉拉高， 并可用作输入，其地址为 0000H。 5 在片内 EPROM 编程 这个引脚也是 12.75V 编程电源电压 Vpp 的输入端。 6 P3.2 中断 0 输入 /定时器 0 选通控制 10us。 7 当振荡器工作时，保持 RST 引脚为高电平经二个机器周期，期间即复位。复位后所有 I/O 引脚都置为“ 1”。此时 P3.0 并未改变。 8 P3.0 接收器下一个地址的数据输入或输出，能够提高内部地址寄存器。提供新的数据给 P1 引脚。 9 重复步骤 5，改变数据和地址寄存器。 程序 打开或关闭文件的读写校验 1 程序存储器的寻址范围为 0000H 03FFH，保持 RST引脚为高电平经二个机器周期，期间即复位，此时， P3.0 口从高电平到低电平。 2 应用适当的 控制信号作为 P3.3， P3.4， P3.5， P3.7 读信号， P1 引脚输出。 3 P3.0 被提高内部数据寄存器。 4 在 P1 口读取下一个数据。 5 直到全部地址被读后重复步骤 3 和步骤 4。 nts 1 8-Bit CMOS Microcontorller GMS97C1051/L1051 Features _ Compatible with MCS-51TM Products _ 1 Kbytes of programmable EPROM _ 4.25V to 5.5V Operating Range (GMS97C1051) 2.70V to 3.6V Operating Range (GMS97L1051) _ Version for 12MHz / 24 MHz Operating frequency (GMS97C1051) Only 12MHz Operating frequency (GMS97L1051) _ Two-Level Program Memory Lock with encryption array _ 64 bytes SRAM _ 15 Programmable I/O Lines _ One 16-Bit Timer/Counter _ Three Interrupt Sources _ Direct LED Drive Outputs _ On-Chip Analog Comparator _ Low Power Idle and Power Down Modes Description The GMS97C1051/L1051 is a high-performance CMOS 8-bit microcontroller with 1Kbytes of programmable EPROM. The device is compatible with the industry standard MCS-51TM instruction set and pinout. The HYUNDAI MicroElectronics GMS97C1051/L1051 is a powerful microcontroller which provides a highly flexible and cost effective solution to many embedded control applications. The GMS97C1051/L1051 provides the following standard features: 1Kbytes of EPROM, 64 bytes of RAM, 15 I/O lines, 16-bit timer/counter, a three vector two-level interrupt architecture, a precision analog comparator, on-chip oscillator and clock circuitry. In addition, the GMS97C1051/L1051 supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset. Pin Configuration nts 2 Pin Description Vcc Supply voltage. GND Ground. Port 1 Port 1 is an 8-bit bidirectional I/O port. Port pins P1.2 to P1.7 provide internal pullups. P1.0 and P1.1 require external pullups. P1.0 and P1.1 also serve as the positive input (AIN0) and the negative input (AIN1), respectively, of the on-chip precision analog comparator. The Port 1 output buffers can sink 10mA and can drive LED displays directly. When 1s are written to Port1 pins, they can be used as inputs. When pins P1.2 to P1.7 are used as inputs and are externally pulled low, they will source current (IIL) because of the internal pullups. Port 1 also receives code data during EPROM programming and program verification. Port3 Port 3 pins P3.0 to P3.5, P3.7 are seven bidirectional I/O pins with internal pullups. P3.6 is hard-wired as an input to the output of the on-chip comparator and is not accessible as a general purpose I/O pin. The Port 3 output buffers can sink 10mA. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups. Port 3 also serves the functions of various special feature of the GMS97C1051/L1051 as listed below: nts 3 Port 3 also receives some control signals for EPROM programming and programming verification. RST Reset input. All I/O pins are reset to 1s as soon as RST goes high. Holding the RST pin high for two machine cycles while the oscillator is running resets the device. This pin is also receives the 12.75V programming supply voltage ( Vpp ) during EPROM programming. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier. Recommended Oscillator Circuit XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. Special Function Registers A map of the on-chip memory area called the Special Function Register (SFR) space is shown in the Table1, Table 2 and Table 3. Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0. Timer/Counter 0 nts 4 The GMS97C1051/L1051 has one 16-bit Timer/ Counter register : Timer0 . As a Timer, the register is incremented every machine cycle. Thus, the register counts machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. As a counter, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin P3.4/T0. Since 2 machine cycles are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. External inputs P3.2/INT0 and 3.3/INT1 can be programmed to function as a gate to facilitate pulse width measurements. Timer/Counter 0 can be used in four operating modes as listed in Table 4. Figure 3 illustrates the input clock logic. Interrupt System The GMS97C1051/L1051 provides 3 interrupt sources ( two external interrupts and timer interrupt ) with two priority levels. Figure 4 gives a general overview of the interrupt sources and illustrates the request and control flags. A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source. If two requests of different priority levels are received simultaneously, the request of higher priority is serviced. If requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence like Table 6. Figure 4. Interrupt Request Sources Restrictions on Certain Instructions The GMS97C1051/L1051 is an economical and costeffective member of HYUNDAI MicroElectronics growing family of microcontrollers. It contains 1Kbytes of EPROM program memory. It is fully compatible with the MCS-51 architecture, and can be programmed using the MCS-51 instruction set. However, there are a few considerations one must keep in mind when utilizing certain instructions to program this device. 1. Branching instructions: LCALL, LJMP, ACALL, AJMP, SJMP, JMP,A+DPTR nts 5 These unconditional branching instructions will execute correctly as long as the programmer keeps in mind that the destination branching address must fall within the physical boundaries of the program memory size (locations 00H to 3FFH for the GMS97C1051/L1051). Violating the physical space limits may cause unknown program behavior. CJNE ., DJNZ ., JB, JNB, JC, JNC, JBC, JZ, JNZ With these conditional branching instructions the same rule above applies. Again, violating the memory boundaries may cause erratic execution. For applications involving interrupts the normal interrupt service routine address locations of the 80C51 family architecture have been preserved. 2. MOVX-related instructions, Data Memory: The GMS97C1051/L1051 contains 64 bytes of internal data memory. Thus, in the GMS97C1051/L1051 the stack depth is limited to 64 bytes, the amount of available RAM. External DATA memory access is not supported in this device, nor is external PROGRAM memory execution. Therefore, no MOVX . instructions should be included in the program. A typical 80C51 assembler will still assemble instructions, even if they are written in violation of the restrictions mentioned above. It is the responsibility of the controller user to know the physical features and limitations of the device being used and adjust the instructions used correspondingly. Idle Mode In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. P1.0 and P1.1 should be set to 0 if no external pullups are used, or set to 1 if external pull-ups are used. It should be noted that when idle is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. nts 6 To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following one that invokes Idle should not be one that writes to a port pin or to external memory. Power Down Mode GMS97C1051/L1051 have two power saving modes, Idle and Power Down. The bits PD and IDLE of the register PCON select the Power Down mode and the Idle mode, respectively. If 1s are written to PD and IDLE at the same time, PD takes precedence. Table 7 gives a general overview of the Power saving modes. In the Power Down mode of operation, VCC can be reduced to minimize power consumption. It must be ensured, however, that Vcc is not reduced before the Power Down mode is invoked, and that Vcc is restored to its normal operating level, before the Power Down mode is terminated. The reset signal that terminates the Power down mode also restarts the oscillator. The reset should not be activated before Vcc is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. ( similar to power-on reset ). Programming The EPROM The GMS97C1051/L1051 is programmed by using a modified Quick-Pulse ProgrammingTM algorithm. It differs from older methods in the value used for VPP (programming supply voltage) and in the width and number of theP3.2(PROG )TheGMS97C1051/L1051 contains two signature bytes that can be read and used by an EPROM programming system to identify the device. The signature bytes identify the device as an manufactured by HME. Table 8 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the security bits. The circuit configuration and waveforms for quick-pulse programming are shown in Figures 5 and Figure 8. Figure 6 shows the circuit configuration for normal program memory verification. EPROM Programming and Verification Internal Address Counter : The GMS97C1051/L1051 contains an internal EPROM address counter which is always set to 03FFH on the rising edge of RST after nts 7 setting P3.0 to H and is advanced by applying continuous level transition to pin P3.0. Programming Algorithm : To program the GMS97C1051/L1051, the following sequence is recommended. 1. Power-up Sequence Apply power between VCC and GND pins with crystal oscillation. Set P3.0 to H. Set RST to GND. With all
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