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DZ231步进电动机的DSP控制,毕业设计
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学 位 论 文 中北大学分校学位论文英文翻译 作 者 姓 名： 谢 安 专 业 名 称： 电子信息工程 学 号 ： 0420221 48 指 导 教 师： 楼国红 完 成 日 期： 2008 年 06 月 中北大学分校 nts中北大学分校学位论文英文翻译 1 英文原文： TMS320LF/LC240xA DSP ControllersReference Guide The TMS320Lx240xA series of devices are members of the TMS320_ familyof digital signal processors (DSPs) designed to meet a wide range of digitalmotor control (DMC) and other embedded control applications. This series isbased on the C2xLP 16-bit, fixed-point, low-power DSP CPU, and is complementedwith a wide range of on-chip peripherals and on-chip ROM or flash programmemory, plus on-chip dual-access RAM (DARAM). This reference guide describes the following 240xA devices: 2407A, 2406A, 2404A, 2403A, 2402A, and 2401A. This chapter provides an overview of the current TMS320 family, describes thebackground and benefits of the 240xA DSP controller products, and introducesthe 240xA devices. These low-cost DSPs are intended to enable multipleapplications for a nominal price. Devices within a generation of a TMS320 platform have the same CPU structurebut different on-chip memory and peripheral configurations. Spin-offdevices use new combinations of on-chip memory and peripherals to satisfya wide range of needs in the worldwide electronics market. By integratingmemory and peripherals onto a single chip, TMS320 devices reduce systemcosts and save circuit board space. 1.2 TMS320C240xA Series of DSP Controllers Control-Based Applications The 240xA DSP controllers are designed to meet the needs of control-based applications. By integrating the high performance of a DSP core and the on-chip peripherals of a microcontroller into a single-chip solution, the 240xA series yields a device that is an affordable alternative to traditional microcontroller units (MCUs) and expensive multichip designs. At 40 million instructions per second (MIPS), the 240xA DSP controllers offer significant performance over traditional 16-bit microcontrollers and microprocessors. (240x devices operate at 30 MIPS.) The 16-bit, fixed-point DSP core of the 240xA device provides analog designers a digital solution that does not sacrifice the precision and performance of their systems. In fact, system performance can be enhanced through the use of advanced control algorithms for techniques such as adaptive control, Kalman filtering, and state control. The 240xA DSP controllers offer reliability and programmability. Analog control systems, on the other hand, are hardwired solutions and can experience performance degradation due to aging, component tolerance, and drift. Reduced Development Time nts中北大学分校学位论文（设计） 2 The high-speed central processing unit (CPU) allows the digital designer to process algorithms in real time rather than approximate results with look-up tables. The instruction set of these DSP controllers, which incorporates both signal processing instructions and general-purpose control functions, coupled with the extensive development support available for the 240xA devices, reduces development time and provides the same ease of use as traditional 8- and 16-bit microcontrollers. The instruction set also allows you to retain your software investment when moving from other general-purpose TMS320 fixedpoint DSPs. It is source- and object-code compatible with the other members of the 24x generation, source-code compatible with the C2x generation, and upwardly source-code compatible with the C5x generation of DSPs from Texas Instruments. The 240xA architecture is also well-suited for processing control signals. It uses a 16-bit word length along with 32-bit registers for storing intermediate results, and has two hardware shifters available to scale numbers independently of the CPU. This combination minimizes quantization and truncation errors, and increases processing power for additional functions. Such functions might include a notch filter that could cancel mechanical resonances in a system or an estimation technique that could eliminate state sensors in a system. The 240xA DSP controllers take advantage of an existing set of peripheral functions that allow Texas Instruments to quickly configure various series members for different price/performance points or for application optimization. This library of both digital- and mixed-signal peripherals includes: _ Event manager _ Controller Area Network (CAN) _ Serial communications ports (SCI, SPI) _ Analog-to-digital converters (ADC) _ Safety features such as watchdog timer and power drive protection The DSP controller peripheral library is continually growing and changing to suit the needs of tomorrows embedded control marketplace. 1.3 Peripheral Overview The peripheral set for the 240xA devices includes: _ Event Manager: Timers and PWM generators for digital motor control _ CAN Interface: Controller Area Network (CAN) 2.0b compatible, with six mailboxes (not available in 2402A and 2404A) _ A/D: 10-bit 2, 375-ns conversion (425-ns in LC2402A), 16/8 channel, analog-to-digital converter _ SPI: Serial Peripheral Interface synchronous serial port (not available in 2402A) nts中北大学分校学位论文英文翻译 3 _ SCI: Serial Communications Interface asynchronous serial port (universal asynchronous receiver and transmitter UART) _ Watchdog timer _ General-purpose bidirectional digital I/O (GPIO) pins 1.4 New Features in 240xA Devices The following new features were added in the 240xA devices:(compared to 240x devices) _ 40-MHz operation (as compared to 30 MHz for the 240x family) _ Code security for on-chip Flash/ROM _ Input qualifier circuitry for PDPINTx, CAPn, XINTn, and ADCSOC pins _ Status of the PDPINTx pin is reflected in the COMCONx register Memory 3.1 On-Chip RAM The 240xA on-chip RAM includes on-chip dual-access RAM (DARAM) and on-chip single-access program/data RAM (SARAM). 3.1.1 Dual-Access On-Chip RAM All Lx240xA devices have 544 words 16 bits of on-chip DARAM, which can be accessed twice per machine cycle. The 544 words are divided into three blocks: B0, B1, and B2. This memory is primarily intended to hold data but, in the case of B0, can also hold programs. B0 can be configured in one of two ways depending on the value of the CNF bit. CNF = 0 maps B0 in data memory, while CNF = 1 maps B0 in program memory. In the pipeline operation, the CPU reads data on the third cycle and writes data on the fourth cycle. However, DARAM allows the CPU to write and read in one cycle; the CPU writes to DARAM on the master phase of the cycle and reads from DARAM on the slave phase. For example, suppose two instructions, A and B, store the accumulator value to DARAM and load the accumlator with a new value from DARAM. Instruction A stores the accumulator value during the master phase of the CPU cycle, and instruction B loads the new value to the accumulator during the slave phase. Because part of the dual-access operation is a write, it only applies to RAM. 3.1.2 Single-Access On-Chip Program/Data RAM Some of the Lx240xA devices have up to 2K 16-bit words of single-access RAM (SARAM). The addresses associated with the SARAM can be used for both data memory and program memory, and are software configurable to either external memory or the internal SARAM. When configured as external, these addresses can be used for off-chip program memory. SARAM is accessed only once per CPU cycle. When the CPU requests multiple accesses, the nts中北大学分校学位论文（设计） 4 SARAM schedules the accesses by providing a not-ready condition to the CPU and then executing the accesses one per cycle. For example, if the instruction sequence involves storing the accumulator value and then loading a value to the accumulator, it would take two cycles to complete in SARAM, compared to one cycle in DARAM. 3.2 Factory Masked On-Chip ROM The on-chip ROM in ROM devices is mapped in program memory space. This ROM is always enabled since these devices lack an external memory interface. This ROM is programmed with customer-specific code. 3.3 Flash The on-chip flash in flash devices is mapped in program memory space. This flash memory is always enabled in devices that lack an external memory interface. For the 2407A, which has an external memory interface, the MP/MC pin determines whether the on-chip program memory (flash) or the off-chip program memory (customer design specific) is accessed. 3.3.1 Flash Program Memory The Flash module is used to provide permanent program storage. The Flash can be programmed and electrically erased many times to allow code development. The 240xA Flash is similar to that on the 24x devices, with some key differences and enhancements. 240xA Flash features are as follows: _ Flash run-time execution at 3.3 V _ Flash programming requires a 5-V supply (5%) at VCCP pin _ Flash has multiple sectors that can be protected while erasing _ Flash programming registers are similar to those on the 24x devices _ Flash programming is done through CPU _ 240xA devices come with JTAG interface to aid programming and emulation _ A 256-word Boot ROM is available on 240xA devices to enable programming through SCI or SPI ports The following sections explain the Flash programming registers and their bit functions. Flash programming utilities will be provided by Texas Instruments (TI). Refer to the TIs web page (, under 24x Flash tools) for revisions of these utilities. 3.3.2 Flash Control Mode Register (FCMR) The Flash control mode register is in internal I/O space FF0Fh. This register is a dummy register address to enable the Flash in Flash array mode or in Flash control register mode. The Flash control registers are used to program the Flash array. These registers are a part of the Flash wrapper and are mapped at the same start address as the Flash array itself. These registers are not visible (disabled) during Flash array mode (i.e., Flash read). During the Flash nts中北大学分校学位论文英文翻译 5 control register mode, the Flash program control registers are enabled and the Flash array is disabled (i.e., not accessible to CPU). 3.3.3 Flash Control Register Access In addition to the flash memory array, the flash module has four registers that control operations on the flash array. At any given time, you can access the memory array in the flash module (array-access mode) or you can access the control registers (register-access mode) but you cannot access both simultaneously. The flash module has a flash-access control register that selects between the two access modes. This register is the flash control mode register (FCMR) and is mapped at FF0Fh in I/O space. This is a special type of I/O register that cannot be read. The register functions as follows: _ An OUT instruction, using the register address as an I/O port, places theflash module in register-access mode. The data operand used is insignificant. For example: OUT dummy, 0FF0Fh; Selects register-access mode _ An IN instruction, using the register address as an I/O port, places the flash module in array-access mode. The data operand used is insignificant. For example: IN dummy, 0FF0Fh; Selects array-access mode. nts中北大学分校学位论文（设计） 6 About DSP Builder New Feature in Version 2.1.3 Generates a Verilog HDL testbench for simulation with a Quartus II Verilog Output File (.vo) Supports Quartus II version 3.0 New blocks: Barrel Shifter (Arithmetic library) Bit Level Sum of Products (Arithmetic library) FIFO (Storage library) Flip Flop (Gates library) Memory Delay (Storage library) NOT (Gates library) Round (Bus Manipulation library) Saturate (Bus Manipulation library) New PLL option for indicating whether PLL output clocks should be kept internal or output to pins The SubSystem Builder block imports Verilog HDL files (.v) in addition to VHDL files for black-boxing subsystems Features Links The Mathworks MATLAB (Signal Processing ToolBox andFilter Design Toolbox) and Simulink environment with the AlteraQuartus II environment MATLAB version 6.5/Simulink 5.0 support Supports Altera DSP cores that are downloadable from the Alter aweb site (e.g., FIR Compiler, Reed-Solomon Compiler, etc.) Supports Altera devices: Stratix GX devices Cyclone devices Stratix devices APEX II devices APEX 20KE devices APEX 20KC devices Mercury devices ACEX 1K devices FLEX 10K devices FLEX 6000 devices nts中北大学分校学位论文英文翻译 7 Enables rapid prototyping using the Altera DSP development boards Supports the SignalTap II logic analyzer, an embedded signal analyzer that probes signals from the Altera device on the DSP board and imports the data into the MATLAB work space to facilitate visual analysis Includes blocks that you can use to build custom logic that works with the SOPC Builder and Nios embedded processor designs Includes PLL block for multi-clock designs Includes state machine block Supports a unified representation of the algorithm and implementation of a DSP system Automatically generates a VHDL testbench or Quartus II Vector File (.vec) from MATLAB and Simulink test vectors Automatically launches VHDL synthesis and Quartus II compilation Enables bit- and cycle-accurate design simulation Provides a variety of fixed-point arithmetic and logical operators for use with the Simulink software General Description Digital signal processing (DSP) system design in Altera programmable logic devices requires both high-level algorithm and hardware description language (HDL) development tools. The Altera DSP Builder integrates these tools by combining the algorithm development, simulation, and verification capabilities of The MathWorks MATLAB and Simulink system-level design tools with VHDL synthesis, simulation, and Altera development tools。 DSP Builder shortens DSP design cycles by helping you create the hardware representation of a DSP design in an algorithm-friendly development environment. You can combine existing MATLAB functions and Simulink blocks with Altera DSP Builder blocks and Altera intellectual property (IP) MegaCore functions to link system-level design and implementation with DSP algorithm development. DSP Builder allows system, algorithm, and hardware designers to share a common development platform. You can use the blocks in DSP Builder to create a hardware implementation of a system modeled in Simulink in sampled time. DSP Builder contains bit- and cycle-accurate Simulink blocks, which cover basic operations such as arithmetic or storage functions and takes advantage of key device features such as built-in PLLs, DSP blocks or embedded memory. You can integrate complex functions by using MegaCore functions in your DSP Builder model MegaCore Functions nts中北大学分校学位论文（设计） 8 Altera MegaCore functions are usually delivered as low-cost, encrypted functions that can be instantiated directly in your design. MegaCore functions support Alteras free IP evaluation features, which allow you to verify the functionality and timing of a function prior to purchasing a license. The OpenCore evaluation feature lets you test-drive IP cores for free using the Quartus II software; however, you cannot generate device programming files to test the core in hardware. The OpenCore Plus evaluation feature enhances the OpenCore evaluation feature by supporting free hardware evaluation. This feature allows you to generate time-limited programming files for a design that includes Altera MegaCore functions. With these files, you can perform board-level design verification before deciding to purchase licenses for the MegaCore functions. With both evaluation features, you only need to purchase a license when you are completely satisfied with a cores functionality and performance, and would like to take your design to production. The DSP Builder SignalCompiler block reads Simulink Model Files (.mdl) that are built using DSP Builder and MegaCore blocks and generates VHDL files and Tcl scripts for synthesis, hardware implementation, and simulation. High-Speed DSP with Programmable Logic Programmable logic offers compelling performance advantages over dedicated digital signal processors. Programmable logic can be thought of as an array of elements, each of which can be configured as a complex processor routine. These processor routines can then be linked together in serial (the same way digital signal processor would execute them), or they can be connected in parallel. In parallel, they offer many times the performance of standard digital signal processors by executing hundreds of instructions at the same time. Algorithms that benefit from this improved performance include FEC, modulation/demodulation, and encryption. Traditionally, designers had to make a trade-off between the flexibility of off-the-shelf digital signal processors and the performance of custom-built devices. Altera Stratix devices eliminate the need for this trade-off by providing exceptional performance combined with the flexibility of programmable logic devices (PLDs). Stratix devices have dedicated DSPblocks, which have high-speed parallel processing capabilities, that are optimized for DSP applications. Additionally, the TriMatrix memory structures can implement a wide variety of memory functions found in complex designs. nts中北大学分校学位论文英文翻译 9 The Stratix DSP block is composed of multipliers, adders, subtractors,accumulators, a summation unit, and pipeline registers. The DSP block is optimized for all DSP applications and can provide data throughput of up to 2.0 GMACS per DSP block (for 9 9 bit data widths). The DSP block is versatile, highly efficient, and easy to use. You can implement a 4-tap FIR filter or complex multiplication inside a single DSP block without using additional logic. The TriMatrix memory structure is a significant breakthrough in on-chip memory technology and offers a wide range of memory features. By efficiently integrating embedded RAM, the TriMatrix memory brings unprecedented amounts of memory bits (up to 1
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