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DZ213单片机实现的步进电机通用控制器

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DZ213单片机实现的步进电机通用控制器,毕业设计
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C0077C0083C0080C0052C0051C0048C0120C0049C0051C0120C0044 C0077C0083C0080C0052C0051C0048C0120C0049C0052C0120C0044 C0077C0083C0080C0052C0051C0048C0120C0049C0052C0120C0049C0077C0073C0088C0069C0068 C0083C0073C0071C0078C0065C0076 C0077C0073C0067C0082C0079C0067C0079C0078C0084C0082C0079C0076C0076C0069C0082SLAS272F JULY 2000 REVISED JUNE 20041POST OFFICE BOX 655303 DALLAS, TEXAS 75265C0068 Low Supply-Voltage Range, 1.8 V . . . 3.6 VC0068 Ultralow-Power Consumption: Active Mode: 280 A at 1 MHz, 2.2V Standby Mode: 1.6 A Off Mode (RAM Retention): 0.1 AC0068 Five Power-Saving ModesC0068 Wake-Up From Standby Mode in less than 6 sC0068 16-Bit RISC Architecture,125-ns Instruction Cycle TimeC0068 12-Bit A/D Converter With InternalReference, Sample-and-Hold and AutoscanFeatureC0068 16-Bit Timer_B With SevenCapture/Compare-With-Shadow RegistersC0068 16-Bit Timer_A With ThreeCapture/Compare RegistersC0068 On-Chip ComparatorC0068 Serial Onboard Programming,No External Programming Voltage NeededProgrammable Code Protection by SecurityFuseC0068 Serial Communication Interface (USART),Functions as Asynchronous UART orSynchronous SPI Interface Two USARTs (USART0, USART1) MSP430x14x(1) Devices One USART (USART0) MSP430x13xDevicesC0068 Family Members Include: MSP430F133:8KB+256B Flash Memory,256B RAM MSP430F135:16KB+256B Flash Memory,512B RAM MSP430F147, MSP430F1471:32KB+256B Flash Memory,1KB RAM MSP430F148, MSP430F1481:48KB+256B Flash Memory,2KB RAM MSP430F149, MSP430F1491:60KB+256B Flash Memory,2KB RAMC0068 Available in 64-Pin Quad Flat Pack (QFP)and 64-pin QFNC0068 For Complete Module Descriptions, See theMSP430x1xx Family Users Guide,Literature Number SLAU049The MSP430F14x1 devices are identical to the MSP430F14xdevices with the exception that the ADC12 module is notimplemented.descriptionThe Texas Instruments MSP430 family of ultralow-power microcontrollers consist of several devices featuringdifferent sets of peripherals targeted for various applications. The architecture, combined with five low powermodes is optimized to achieve extended battery life in portable measurement applications. The device featuresa powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6 s.The MSP430x13x and the MSP430x14x(1) series are microcontroller configurations with two built-in 16-bittimers, a fast 12-bit A/D converter (not implemented on the MSP430F14x1 devices), one or two universal serialsynchronous/asynchronous communication interfaces (USART), and 48 I/O pins.Typical applications include sensor systems that capture analog signals, convert them to digital values, andprocess and transmit the data to a host system. The timers make the configurations ideal for industrial controlapplications such as ripple counters, digital motor control, EE-meters, hand-held meters, etc. The hardwaremultiplier enhances the performance and offers a broad code and hardware-compatible family solution.Copyright 2000 2004, Texas Instruments IncorporatedC0080C0082C0079C0068C0085C0067C0084C0073C0079C0078 C0068C0065C0084C0065 C0105C0110C0102C0111C0114C0109C0097C0116C0105C0111C0110 C0105C0115 C0099C0117C0114C0114C0101C0110C0116 C0097C0115 C0111C0102 C0112C0117C0098C0108C0105C0099C0097C0116C0105C0111C0110 C0100C0097C0116C0101C0046C0080C0114C0111C0100C0117C0099C0116C0115 C0099C0111C0110C0102C0111C0114C0109 C0116C0111 C0115C0112C0101C0099C0105C0102C0105C0099C0097C0116C0105C0111C0110C0115 C0112C0101C0114 C0116C0104C0101 C0116C0101C0114C0109C0115 C0111C0102 C0084C0101C0120C0097C0115 C0073C0110C0115C0116C0114C0117C0109C0101C0110C0116C0115C0115C0116C0097C0110C0100C0097C0114C0100 C0119C0097C0114C0114C0097C0110C0116C0121C0046 C0080C0114C0111C0100C0117C0099C0116C0105C0111C0110 C0112C0114C0111C0099C0101C0115C0115C0105C0110C0103 C0100C0111C0101C0115 C0110C0111C0116 C0110C0101C0099C0101C0115C0115C0097C0114C0105C0108C0121 C0105C0110C0099C0108C0117C0100C0101C0116C0101C0115C0116C0105C0110C0103 C0111C0102 C0097C0108C0108 C0112C0097C0114C0097C0109C0101C0116C0101C0114C0115C0046Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.ntsC0077C0083C0080C0052C0051C0048C0120C0049C0051C0120C0044 C0077C0083C0080C0052C0051C0048C0120C0049C0052C0120C0044 C0077C0083C0080C0052C0051C0048C0120C0049C0052C0120C0049C0077C0073C0088C0069C0068 C0083C0073C0071C0078C0065C0076 C0077C0073C0067C0082C0079C0067C0079C0078C0084C0082C0079C0076C0076C0069C0082SLAS272F JULY 2000 REVISED JUNE 20042 POST OFFICE BOX 655303 DALLAS, TEXAS 75265AVAILABLE OPTIONSPACKAGED DEVICESTAPLASTIC 64-PIN QFP(PM)PLASTIC 64-PIN QFP(PAG)PLASTIC 64-PIN QFN(RTD)40C to 85CMSP430F133IPMMSP430F135IPMMSP430F147IPMMSP430F1471IPMMSP430F148IPMMSP430F1481IPMMSP430F149IPMMSP430F1491IPMMSP430F133IPAGMSP430F135IPAGMSP430F147IPAGMSP430F148IPAGMSP430F149IPAGMSP430F133IRTDMSP430F135IRTDMSP430F147IRTDMSP430F1471IRTDMSP430F148IRTDMSP430F1481IRTDMSP430F149IRTDMSP430F1491IRTDpin designation, MSP430F133, MSP430F13517 18 19P5.4/MCLKP5.3P5.2P5.1P5.0P4.7/TBCLKP4.6P4.5P4.4P4.3P4.2/TB2P4.1/TB1P4.0/TB0P3.7P3.6P3.5/URXD0484746454443424140393837363534332012345678910111213141516DVCCP6.3/A3P6.4/A4P6.5/A5P6.6/A6P6.7/A7VREF+XINXOUTVeREF+VREF/VeREFP1.0/TACLKP1.1/TA0P1.2/TA1P1.3/TA2P1.4/SMCLK21 22 23 24P5.6/ACLKTDO/TDI63 62 61 60 5964 58AV P6.2/A2 P6.1/A1 P6.0/A0 RST/NMI TCK TMSP2.6/ADC12CLKP2.7/TA0P3.0/STE0P3.1/SIMO0P1.7/TA2P2.1/TAINCLKP2.2/CAOUT/TA0P2.3/CA0/TA1P2.4/CA1/TA2P2.5/Rosc56 55 545725 26 27 28 2953 52P1.5/TA0XT2IN XT2OUT51 50 4930 31 32P3.2/SOMI0P3.3/UCLK0 P3.4/UTXD0P5.7/TBOUTHTDI/TCLK P5.5/SMCLKAV DVPM, PAG, RTD PACKAGE(TOP VIEW)P1.6/TA1P2.0/ACLKCC SS SSntsC0077C0083C0080C0052C0051C0048C0120C0049C0051C0120C0044 C0077C0083C0080C0052C0051C0048C0120C0049C0052C0120C0044 C0077C0083C0080C0052C0051C0048C0120C0049C0052C0120C0049C0077C0073C0088C0069C0068 C0083C0073C0071C0078C0065C0076 C0077C0073C0067C0082C0079C0067C0079C0078C0084C0082C0079C0076C0076C0069C0082SLAS272F JULY 2000 REVISED JUNE 20043POST OFFICE BOX 655303 DALLAS, TEXAS 75265pin designation, MSP430F147, MSP430F148, MSP430F14917 18 19P5.4/MCLKP5.3/UCLK1P5.2/SOMI1P5.1/SIMO1P5.0/STE1P4.7/TBCLKP4.6/TB6P4.5/TB5P4.4/TB4P4.3/TB3P4.2/TB2P4.1/TB1P4.0/TB0P3.7/URXD1P3.6/UTXD1P3.5/URXD0484746454443424140393837363534332012345678910111213141516DVCCP6.3/A3P6.4/A4P6.5/A5P6.6/A6P6.7/A7VREF+XINXOUTVeREF+VREF/VeREFP1.0/TACLKP1.1/TA0P1.2/TA1P1.3/TA2P1.4/SMCLK21 22 23 24P5.6/ACLKTDO/TDI63 62 61 60 5964 58AV P6.2/A2 P6.1/A1 P6.0/A0 RST/NMI TCK TMSP2.6/ADC12CLKP2.7/TA0P3.0/STE0P3.1/SIMO0P1.7/TA2P2.1/TAINCLKP2.2/CAOUT/TA0P2.3/CA0/TA1P2.4/CA1/TA2P2.5/Rosc56 55 545725 26 27 28 2953 52P1.5/TA0XT2IN XT2OUT51 50 4930 31 32P3.2/SOMI0P3.3/UCLK0 P3.4/UTXD0P5.7/TBOUTHTDI/TCLK P5.5/SMCLKAV DVPM, PAG, RTD PACKAGE(TOP VIEW)P1.6/TA1P2.0/ACLKCCSSSSntsC0077C0083C0080C0052C0051C0048C0120C0049C0051C0120C0044 C0077C0083C0080C0052C0051C0048C0120C0049C0052C0120C0044 C0077C0083C0080C0052C0051C0048C0120C0049C0052C0120C0049C0077C0073C0088C0069C0068 C0083C0073C0071C0078C0065C0076 C0077C0073C0067C0082C0079C0067C0079C0078C0084C0082C0079C0076C0076C0069C0082SLAS272F JULY 2000 REVISED JUNE 20044 POST OFFICE BOX 655303 DALLAS, TEXAS 75265pin designation, MSP430F1471, MSP430F1481, MSP430F149117 18 19P5.4/MCLKP5.3/UCLK1P5.2/SOMI1P5.1/SIMO1P5.0/STE1P4.7/TBCLKP4.6/TB6P4.5/TB5P4.4/TB4P4.3/TB3P4.2/TB2P4.1/TB1P4.0/TB0P3.7/URXD1P3.6/UTXD1P3.5/URXD0484746454443424140393837363534332012345678910111213141516DVCCP6.3P6.4P6.5P6.6P6.7ReservedXINXOUTDVSSDVSSP1.0/TACLKP1.1/TA0P1.2/TA1P1.3/TA2P1.4/SMCLK21 22 23 24P5.6/ACLKTDO/TDI63 62 61 60 5964 58AV P6.2 P6.1 P6.0 RST/NMI TCK TMSP2.6P2.7/TA0P3.0/STE0P3.1/SIMO0P1.7/TA2P2.1/TAINCLKP2.2/CAOUT/TA0P2.3/CA0/TA1P2.4/CA1/TA2P2.5/Rosc56 55 545725 26 27 28 2953 52P1.5/TA0XT2IN XT2OUT51 50 4930 31 32P3.2/SOMI0P3.3/UCLK0 P3.4/UTXD0P5.7/TBOUTHTDI/TCLK P5.5/SMCLKAV DVPM, RTD PACKAGE(TOP VIEW)P1.6/TA1P2.0/ACLKCCSSSSntsC0077C0083C0080C0052C0051C0048C0120C0049C0051C0120C0044 C0077C0083C0080C0052C0051C0048C0120C0049C0052C0120C0044 C0077C0083C0080C0052C0051C0048C0120C0049C0052C0120C0049C0077C0073C0088C0069C0068 C0083C0073C0071C0078C0065C0076 C0077C0073C0067C0082C0079C0067C0079C0078C0084C0082C0079C0076C0076C0069C0082SLAS272F JULY 2000 REVISED JUNE 20045POST OFFICE BOX 655303 DALLAS, TEXAS 75265functional block diagramsMSP430x13xOscillator ACLKSMCLKCPUIncl. 16 Reg.BusConvMCBXIN XOUT P3 P4P2XT2INXT2OUTTMSTCKMDB, 16 BitMAB, 16 BitMCLK4TDI/TCLKTDO/TDIP5 P6MAB,4 BitDVCCDVSSAVCCAVSSRST/NMISystemClockROSCP116KB Flash8KB Flash512B RAM256B RAMADC1212-Bit8 ChannelsR5Single operands, destination only e.g. CALL R8 PC (TOS), R8 PCRelative jump, un/conditional e.g. JNE Jump-on-equal bit = 0Table 2. Address Mode DescriptionsADDRESS MODE S D SYNTAX EXAMPLE OPERATIONRegister C0070 C0070 MOV Rs,Rd MOV R10,R11 R10 R11Indexed C0070 C0070 MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) M(6+R6)Symbolic (PC relative) C0070 C0070 MOV EDE,TONI M(EDE) M(TONI)Absolute C0070 C0070 MOV &MEM,&TCDAT M(MEM) M(TCDAT)Indirect C0070 MOV Rn,Y(Rm) MOV R10,Tab(R6) M(R10) M(Tab+R6)IndirectautoincrementC0070 MOV Rn+,Rm MOV R10+,R11M(R10) R11R10 + 2 R10Immediate C0070 MOV #X,TONI MOV #45,TONI #45 M(TONI)NOTE: S = source D = destinationntsC0077C0083C0080C0052C0051C0048C0120C0049C0051C0120C0044 C0077C0083C0080C0052C0051C0048C0120C0049C0052C0120C0044 C0077C0083C0080C0052C0051C0048C0120C0049C0052C0120C0049C0077C0073C0088C0069C0068 C0083C0073C0071C0078C0065C0076 C0077C0073C0067C0082C0079C0067C0079C0078C0084C0082C0079C0076C0076C0069C0082SLAS272F JULY 2000 REVISED JUNE 200412 POST OFFICE BOX 655303 DALLAS, TEXAS 75265operating modesThe MSP430 has one active mode and five software selectable low-power modes of operation. An interruptevent can wake up the device from any of the five low-power modes, service the request and restore back tothe low-power mode on return from the interrupt program.The following six operating modes can be configured by software:C0068 Active mode AM; All clocks are activeC0068 Low-power mode 0 (LPM0); CPU is disabledACLK and SMCLK remain active. MCLK is disabledC0068 Low-power mode 1 (LPM1); CPU is disabledACLK and SMCLK remain active. MCLK is disabledDCOs dc-generator is disabled if DCO not used in active modeC0068 Low-power mode 2 (LPM2); CPU is disabledMCLK and SMCLK are disabledDCOs dc-generator remains enabledACLK remains activeC0068 Low-power mode 3 (LPM3); CPU is disabledMCLK and SMCLK are disabledDCOs dc-generator is disabledACLK remains activeC0068 Low-power mode 4 (LPM4); CPU is disabledACLK is disabledMCLK and SMCLK are disabledDCOs dc-generator is disabledCrystal oscillator is stoppedntsC0077C0083C0080C0052C0051C0048C0120C0049C0051C0120C0044 C0077C0083C0080C0052C0051C0048C0120C0049C0052C0120C0044 C0077C0083C0080C0052C0051C0048C0120C0049C0052C0120C0049C0077C0073C0088C0069C0068 C0083C0073C0071C0078C0065C0076 C0077C0073C0067C0082C0079C0067C0079C0078C0084C0082C0079C0076C0076C0069C0082SLAS272F JULY 2000 REVISED JUNE 200413POST OFFICE BOX 655303 DALLAS, TEXAS 75265interrupt vector addressesThe interrupt vectors and the power-up starting address are located in the address range 0FFFFh 0FFE0h.The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITYPower-upExternal ResetWatchdogFlash memoryWDTIFGKEYV(see Note 1)Reset 0FFFEh 15, highestNMIOscillator FaultFlash memory access violationNMIIFG (see Notes 1 & 4)OFIFG (see Notes 1 & 4)ACCVIFG (see Notes 1 & 4)(Non)maskable(Non)maskable(Non)maskable0FFFCh 14Timer_B7 (see Note 5) TBCCR0 CCIFG (see Note 2) Maskable 0FFFAh 13Timer_B7 (see Note 5)TBCCR1 to 6 CCIFGs,TBIFG (see Notes 1 & 2)Maskable 0FFF8h 12Comparator_A CAIFG Maskable 0FFF6h 11Watchdog timer WDTIFG Maskable 0FFF4h 10USART0 receive URXIFG0 Maskable 0FFF2h 9USART0 transmit UTXIFG0 Maskable 0FFF0h 8ADC12 (see Note 6) ADC12IFG (see Notes 1 & 2) Maskable 0FFEEh 7Timer_A3 TACCR0 CCIFG (see Note 2) Maskable 0FFECh 6Timer_A3TACCR1 CCIFG,TACCR2 CCIFG,TAIFG (see Notes 1 & 2)Maskable 0FFEAh 5I/O port P1 (eight flags)P1IFG.0 to P1IFG.7(see Notes 1 & 2)Maskable 0FFE8h 4USART1 receive URXIFG1 Maskable 0FFE6h 3USART1 transmit UTXIFG1 0FFE4h 2I/O port P2 (eight flags)P2IFG.0 to P2IFG.7(see Notes 1 & 2)Maskable 0FFE2h 10FFE0h 0, lowestNOTES: 1. Multiple source flags2. Interrupt flags are located in the module.3. Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.4. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable can not disableit.5. Timer_B7 in MSP430x14x(1) family has 7 CCRs; Timer_B3 in MSP430x13x family has 3 CCRs. In Timer_B3 there are only interruptflags TBCCR0, 1, and 2 CCIFGs and the interrupt-enable bits TBCCTL0, 1, and 2 CCIEs.6. ADC12 is not implemented on the 14x1 devices.ntsC0077C0083C0080C0052C0051C0048C0120C0049C0051C0120C0044 C0077C0083C0080C0052C0051C0048C0120C0049C0052C0120C0044 C0077C0083C0080C0052C0051C0048C0120C0049C0052C0120C0049C0077C0073C0088C0069C0068 C0083C0073C0071C0078C0065C0076 C0077C0073C0067C0082C0079C0067C0079C0078C0084C0082C0079C0076C0076C0069C0082SLAS272F JULY 2000 REVISED JUNE 200414 POST OFFICE BOX 655303 DALLAS, TEXAS 75265special function registersMost interrupt and module-enable bits are collected in the lowest address space. Special-function register bitsnot allocated to a functional purpose are not physically present in the device. This arrangement provides simplesoftware errupt enable 1 and 27654 0UTXIE0 OFIE WDTIE321rw-0 rw-0 rw-0Address0h URXIE0 ACCVIE NMIIErw-0 rw-0 rw-0WDTIE: Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdogtimer is configured in interval timer mode.OFIE: Oscillator-fault-interrupt enableNMIIE: Nonmaskable-interrupt enableACCVIE: Flash access violation interrupt enableURXIE0: USART0: UART and SPI receive-interrupt enableUTXIE0: USART0: UART and SPI transmit-interrupt enable7654 0UTXIE1321rw-0 rw-0Address01h URXIE1URXIE1: USART1: UART and SPI receive-interrupt enableUTXIE1: USART1: UART and SPI transmit-interrupt enableinterrupt flag register 1 and 27654 0UTXIFG0 OFIFG WDTIFG321rw-0 rw-1 rw-(0)Address02h URXIFG0 NMIIFGrw-1 rw-0WDTIFG: Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on VCCpower up or a reset condition at the RST/NMI pin in reset mode.OFIFG: Flag set on oscillator faultNMIIFG: Set via RST/NMI pinURXIFG0: USART0: UART and SPI receive flagUTXIFG0: USART0: UART and SPI transmit flag7654 0UTXIFG1321rw-1 rw-0Address03h URXIFG1URXIFG1: USART1: UART and SPI receive flagUTXIFG1: USART1: UART and SPI transmit flagntsC0077C0083C0080C0052C0051C0048C0120C0049C0051C0120C0044 C0077C0083C0080C0052C0051C0048C0120C0049C0052C0120C0044 C0077C0083C0080C0052C0051C0048C0120C0049C0052C0120C0049C0077C0073C0088C0069C0068 C0083C0073C0071C0078C0065C0076 C0077C0073C0067C0082C0079C0067C0079C0078C0084C0082C0079C0076C0076C0069C0082SLAS272F JULY 2000 REVISED JUNE 200415POST OFFICE BOX 655303 DALLAS, TEXAS 75265module enable registers 1 and 27654 0UTXE0321rw-0 rw-0Address04hURXE0USPIE0URXE0: USART0: UART receive enableUTXE0: USART0: UART transmit enableUSPIE0: USART0: SPI (synchronous peripheral interface) transmit and receive enable7654 0UTXE1321rw-0 rw-0Address05hURXE1USPIE1URXE1: USART1: UART receive enableUTXE1: USART1: UART transmit enableUSPIE1: USART1: SPI (synchronous peripheral interface) transmit and receive enablerw-0:Legend: rw: Bit Can Be Read and WrittenBit Can Be Read and Written. It Is Reset by PUC.SFR Bit Not Present in Devicememory organizationMSP430F133 MSP430F135 MSP430F147MSP430F1471MSP430F148MSP430F1481MSP430F149MSP430F1491MemoryMain: interrupt vectorMain: code memorySizeFlashFlash8KB0FFFFh 0FFE0h0FFFFh 0E000h16KB0FFFFh 0FFE0h0FFFFh 0C000h32KB0FFFFh 0FFE0h0FFFFh 08000h48KB0FFFFh 0FFE0h0FFFFh 04000h60KB0FFFFh 0FFE0h0FFFFh 01100hInformation memory SizeFlash256 Byte010FFh 01000h256 Byte010FFh 01000h256 Byte010FFh 01000h256 Byte010FFh 01000h256 Byte010FFh 01000hBoot memory SizeROM1KB0FFFh 0C00h1KB0FFFh 0C00h1KB0FFFh 0C00h1KB0FFFh 0C00h1KB0FFFh 0C00hRAM Size 256 Byte02FFh 0200h512 Byte03FFh 0200h1KB05FFh 0200h2KB09FFh 0200h2KB09FFh 0200hPeripherals 16-bit8-bit8-bit SFR01FFh 0100h0FFh 010h0Fh 00h01FFh 0100h0FFh 010h0Fh 00h01FFh 0100h0FFh 010h0Fh 00h01FFh 0100h0FFh 010h0Fh 00h01FFh 0100h0FFh 010h0Fh 00hbootstrap loader (BSL)The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serialinterface. Access to the MSP430 memory via the BSL is protected by user-defined password. For completedescription of the features of the BSL and its implementation, see the Application report Features of the MSP430Bootstrap Loader, Literature Number SLAA089.BSL Function PM, PAG & RTD Package PinsData Transmit 13 - P1.1Data Receive 22 - P2.2ntsC0077C0083C0080C0052C0051C0048C0120C0049C0051C0120C0044 C0077C0083C0080C0052C0051C0048C0120C0049C0052C0120C0044 C0077C0083C0080C0052C0051C0048C0120C0049C0052C0120C0049C0077C0073C0088C0069C0068 C0083C0073C0071C0078C0065C0076 C0077C0073C0067C0082C0079C0067C0079C0078C0084C0082C0079C0076C0076C0069C0082SLAS272F JULY 2000 REVISED JUNE 200416 POST OFFICE BOX 655303 DALLAS, TEXAS 75265flash memoryThe flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. TheCPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:C0068 Flash memory has n segments of main memory and two segments of information memory (A and B) of 128bytes each. Each segment in
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