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毕业设计（论文）外文资料翻译 系别： 电气工程系 专业： 电气工程及其自动化 班级： 姓名： 学号： 36 号 外文出处： ATMEL公司技术资料 （用外文写） ATMEL Corporation technical data 附 件： 1、外文原文； 2、外文资料翻译译文。 指导教师评语： 签字： 年 月 日 注：请将该封面与附件装订成册。 nts1、 外文原文（复印件） AT89C51 Description ATMEL The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash Programmable and Erasable Read Only Memory (PEROM). The device is manufactured using Atmel s high density nonvolatile memory technology and is compatible with the industry standard MCS-51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventionalnonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications. The AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset. 1. principal characteristics： nts Is compatible with MCS-51 The 4K byte programmable glitters the memory Life: 1,000 writes/scratches the circulation Retention of data time: 10 years Entire static work: 0Hz-24Hz Three levels of program memories locking 128*8 position interior RAM 32 programmable I/O line Two 16 timers/counters 5 interrupt sources Programmable serial channel The low power loss leaves unused and falls the electricitypattern Internal oscillator and clock electric circuit 2. base pins explained that： VCC: Supply voltage. GND: Earth. Port 0 Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs. Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pullups are required during program verification. Port 1： Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, the Port 1 pins when under is pulled by exterior for the low level, outputcurrent, this is because in the interior pulls reason. When FLASHprogramming and verification, Port 1 achievement eighth bit addressreceive. ntsPort 2: The Port 2 is in an interior pulls the resistance 8bit I/O Port, the Port 2 buffer may receive, outputs 4TTL gate electric current, when the Port 2 is written 1, its basepin is pulled by the interior in the resistance to pull high, also asinput. And therefore took when input, the Port 2 pins is pulledlowly by exterior, output current. This is because in the interiorpulls reason. The Port 2 when uses in exterior program memory or 16bit addresses exterior data-carrier storage carries on the deposit andwithdrawal, Port 2 output address high eight. When produces theaddress 1, it uses in the interior to pull the superiority, whencarries on read-write to the exterior eight bit addresses data-carrierstorage, the Port 2 outputs its special function register thecontent. Port 2 when FLASH programming and verification receives thehigh eight bit address signal and the control signal. Port 3： Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, After the Port 3 reads in 1, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups. The Port 3 also may take AT89C51 some special function Port, thefollowing table shows: The mouth base pin prepares chooses the function P3.0 RXD (serial input port) P3.1 TXD (serial output port) P3.2 /INT0 (external interrupt 0) P3.3 /INT1 (external interrupt 1) P3.4 T0 (timer 0 external input) P3.5 T1 (timer 1 external input) P3.6 /WR (external data memory write strobe) P3.7 /RD (external data memory read strobe) Port 3 also receives some control signals for Flash programming and verification. RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. ALE/PROG ntsAddress Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode. /PSEN Program Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. /EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at （ 0000H up to FFFFH） . Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. /EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier. 3. Oscillator Characteristics: XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. XTAL2 should be left unconnected There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed. nts4. Chip Erase: The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “ 1” s. The chip erase operation must be executed before the code memory can be re-programmed. In addition, AT89C51 is equipped with the stable state logic, may inlower to the zero frequency rate condition under the static logic,supports two kind of software to be possible to elect to fall theelectricity pattern. In leaves unused under the pattern, CPU knockoff. But RAM, the timer, the counter, strung together the mouth andthe interruption system still is working. In falls under theelectricity pattern, preserves RAM the content and to freeze theoscillator, forbids to use other chip functions, repositions until thenext hardware. Very begins studies 51 monolithic integrated circuits Network friend can havesuch question: What is AT89S51? In on the book and the network coursemay all be 8,051, 89C51 and so on! Had not heard has 89S51? ! Here, the beginner wants to clarify the monolithic integrated circuitactual use aspect a product concept, the MCS-51 monolithic integratedcircuit was American INTE Corporation the product which promoted in1980, the typical product had 8031 (interior not to have programmemory, actually used aspect already by market elimination), 8,051(chip is used HMOS, power loss was 630mW, was 89C51 5 times, actuallyused aspect already by market elimination) and 8,751 and so on thegeneral product, one until now, the MCS-51 essence series compatiblemonolithic integrated circuit still was (89C51 which the applicationmainstream product for instance present popular 89S51, alreadysuspended production and so on), Various universities and thevocational school training teaching material still carried on therationale study with the MCS-51 monolithic integrated circuit as therepresentative. Some literature even also 8,051 make a general reference the MCS-51series monolithic integrated circuit, 8,051 is the early most typicalrepresentative works, because the MCS-51 monolithic integrated circuitinfluence is extremely profound, many companies have all promoted thecompatible series monolithic integrated circuit, is said the MCS-51essence already became 8 monolithic integrated circuits in fact thestandards. Other companies 51 monolithic integrated circuits products all areand the MCS-51 essence compatible product but by. Similar section ofprocedures, ntsthe result which moves in on each monolithic integratedcircuit factory hardware all are same, like ATMEL 89C51 (alreadysuspended production), 89S51, PHILIPS (the Filley waters edge), withWINBOND (the Chinese nation) and so on, we often said alreadyproduction suspension 89C51 to refer was ATMEL Corporations AT89C51monolithic integrated circuit, simultaneously was strengthened manycharacteristics in the original foundation, what if the clock, wasmore outstanding was (program memory content at least may rewrite1,000 time) the memory by Flash to take brings original ROM(disposable to read in), the AT89C51 performance was opposite to 8051already was extremely superior. But in the market aspect, 89C51 received the PIC monolithic integratedcircuit camps challenge, the 89C51 most fatal flaw has lain in doesnot support ISP (on-line renewal procedure) the function, had to addon the ISP function and so on the new function to be able better tocontinue MCS-51 the legend. 89S51 is substitutes for 89C51 under suchbackground, 89S51 at present already has become now in the practicalapplication market the new pet, at present the company alreadysuspended production as market share first Atmel AT89C51, will useAT89S51 to replace. 89S51 made the improvement in the craft, 89S51 hasused 0.35 new craft, cost reduction, moreover promoted the function,to increase the competitive ability. Under 89SXX may like compatible89CXX and so on 51 series chips. At the same time, Atmel no longeraccepts 89CXX the order form, everybody 89C51 which saw in the marketactually all is the Atmel earlier period production great quantitystock but by. 89S51 is opposite the new function which increases to 89C51 includes: - New increase very multi-purpose, the performance had a biggerpromotion, the price actually basic invariable, even is lower than89C51! - The ISP on-line programming function, this function superioritylies in the rewriting monolithic integrated circuit memory theprocedure not to need to strip the chip from the working conditions.Is a formidable Yi Yong function. - The operating frequency is 33MHz, everybody knew 89C51 the limitoperating frequency only has 24M, is said S51 has the higher operatingfrequency, thus had the quicker computation speed. - Has the duplex UART serial channel. - The internal integration WDT timer, no longer needs to likeoutside 89C51 such to meet WDT the timer unit electric ntscircuit. -Double multiple according to display. - Power source closure marking. - The brand-new encryption algorithm, this causes regarding the 89S51decipher to become is impossible, the procedure secrecy greatlystrengthens, like this may the effective protection intellectualproperty rights not encroach. - Compatible aspect: To under completely compatible 51 completecharacters series product. For instance 8,051, 89C51 and so on earlyMCS-51 compatible product. In other words on all textbooks, networkcourse procedure (no matter in textbook uses monolithic integratedcircuit is 8,051 or 89C51 or MCS-51 and so on), equally may move asusual on 89S51, this is so-called is compatible to under. nts2、外文资料翻译译文 AT89C51 简介 ATMEL AT89C51 是一种带 4K 字节闪烁可编程可擦除只读存储器（ FPEROM）的低电压，高性能 CMOS8 位微处理器，俗称单片机。该器件采用 ATMEL 高密度非易失存储器制造技术制造，与工业标准的 MCS-51 指令集和输出管脚相兼容。由于将多功能 8 位CPU 和闪烁存储器组合在单个芯片中， ATMEL 的 AT89C51 是一种高效微控制器，为很多嵌入式控制系统提供了一种灵活性高且价廉的方案。 功能特性描述： AT89C51 提供以下标准功能： 4K 字节 Flash 闪存字节， 128 字节 ROM， 32 个 I/O口线，两个 16 位定时 /计数器，一个 5 向量两级中断结构，一个全双工串行通讯口，片内振荡器及时钟电路。另外， AT89C51 可降至 0Hz 的静态逻辑操作，并支持两种软件可选 的节电工作模式。空闲方式停止 CPU 的工作，但允许 RAM，定时 /计数器，串行通讯口及中断系统继续工作。掉电方式保存 RAM 中的内容，但振荡器停止工作并禁止其他所有部件工作直到下一个硬件复位。 1主要特性： 与 MCS-51 兼容 4K 字节可编程闪烁存储器 寿命： 1000 写 /擦循环 数据保留时间： 10 年 nts全静态工作： 0Hz-24Hz 三级程序存储器锁定 128*8 位内部 RAM 32 可编程 I/O 线 两个 16 位定时器 /计数器 5 个中断源 可编程串行通道 低功耗的闲置和掉电模式 片内振荡器和时钟电路 2管 脚说明 ： VCC：供电电压。 GND：接地。 P0 口： P0 口为一个 8 位漏级开路双向 I/O 口，每脚可吸收 8TTL 门电流。当P1 口的管脚第一次写 1 时，被定义为高阻输入。 P0 能够用于外部程序数据存储器，它可以被定义为数据 /地址的第八位。在 FIASH 编程时， P0 口作为原码输入口，当FIASH 进行校验时， P0 输出原码，此时 P0 外部必须被拉高。 P1 口： P1 口是一个内部提供上拉电阻的 8 位双向 I/O 口， P1 口缓冲器能接收输出 4TTL 门电流。 P1 口管脚写入 1 后，被内部上拉为高，可用作输入， P1 口被外部下拉为低电平时，将输出电流，这是由于内部上拉的缘故。在 FLASH 编程和校验时， P1 口作为第八位地址接收。 P2 口： P2 口为一个内部上拉电阻的 8 位双向 I/O 口， P2 口缓冲器可接收，输出 4 个 TTL 门电流，当 P2 口被写 “1” 时，其管脚被内部上拉电阻拉高，且作为输入。并因此作为输入时， P2 口的管脚被外部拉低，将输出电流。这是由于内部上拉的缘故。 P2 口当用于外部程序存储器或 16 位地址外部数据存储器进行存取时，P2 口输出地址的高八位。在给出地址 “1” 时，它利用内部上拉优势，当对外部八位地址数据存储 器进行读写时， P2 口输出其特殊功能寄存器的内容。 P2 口在 FLASH编程和校验时接收高八位地址信号和控制信号。 P3 口： P3 口管脚是 8 个带内部上拉电阻的双向 I/O 口，可接收输出 4 个 TTL门电流。当 P3 口写入 “1” 后，它们被内部上拉为高电平，并用作输入。作为输入，由于外部下拉为低电平， P3 口将输出电流（ ILL）这是由于上拉的缘故。 P3 口也可作为 AT89C51 的一些特殊功能口，如下表所示： 口管脚 备选功能 P3.0 RXD（串行输入口） P3.1 TXD（串行输出口） P3.2 /INT0（外部中断 0） P3.3 /INT1（外部中断 1） ntsP3.4 T0（记时器 0 外部输入） P3.5 T1（记时器 1 外部输入） P3.6 /WR（外部数据存储器写选通） P3.7 /RD（外部数据存储器读选通） P3 口同时为闪烁编程和编程校验接收一些控制信号。 RST：复位输入。当振荡器复位器件时，要保持 RST 脚两个机器周期的高电平时间。 ALE/PROG：当访问外部存储器时，地址锁存允许的输出电平用于锁存地址的地位字节。在 FLASH 编程期间，此引脚用于输入编程脉冲。在平时， ALE 端以不变的频率周期输出正脉冲信号， 此频率为振荡器频率的 1/6。因此它可用作对外部输出的脉冲或用于定时目的。然而要注意的是：每当用作外部数据存储器时，将跳过一个 ALE脉冲。如想禁止 ALE 的输出可在 SFR8EH 地址上置 0。此时， ALE 只有在执行 MOVX，MOVC 指令是 ALE 才起作用。另外，该引脚被略微拉高。如果微处理器在外部执行状态 ALE 禁止，置位无效。 /PSEN：外部程序存储器的选通信号。在由外部程序存储器取指期间，每个机器周期两次 /PSEN 有效。但在访问外部数据存储器时，这两次有效的 /PSEN 信号将不出现。 /EA/VPP：当 /EA 保持低电平时，则在此期间外部程序存储器（ 0000H-FFFFH），不管是否有内部程序存储器。注意加密方式 1 时， /EA 将内部锁定为 RESET；当 /EA端保持高电平时，此间内部程序存储器。在 FLASH 编程期间，此引脚也用于施加 12V编程电源（ VPP）。 XTAL1：反向振荡放大器的输入及内部时钟工作电路的输入。 XTAL2：来自反向振荡器的输出。 3振荡器特性： XTAL1 和 XTAL2 分别为反向放大器的输入和输出。该反向放大器可以配置为片内振荡器。石晶振荡和陶瓷振荡均可采用。如采 用外部时钟源驱动器件， XTAL2 应不接。有余输入至内部时钟信号要通过一个二分频触发器，因此对外部时钟信号的脉宽无任何要求，但必须保证脉冲的高低电平要求的宽度。 4芯片擦除： 整个 PEROM 阵列和三个锁定位的电擦除可通过正确的控制信号组合，并保持 ALE 管脚处于低电平 10ms 来完成。在芯片擦操作中，代码阵列全被写 “1” 且在任何非空存储字节被重复编程以前，该操作必须被执行。 此外， AT89C51 设有稳态逻辑，可以在低到零频率的条件下静