基于AT89S52单片机和DS1302的电子万年历设计资料
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基于AT89S52单片机和DS1302的电子万年历设计资料,毕业设计
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天津工程师范学院 03 级学生 毕业设计 中期报告 系别 自动化系 班级 自 0302 学生 姓名 许宁 指导 教师 赵学玲 课题名称： 电子万年历设计 简述开题以来所做的具体工作 、 取得的进展 及 下一步主要工作 ： 2006-2007 学年 （ 1）第一学期（ 11.15-12.15） 通过收集整理资料，认真阅读资料，对电子万年历设计有个整体的了解。 然后设计方案， 对所设计的 方案 进行分析论证，记下各 方案 的优缺点 ， 选择比较可取的方案 而且电路所用到的器件必须是性价比较高 、 在市场上比较容易买到的。 方案选择完毕后，针对该方案看懂电 路的原理， 分析整个系统的流程 并 用框图表示出来， 构造出大体框架。然后再 分析每个模块电路的具体作用以及可能出现的问题 。 根据方案选择出元器件后， 查找各器件的管 脚 图及其用法，根据公式计算所用到器件的型号及大小，列元件清单，购买器件 。 （ 2）第二学期（ 4.5-4.20、 4.20-5.10） 第一阶段：根据 上学期 整理的资料开始焊接 电路 ，构思整个系统的信号流程和布局工作 。对各个模块进行编程，不断修改程序以达到预期要实现的功能。 第二阶段：完成所有模块的 编程及 调试任务，接着统调，在统调的过程中注意电源的正负极以及各模块间的信号是否接好、是否共地、芯片是否装反等 问题 。 （ 3）取得的进展 各模块电路已基本实现，获得的指标 与预期的 差距不大 。 （ 4）下一步的 主要 工作 尽力解决统调过程中出现的问题，分析产生 各 种现象的原因。 记下调试过程中各个指标。 整理资料，准备着手写论文。 回想设计的整个过程，准备答辩 。 学生签字： 年 月 日 nts指导教师的建议与要求： 指导教师签字 ： 年 月 日 注： 本表格同毕业设计（论文）一同装订成册，由所在单位归档保存。 nts天津工程师范学院 毕业设计 任务书 2006 年 11 月 4 日 题 目 （包括副标题） 电子万年历设计 教师姓名 赵学玲 系 别 自动化工程 系 职 称 讲师 学生姓名 许宁 班 级 自 0302 班 学 号 15 课题成果形式 论文 设计说明书 实物 软件 其它 1毕业设计（论文）课题任务的内容和要求（如原始数据、技术要求、工作要求等）： 1、毕业设 计的主要内容： 1） 设计并制作电子万年历 2） 完成相关的技术文档和毕业设计论文 2、毕业设计的主要技术指标 1） 显示阳历 年、月、日、时、分、秒、星期 及 阴历 年、月、日，能标明是否 闰 月 2） 用液晶进行显示，用按键进行调整 3） 实现闹铃功能 3、毕业设计的基本要求： 1） 完成电子系统的方案设计，技术调试，硬件实现 2） 完成 技术指标中的各项要求 为优秀 2毕业设计（论文）工作进度计划： 周 次 工作内容 第一周、第二周 第三周，第四周 第五周，第六周 第七、八、九周 第十、十一、十二周 查找资料、设计电路 方案论证、购买元件 制作电路、程序设计 系统制作、整体调试 总结论文、准备答辩 教研室（学科组）主任签字： nts1、毕业设计的主要内容：1） 设计并制作电子万年历2） 完成相关的技术文档和毕业设计论文2、毕业设计的主要技术指标1） 显示阳历年、月、日、时、分、秒、星期及阴历年、月、日，能标明是否闰月2） 用液晶进行显示，用按键进行调整3） 实现闹铃功能3、毕业设计的基本要求：1） 完成电子系统的方案设计，技术调试，硬件实现完成技术指标中的各项要求为优秀nts 1 英文翻译 Overview The 8051 family of micro controllers is based on an architecture which is highly optimized for embedded control systems. It is used in a wide variety of applications from military equipment to automobiles to the keyboard on your PC. Second only to the Motorola 68HC11 in eight bit processors sales, the 8051 family of microcontrollers is available in a wide array of variations from manufacturers such as Intel, Philips, and Siemens. These manufacturers have added numerous features and peripherals to the 8051 such as I2C interfaces, analog to digital converters, watchdog timers, and pulse width modulated outputs. Variations of the 8051 with clock speeds up to 40MHz and voltage requirements down to 1.5 volts are available. This wide range of parts based on one core makes the 8051 family an excellent choice as the base architecture for a companys entire line of products since it can perform many functions and developers will only have to learn this one platform. The basic architecture consists of the following features: 1 2 which can be individually accessed 3 4 5 6 7 paces for DATA and CODE memory One 8051 processor cycle consists of twelve oscillator periods. Each of the twelve oscillator periods is used for a special function by the 8051 core such as op code fetches and samples of the interrupt daisy chain for pending interrupts. The time required for any 8051 instruction can be computed by dividing the clock frequency by 12, inverting that result and multiplying it by the number of processor cycles required by the instruction in question. Therefore, if you have a system which is using an 11.059MHz clock, you can compute the number of instructions per second by dividing this value by 12. This gives an instruction frequency of 921583 instructions per second. Inverting this will provide the amount of time taken by each instruction cycle (1.085 microseconds). nts 2 Memory Organization The 8051 architecture provides the user with three physically distinct memory spaces which can be seen in Figure A - 1. Each memory space consists of contiguous addresses from 0 to the maximum size, in bytes, of the memory space. Address overlaps are resolved by utilizing instructions which refer specifically to a given address space. The three memory spaces function as described below. The CODE Space The first memory space is the CODE segment in which the executable program resides. This segment can be up to 64K (since it is addressed by 16 address lines) . The processor treats this segment as read only and will generate signals appropriate to access a memory device such as an EPROM. However, this does not mean that the CODE segment must be implemented using an EPROM. Many embedded systems these days are using EEPROM which allows the memory to be overwritten either by the 8051 itself or by an external device. This makes upgrades to the product easy to do since new software can be downloaded into the EEPROM rather than having to disassemble it and install a new EPROM. Additionally, battery backed SRAM can be used in place of an EPROM. This method offers the same capability to upload new software to the unit as does an EEPROM, and does not have any sort of read/write cycle limitations such as an EEPROM has. However, when the battery supplying the RAM eventually dies, so does the software in it. Using an SRAM in place of an EPROM in development systems allows for rapid downloading of new code into the target system. When this can be done, it helps avoid the cycle of programming/testing/erasing with EPROM, and can also help avoid hassles over an in circuit emulator which is usually a rare commodity. In addition to executable code, it is common practice with the 8051 to store fixed lookup tables in the CODE segment. To facilitate this, the 8051 provides instructions which allow rapid access to tables via the data pointer (DPTR) or the program counter with an offset into the table optionally provided by the accumulator. This means that oftentimes, a tables base address can be loaded in DPTR and the element of the table to access can be held in the accumulator. The addition is performed by the 8051 during the execution of the instruction which can save many cycles depending on the situation. An example of this is shown later in this chapter in. The DATA Space nts 3 The second memory space is the 128 bytes of internal RAM on the 8051, or the first 128 bytes of internal RAM on the 8052. This segment is typically referred to as the DATA segment. The RAM locations in this segment are accessed in one or two cycles depending on the instruction. This access time is much quicker than access to the XDATA segment because memory is addressed directly rather than via a memory pointer such as DPTR which must first be initialized. Therefore, frequently used variables and temporary scratch variables are usually assigned to the DATA segment. Such allocation must be done with care, however, due to the limited amount of memory in this segment. Variables stored in the DATA segment can also be accessed indirectly via R0 or R1. The register being used as the memory pointer must contain the address of the byte to be retrieved or altered. These instructions can take one or two processor cycles depending on the source/destination data byte. The DATA segment contains two smaller segments of interest. The first sub segment consists of the four sets of register banks which compose the first 32 bytes of RAM. The 8051 can use any of these four groups of eight bytes as its default register bank. The selection of register banks is changeable at any time via the RS1 and the RS0 bits in the Processor Status Word (PSW). These two bits combine into a number from 0 to 3 (with RS1 being the most significant bit) which indicates the register bank to be used. Register bank switching allows not only for quick parameter passing, but also opens the door for simplifying task switching on the 8051. The second sub-segment in the DATA space is a bit addressable segment in which each bit can be individually accessed. This segment is referred to as the BDATA segment. The bit addressable segment consists of 16 bytes (128 bits) above the four register banks in memory. The 8051 contains several single bit instructions which are often very useful in control applications and aid in replacing external combinatorial logic with software in the 8051 thus reducing parts count on the target system. It should be noted that these 16 bytes can also be accessed on a byte-wide basis just like any other byte in the DATA space. Special Function Registers Control registers for the interrupt system and the peripherals on the 8051 are contained in internal RAM at locations 80 hex and above. These registers are referred to as special function Registers (or SFR for short). Many of them are bit addressable. The bits in the bit addressable SFR can either be accessed by name, index or bit address. Thus, you can refer nts 4 to the EA bit of the Interrupt Enable SFR as EA, IE.7, or 0AFH. The SFR control things such as the function of the timer/counters, the UART, and the interrupt sources as well as their priorities. These registers are accessed by the same set of instructions as the bytes and bits in the DATA segment. A memory map of the SFRS indicating the registers. The IDATA Space Certain 8051 family members such as the 8052 contain an additional 128 bytes of internal RAM which reside at RAM locations 80 hex and above. This segment of RAM is typically referred to as the IDATA segment. Because the IDATA addresses and the SFR addresses overlap, address conflicts between IDATA RAM and the SFRs are resolved by the type of memory access being performed, since the IDATA segment can only be accessed via indirect addressing modes. The XDATA Space. The final 8051 memory space is 64K in length and is addressed by the same 16 address lines as the CODE segment. This space is typically referred to as the external data memory space (or the XDATA segment for short). This segment usually consists of some sort of RAM (usually an SRAM) and the I/O devices or external peripherals to which the 8051 must interface via its bus. Read or write operations to this segment take a minimum of two processor cycles and are performed using either DPTR, R0, or R1. In the case of DPTR, it usually takes two processor cycles or more to load the desired address in addition to the two cycles required to perform the read or write operation. Similarly, loading R0 or R1 will take minimum of one cycle in addition to the two cycles imposed by the memory access itself. Therefore, it is easy to see that a typical operation with the XDATA segment will, in general, take a minimum of three processor cycles. Because of this, the DATA segment is a very attractive place to store any frequently. It is possible to fill this segment entirely with 64K of RAM if the 8051 does not need to perform any I/O with devices in its bus or if the designer wishes to cycle the RAM on and off when I/O devices are being accessed via the bus. Methods for performing this technique will be discussed in chapters later in this book. On-Board Timer/Counters The standard 8051 has two timer/counters (other 8051 family members have varying amounts), each of which is a full 16 bits. Each timer/counter can be function as a free nts 5 running timer (in which case they count processor cycles) or can be used to count falling edges on the signal applied to their respective I/O pin (either T0 or T1). When used as a counter, the input signal must have a frequency equal to or lower than the instruction cycle frequency divided by 2 (ie: the oscillator frequency /24) since the incoming signal is sampled every instruction cycle, and the counter is incremented only when a 1 to 0 transition is detected (which will require two samples). If desired, the timer/counters can force a software interrupt when they overflow. The TCON (Timer Control) SFR is used to start or stop the timers as well as hold the overflow flags of the timers. The TCON SFR is detailed below in Table A - 7. The timer/counters are started or stopped by changing the timer run bits (TR0 and TR1) in TCON. The software can freeze the operation of either timer as well as restart the timers simply by changing the Trx bit in the TCON register. The TCON register also contains the overflow flags for the timers. When the timers overflow, they set their respective flag (TF0 or TF1) in this register. When the processor detects a 0 to 1 transition in the flag, an interrupt occurs if it is enabled. It should be noted that the software can set or clear this flag at any time. Therefore, an interrupt can be prevented as well as forced by the software. Microcomputer interface A microcomputer interface converts information between two forms .Outside the microcomputer the information handled by an electronic system exists as a physical signals, but within the program , it is represented numerically . The function of any interface can be broken down into a number of operations which modify the data in some way ,so than the process of conversion between the external and internal forms is carried out in a number or steps. This can be illustrated by means of an example such as than or Fig 10-1,which shows an interface between a microcomputer and a transducer producing a continuously variable analog signal. transducers often produce very small out requiring amply frication, or they may generate signals .in a form that needs to be converted again before being handled by the rest of the system .For example ,many transducers these variable resistance which must be converted to a voltage by a special circuit. This process of converting the transducer output into a voltage4 signal which can be connected to the rest of the system is called signal conditioning .In the example of Figure 10-1, the sigma conditioning section translates the range lf voltage or current signals from the transducer to one which can be converted to digital forum by an analog-to-digital converter. nts 6 Fig 10-1 output Interface Analog-to-digital digital converter (ADC) is used to convert a continuously variable signal to a corresponding digital forum which can take any one of a fixed number of possible binary values .If the output lf the transducer does not vary continuously ,no ADC is necessary. In this case the signal conditioning section must convert the incoming signal to a form which can be connected directly to the next part of the interface, the input/output section lf the microcomputer itself. The I/O section converts digital “on/off” voltage signals to a form which can be presented to the processor via the via the system buses .Here the state of each input line whether it is “on” or “off”, is indicated by a corresponding “1” or “0”.In the line inputs which have been converted to digital form, the patterns of ones and zeros in the internal representation will form binary numbers corresponding to the quantity being converted. The “raw” numbers from the interface are limited by the design of the interface circuitry and they often require linearization and scaling to produce values suitable for use in the main program. For example ,the interface night be rise to convert temperatures in the range 20 to +50 dress, buy the numbers produced by an 8-bit converter will lie in the range 0 to 255.Obviously it is easier , the programmers point of view to deal directly with temperature rather than to work out the equivalent of any given temperature in terms of the numbers produced by the ADC .Every time the interface is used to read a transducer ,the same operations must be carried out to convert the input number into a more convenient form .Addtionarly ,the operation of some interfaces requires control signals to be passed between the microcomputer and components of the interface ,For these reasons it is normal to use a subroutine to loot after the detailed operation of the interface and carry out any scaling and /or linearization which might be needed. Output interfaces take a similar form (Fig.10-2), the biopic difference being that here the flow of information is in the opposite direction; it is passed from the program to the outside world. In this case the program may call an output subroutine which supervises the operation of the interface and performs the scaling numbers which may be needed for a digital-to-analog converter (DAC) .This subroutine passes information in term to an out Transducer Signal conditioning A DC I/O Section nts 7 analog form using a DAC .Finally the signal is conditioned (usually amplified ) to a form suitable for operating an actuator. Fig 10-2 output Interface The signals used within microcomputer circuits are almost always too small to be connected directly to the “outside world ”and some king of interface must be used to translate them to a more appropriate form .The design of section of interface circuits is one of the most important tasks facing the engineer wishing to apply microcomputers. We have seen that in microcomputers information is represented as discrete patterns of bits ;this digital form is most useful when the microcomputer is to be connected to equipment which can only be switched on or off, where each bit might represent the state of a switch or actuator. Care must be taken when connecting logic circuits to ensure that their logic levels and current ratings are compatible .The output voltages produced by a logic circuit are normally specified in terms of worst case values when sourcing or sinking the maximum rated currents .Thus VOH is the guaranteed minimum “high ” voltage when sourcing the maximum rate “high” output current IOH ,while VOL is the guaranteed “low” output voltage when sinking the maximum rated “low ”output current IOL .There are corresponding specifications for logic inputs which specify the minimum input voltage which will be recognized as a logic “high” state VIH ,and the maximum input voltage which will be regarded as a logic “low” state VIL. For input interface, perhaps the main problem facing the designer is that of electrical nois e .Small noise signal may cause the system to malfunction, while larger amounts of moist can permanently damage it. The designer must be aware of these dangers from the outset. There are many methods to protect interface circuits and microcomputer from various kinds of noise .Following is some examples: 1. Input and output electrical isolating between the microcomputer system and external devices using an opt-isolator or a transformer. 2. Removing high frequency noise pulses by a low-pea filter and Schmitt-trigger. 3. Protecting against excessive input voltages using a pair of diodes to power nts 8 supply reversibly biased in normal direction. For output interface, parameters VOH, VOL, IOH and IOL of a logic device are usually much to low to allow loads to be connected directly, and in practice an external circuit must be connected to amplify the current and voltage to drive a load. Although several types of semiconductor devices are now available for controlling DC and AC powers up to many kilowatts, there are two basic ways in which a switch can be connected to a load to control it : series connection and shunt connection as shown in Figure 10-3. Fig 10-3 Series and Shunt Connection With series connection, the switch allows current to flow through the load when closed, while with shunt connection closing the switch allows current to bypass the load. Both connections are useful in low-power circuits, but only the series connection can be used in high-power circuits because of the power wasted in the series resistor R. THE INTRODUCTION OF AT89C52 Features of the AT89C52 Compatible with MCS-51 Products 8K Bytes of
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