键盘部分VHDL代码.doc

键盘部分VHDL代码是这样的- KeyboardLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY keyboard ISPORT( CLK_1K: IN STD_LOGIC; -系统原始时钟脉冲(1KHz) KEY_IN: IN STD_LOGIC_VECTOR(3 DOWNTO 0); -按键输入 CLK_SCAN,CC: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -键盘扫描输出 KBY_OUT: OUT STD_LOGIC_VECTOR(9 DOWNTO 0); -键盘数据输出END ENTITY KEYBOARD;ARCHITECTURE ART OF KEYBOARD ISCOMPONENT DEBOUNCING ISPORT( D_IN,CLK:IN STD_LOGIC; D_OUT: OUT STD_LOGIC);END COMPONENT DEBOUNCING; -其中是消抖电路SIGNAL CLK:STD_LOGIC; -电路工作时钟脉冲SIGNAL C_KEYBOARD:STD_LOGIC_VECTOR(1 DOWNTO 0); -键扫信号“00-01-10-11”寄存器SIGNAL C_DEBOUNCE:STD_LOGIC; -去抖动电路时钟SIGNAL C:STD_LOGIC_VECTOR(3 DOWNTO 0); -键盘输入去抖动后的寄存器SIGNAL N,F:STD_LOGIC_VECTOR(3 DOWNTO 0); -数字、功能按键译码值的寄存器SIGNAL FN,FF: STD_LOGIC; -数字、功能按键标志值数字、功能按键SIGNAL SEL: STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINKBY_OUT = FF & FN & F & N;-扫描信号发生器COUNTER: BLOCK IS SIGNAL Q: STD_LOGIC_VECTOR(9 DOWNTO 0); SIGNAL SEL: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(CLK_1K,Q) BEGIN IF(CLK_1KEVENT AND CLK_1K=1) THEN Q = Q + 1; END IF; C_DEBOUNCE = Q(2); C_KEYBOARD = Q(9 DOWNTO 8); CLK = Q(0); END PROCESS; SEL = 1110 WHEN C_KEYBOARD = 0 ELSE 1101 WHEN C_KEYBOARD = 1 ELSE 1011 WHEN C_KEYBOARD = 2 ELSE 0111 WHEN C_KEYBOARD = 3 ELSE 1111 ; CLK_SCAN NOT KEY_IN(0), CLK = C_DEBOUNCE, D_OUT = C(0);U2: DEBOUNCING PORT MAP (D_IN = NOT KEY_IN(1), CLK = C_DEBOUNCE, D_OUT = C(1);U3: DEBOUNCING PORT MAP (D_IN = NOT KEY_IN(2), CLK = C_DEBOUNCE, D_OUT = C(2);U4: DEBOUNCING PORT MAP (D_IN = NOT KEY_IN(3), CLK = C_DEBOUNCE, D_OUT = C(3);CC = C;END BLOCK DEBOUNUING; -键盘译码KEY_DECODER: BLOCKSIGNAL Z: STD_LOGIC_VECTOR(5 DOWNTO 0); -按键位置BEGINPROCESS(CLK,C_KEYBOARD,C)BEGINZ N N N N N N N N N N N F F F F F F F = 1111; END CASE;END IF;END PROCESS; FN = NOT(N(3) AND N(2) AND N(1) AND N(0); FF = NOT(F(3) AND F(2) AND F(1) AND F(0);END BLOCK KEY_DECODER;END ARCHITECTURE ART;问题如下(使用的芯片是altera公司的max7000s系列芯片，芯片型号为7128slc84)：我的程序中,clk3是按键的输入信号 clk2是一个标准的200赫兹输入信号,希望利用这个来计20ms的延时时间 我希望的判断方法： 当接受到第一个clk3=1时，延时20ms，延时以后，再判断此时clk3是否仍为1 如果此时clk3为1，则说明这个脉冲是真脉冲，加counter9 如果此时clk3不为1，则说明这个脉冲只是按键的毛刺，此时延时用的计数器清零，等待下一个clk3=1，再触发延时用的计数器。关于这部分的程序如下:architecture rtl of clk_div728 is signal read_key:integer :=0; signal timer_en:integer :=0 ; signal counter4:integer:=0; p2: process(clk2) variable counter25:integer range 0 to 63; begin if (clk2event and clk2=1 and timer_en=1) then counter4=counter4+1; elsif (clk2event and clk2=1 and timer_en=0) then counter4=0;else counter4=counter4;end if; end process p2;-read_key=1 when counter4=4 else 0;-p3:process(clk3)beginif (counter4=4) then timer_en=0;elsif (counter4/=4 and clk3event and clk3=1) then timer_en=1;else timer_en=timer_en;end if;end process p3;-p4: process(read_key) variable counter9:integer range 0 to 16; begin if (read_keyevent and