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tx053电力载波通信电路,机械毕业设计

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电力载波通信电路 专业： 通信工程 学号： 1002578 姓名： 欧文凯 指导教师： 陈忠辉 中文摘要 电力线通信是继电信 ,电话 ,无线通讯 ,卫星通讯之后的又一通信网 电力线载波通信就是以电力网作为信道 ,实现数据传递和信息交换 因为电源线路是每个家庭最为普通也是覆盖最为宽广的一种物理媒介 ,所以利用电力线实现数 据通信有着很大的经济效益和应用前景 由于低压范围内电力线网络的非规则性 ,传输距离的随意性 ,以及电力线上负载变化的多样性 ,使得干扰问题成为制约低压电力线载波通信发展和普及的主要障碍 本课题在对低压电力线的传输特性和接收调制技术进行分析的基础上 ,将对电力载波通信的接收和发送电路进行设计研究 ,主要研究内容如下 : (1)对低压电力线的传输特性进行分析 ,在低压电力线上进行信号的传输 ,突出表现在工作环境恶劣 ,线路阻抗小 ,信号衰减强 ,干扰与时变性大等特点 ,因此 ,对于低压电力线载波信道特性 ,本文将做必要进一步具体分析 : (2)利用仿真软件 EWB,对自行设计的自动增益控制放大电路 (AGC)进行模拟仿真 ,验证其实验结果 其目的是要完成小信号的放大 ,同时保证输入信号幅值过大时 ,放大器不会饱和失真 ,此级具有自动增益控制能力 (3)设计耦合电路 ,载波调频信号从电力线上可以通过耦合电路进入到解调电路 ,耦合电路是一个带通滤波电路 ,是实现将信号频带外的其他频率滤除的功能电路 耦合电路设计的基本要求包括 :将强电与弱电隔离 ； 通过有用的载波调频信号 ； 滤除带外干扰和噪声 ； 能够双向传输 ,即能收能发 (4)设计发送驱动电路 ,并利用 EWB 仿真软件对 其进行仿真验证 调相信号经该级驱动后 ,经电容耦合 ,直接送入耦合电路 关键词： 传输特性 ， 接收调制技术 ， 自动增益控制 ， 耦合电路 ， 发送驱动电路 ntsELECTRICITY CARRIER COMMUNICATION CIRCUIT Abstract Telecommunication, telephone, wireless conminucatian, satellite communication after another communication network. Electricity network is a power line carrier communication network as access to data transmission and information exchange. Because every family is the most ordinary power lines also is the most broad coverage of a physical media, the use of power lines for data communications have great eco-nomic benefits and application prospects. The low voltage power-line network within the rules of non-sexual, transmission distance arbitrariness, and power line load change diversity makes low voltage power line interference issues have become carriers of the main obstacles to development and diffusion of communications. The topic of low-voltage electricity transmission line characteristics and receiving technical analysis prepared on the basis of electricity carrier will receive and send communications circuit design research, the main re-search reads as follows : (1) Characteristics of low-voltage electricity transmission line analysis, in low voltage electricity transmission line to signal that can be highlighted in the working conditions, small circuit impedance, signal attenuation strong, interference with the characteristics of degenerative large. For low-voltage power lines carrier access, which will be necessary to do further specific analysis. (2) Use simulation software EWB, designed AGC enlarged circuits (AGC) sim-ulation, the certification of its experimental results. The aim is to complete the small signals enlarged, while guaranteeing signal worth importing excessive, the amplifier will not saturation distortion, this class should have AGC. (3) Design coupled circuits, carrier FM signals from the power line can be cou-pled circuits entered demodulate circuit, coupled with a recovery circuit is a circuit that will be achieved outside the signal band frequency filter out other functional cir-cuits. Coupling circuit design of the basic requirements include : strong will power and weak electricity segregation; FM signals; through useful carrier outside interfer-ence and to filter out noise; To two-way transmission, which can be made collect. (4) Sent driven circuit design, and use their simulation EWB simulation software certification. PM signals, viacapacitance coupling, coupled directly into the circuit. Key words: Transmission,Receive,Agc,Drive Circuit,Coupled Circuit nts物理与信息工程学院毕业设计（论文）开题报告表 信息与通信工程 系 通信工程 专业 2002 级 时间： 2006.03.20 课题名称 电力载波通信电路 指导老师 陈忠辉 学生姓名 欧文凯 课题类型 试验研究 进行方式 真题真做 结合情况 科研 承续类型 新题目 课题简介 （基本内容及意义） 随着通信技术的不断发展 ,人们开始考虑使用电力线载波进行通信的方式。使用基于 FSK 的窄带电力线载波通信方式 ,并开发了一个在此原理上的双机串行通信演示系统。 FSK 的抗干扰性和抗衰减性 ,使得通信能够顺利进行。 电力线对载波信号来讲是一个非常糟糕的环境 ,这次设计主要要针对电力线模型中的干扰特性和衰减特性 ,讨论电力线衰减特性的测试方法 ,寻求了克服衰减和干扰的几种途径。这次设计的主要目的是设计相应的电力线发送、 接收耦合电路及自动增益放大电路系统。 该系统能否可靠工作取决于电力线扩频通信收发器设计的好坏。收发器由以下几部分组成：单片机、调制电路、解调电路、过零检测电路、接收耦合电路、发送耦合电路、滤波电路等组成。 另外该系统的一个重要过程就是自动增益控制放大电路的设计，它是使放大电路的增益自动地随信号强度而调整的自动控制方法。实现这种功能的电路简称 AGC 环。 AGC 环是闭环电子电路，它可以分成增益受控放大电路和控制电压形成电路两部分。增益受控放大电路位于正向放大通路，其增益随控制电压而改变。控制电压形成电路的基本部件 是 AGC检波器和低通平滑滤波器，有时也包含门电路和直流放大器等部件。 初步方案 三月底到四月中旬：研究电力线信道的阻抗特性和噪声特性。 四月中旬到五月中旬：设计与电力线信道匹配耦合电路。为了提高接收机的灵敏度，需在接收机端对信号进行预放大。并且为了增大接收机的动态范围，需要设计具有自动增益控制的放大器。设计相应的发送电路及接收电路。接收电路要有相应的匹配隔离措施。 五月中旬到六月初：用 EDA 软件仿真发送电路及接收电路，验证设计方案。测试系统的抗噪声特性。条件许可的话，制作样机 。并完成论文。 预计存在的问题及解决方法 1、由于电力载波通信目前在世界上还处在研发阶段，并且我们平时接触这方面的知识较少，因此设计阶段可能需要先学习相关知识与多次实验； 2、电力线信道匹配的问题，直接影响接收滤波器的性能，预处理时，应采用 AGC 技术和隔离措施； 3、对于电力线耦合问题，考虑到收发的不同耦合，我们应进行收发分离； 4、发送电路功率很大的问题，我们采用开关二极管； nts5、限于实验室的硬件设施条件，某些实验结果可能无法实现： 6、由于毕业设计时间较短，任务可能无法全 部完成。 教研室 意见 院教学指导委员会意见 nts 本科生毕业设计（论文）任务书 2006 年 03 月 20 日至 2006 年 06 月 10 日 题 目： 电力载波通信电路 姓 名： 欧文凯 学 号： 1002578 学 院： 物理与信息工程学院 专 业： 通信工程 年 级： 2002级 指导教师： （签名） 系主任（或教研室主任）： （签章） nts设 计 （ 论 文 ） 任 务 （包括原始数据、技术要求、工作要求） 1、研究电力线信道的特点，包括阻抗特性和噪声特性。 2、研究了解各种数字调制方式的原理。 3、掌握自动增益控制原理。 4、研究电力线载波信号的耦合原理及实现方法。 5、了解掌握 EDA 仿 真工具的使用、设计方法。 6、要求数据传输载波中心频率为 80120kHz，发送功率大于 1W，接收灵敏度小于10mV。 7、设计相应的电力线发送、接收耦合电路及自动增益放大电路。 8、利用 EDA 仿真工具进行仿真测试，验证设计方案。 nts毕业设计（论文）的主要内容 毕业设计的主要内容 一、设计电力线载波通信耦合电路 1、 研究电力线信道的阻抗特性和噪声特性。 2、 设计与电力线信道匹配耦合电路。 3、 为了提高接收机的灵敏度，需在接收机端对信号进行预放大。 4、 为了增大接收机的 动态范围，需要设计具有自动增益控制的放大器。 5、 为了适应电力线信道的随参特性，接收电路要具有匹配隔离措施。 6、 设计相应的发送电路及接收电路。 二、利用 EDA 仿真设计 1、 掌握 EDA 的设计方法。 2、 掌握 EDA 中相关工具箱的使用。 3、 用 EDA 软件仿真发送电路及接收电路，验证设计方案。 4、 测试系统的抗噪声特性。 5、 条件许可的话，制作样机。 进度安排： 三月底至四月中旬，研究电力线信道的阻抗特性和噪声特性。 四月中旬至五月中旬，设计与电力线信道匹配的耦合电路，以及设计自动增益控制 放大电路。设计相应的发送接收电路，接收电路要有相应的匹配隔离措施。 五月中旬至六月初，用 EDA 软件仿真自行设计的电路，验证设计方案，测试系统的抗噪声特性，并纂写论文。 nts毕业设计（论文）任务更改记录 更 改 原 因 更 改 内 容 主要参考文献 1 王赞基 ,郭静波 ,等 .电力线扩频载波通信技术及应用 .哈尔滨 .哈尔滨工业出版社 ,2000.78-100 2 陆荣春 .通信原理与技术 .上海 .上海大学出版社 ,2000.45-56 3 赵云峰，汪晓岩 ,等 .低压电力线噪声分析与建模 .北京 .中国人民出版社 ,2003.58-70 4 陈维纤 .电力线载波通信 .水利电力出版社 ,1989-02 5 高锋 ,董亚波 ,等 .低压电力线载波通信中信号传输特性分析 .电力系统自动化 .2000 6 朱近康 .扩展频谱通信及其应用 .中国科学技 术大学出版社 ,1993 7 Simth.A power line noise survey.IEEE Trans on Eletramagnetic Compatibility,1972. 8Jr.The Residential Power Circuit as a Communication Medium.IEEE North State ntsUniversity,1998. 9O.Guerra,C.M.D.A modem in CMOS technology for data communication on the low-v.2003 10Radford D.Spread-Spectrum Data Leap Through AC Power Wiring. IEEE Spectrum,1996 nts福 州 大 学 物 理 与 信 息 工 程 学 院 产学研联合指导毕业设计工作申请表 今年我院实施产学研联合指导毕业设计工作，由用人单位立题、指定专人负责指导，并试用毕业 生，校方积极配合。现请用人单位填写下表。 福州大学物理与信息工程学院 年 月 日 学生姓名： 学号： 专业： 联系电话： E-mail： 用人单位名称： 通讯地址： 邮编： 负责人姓名： 联系电话： 单位提供课题名称： 单位提供导师简介表： 姓名 学历 职务 职称 所学专业 现从事专业 校内导师 单位导师 用人单位负责人签字： 用人单位盖章： nts 福州大学本科生毕业设计（论文） 外文翻译及原文 姓 名： 欧文凯 学 号： 1002578 学 院： 物理与信息工程学院 专 业： 通信工程 年 级： 2002 级 2006年 06 月 10日 ntsST7536 introduce By Joel HULOUX I- INTRODUCTION TO THE ST7536 The ST7536 is a half duplex synchronous FSK-modem,and has been designed to operate on powerline networks.For a complete communication system, a micro-controller and a powerline-interface (PLI) are needed (see Figure 1).Such a system is able to transmit and receive on 4 different channels with 2 differentdata rates (600 and 1200 baud).The baudrate (BRS) and channel (CHS) selection is made,according to the Table. The ST7536 is a half duplex modem,as it has two operation modes;receive or transmit data.The mode selection is made with a Rx/Tx control input.Data input and output are related to the clock signal;its a synchronous modem. This clock signal is generated by the ST7536.Only a few external components have to be added for full operation of the ST7536:a crystal, four resistors and five capacitors. II- ST7536 DESCRIPTION The ST7536 is a single chip modem;all the electrical circuits needed for a complete modem are inside the chip. The modem is available in 28 pins PLCC (see Figure 2).In transmit mode the Transmit Data (TxD) is sampled on the positive edge of the clock (CLR/T).Then the data enters the FSK modulator. The frequency on which this modulator operates is set by the time base and control logic. In normal operation the multiplexer(MUX) selects the FSK modulator signal to be send to the transmit filter.This filter is a switched capacitor band-pass filter. Thetime base and controllogic uses the Automatic Frequency Control (AFC) to set this filter at the transmit frequency, corresponding to the selected channel.After filtering, the transmitsignal is sent to an Automatic Level Control (ALC).This control is used to overcome problems with line impedance variations. The powerlines on which the modem has to operate, have variations in their line characteristics,which are very frequent and totally unpredictable.The automatic level control uses a feed back signal (ALCI) from the powerline interface to adjust the transmit output (ATO).In receive mode the signal enters the chip on the Receive AnalogInput(RAI). The received signal is filtered in the receive band-pass filter. Its just like the transmit filter,a switched capacitor filter.The automatic frequency control is used to set it on the right frequency. After being amplified the signal is down converted and filtered in the intermediate frequency band-pass filter.The resulting signal is sent to the FSK demodulator. The coupling of the intermediate frequency filter output (IFO) to the FSK DEModulator Input(DEMI) is made by an externalcapacitor which cancelsan even tualoff set voltage. ntsA clock recovery circuit extracts the receive clock (CLR/T) from the demodulated output (RxDEM) of the FSK demodulator. Synchronous received data (RxD) is delivered on the positive edge of the clock.A time base section delivers all the internal clock signals from a crystal oscillator running at 11.0592MHz.The crystal is connected between the XTAL1 and XTAL2 pins.It is also possible to provide directly a clock signal on XTAL1 instead of using a crystal.To debug the chip and test external circuits the ST7536 provides some test options. The transmit band-pass filter can be observed using a direct input on the filter. This input (TxFI) is selected by the multiplexer if TEST4 = 1. The Receive bandpass Filter Output (RxFO) is provided at pin 25.Finally the clock recovery can be observed when TEST1 = 1. In this case the TEST3 input gives a direct input to the clock recovery block. III- ST7536 PIN DESCRIPTION The pin description is not given in numerical order,but the pins are described in relation with their function and consequentlysometimes with other pins. - power supply input - channel selection - crystal oscillator input - AFCF stabilisation - automatic level control input - data input and output - test inputs - IFO/DEMI output/input - transmit output and receive input - Rx/Tx control input - reset input III.1- Power Supply Input - Pin 8 (DGND): Digital ground (0V) - Pin 9 (DVDD): Digital positive supply voltage (+5V) - Pin 18 (DVSS): Digital negative supply voltage (-5V) - Pin 21 (AVSS): Analog negative supply voltage (-5V) - Pin 22 (AGND): Analog ground (0V) - Pin 23 (AVDD): Analog positive supply voltage (+5V) Internally the ST7536 has separated power supplies:The digital andanalog circuit sare separated.Externally the power supplies should be connected together.For decoupling,both the positive and negative supplies are decoupled with 2 capacitors.C6 and C7 decouple the positive,C8 and C9 the negative supplies.For proper operation the digital positive supply voltage should be decoupled with a capacitor(C10)mounted close to Pin9.C6,C8 and C10 are100nF/16Vceramic capacitors,C7 and C9 10uF/16V tant alcapacitors (seeFigure 3). ntsIII.2 - Channel Selection - Pin 15 (CHS): Channel selection input - Pin 16 (BRS): Baudrate selection input Both inputs are digital inputs (0/+5V). The ST7536 operates with two bit rates: 600 and 1200 baud. These bit rates are selected with pin 16 (BRS). For both bit rates the ST7536 offers two channels,which are selected with pin 15 (CHS).Alogical”0” is represented by 0V, a”1”by +5V. R1 and R2 are pull-down resistors,creating a logical”0”.Closing a switch gives a”1”.The selection is made according to Table 1. III.3 - Crystal Oscillator Input - Pin 13 (XTAL2): Crystal oscillator output - Pin 14 (XTAL1): Crystal oscillator input The internal crystal oscillator of the ST7536 needs an external crystal. This one should be a 11.0592MHz crystal. Two capacitors (C1 and C2) have to be added for proper operation. They are typically 22pF/10V ceramic capacitors. It is also possible to connect directly a clock signal to the oscillator input, in this case the crystal and the capacitors should be removed.On the application board this option is notused. The ST7536 clock signal is the time reference of the system. III.4 - AFCF Stabilisation - Pin 17 (AFCF) : Automatic frequency control output In the ST7536 an automaticcontrol section adjusts the central frequency of the receive and transmit band-passfilters. The stabilityof this sectionhas to be ensured with an external RC network. III.5 - Automatic Level Control Input - Pin 27 (ALCI): Automatic level control input. The output stage of the transmit path consists of an automatic level control (ALC).It offers the possibility to keep the output voltage of the power amplifier independent of variations of the powerline network. The impedance of these networks can be anywhere in the range of 5-100.If the impedance of the powerline changes,the outputof theamplifier will change.With the ALC input it is possible to correct these output variations. To control the output of the powerline interface a feed-back signal is needed. This signal is sent through an amplifier. The automatic level control can decrease the maximum transmit output in 32 steps of 0.84dB. The gain range is 0dB-26dB. A peak detection is done on the signal presented on the ALC Input and the ALCcompares it to two reference voltages, VT1 (1.87V) and VT2 (2.12V). ntsIf max. VALCI VT1 the next gain is increased by 84dB. If VT1 max. VALCI VT2 there is no gain change. If VT2 max. VALCI the next gain is decreased by 0.84dB. The gain of the feed-back amplifier is such that the feed-back signal peak voltage falls between VT1 and VT2. III.6 - Data Input and Output - Pin 5 (RxD): Synchronous receive data output - Pin 6 (CLR/T): Receive and transmit clock - Pin 7 (RxDEM): Demodulated data output - Pin 12 (TxD): Transmit data input The ST7536 is a synchronous modem; data input and output are related to the clock (CLR/T). In transmit mode the ST7536 generates this clock signal. The transmit data are sampled on the positive edge of CLR/T. Therefore the TxD should be valid at that moment.In receive mode the demodulated (receive) data is available at pin 7(RxDEM). A clock recovery circuit extracts the clock signal from the demodulated data and delivers synchronous data (RxD) on the positive edge of CLR/T. On the application board the RxDEM data output is not used. All the data signals from and to the ST7536 (RxD, TxD) are related to the clock (CLR/T) (see Figure 8). III.7 - Test Inputs - Pin 3 (TEST4): Test input,with a”1”on this pin the multiplexer selects thetransmit band-pass filter input(TXFI). - Pin 4 (TEST3): Test input which gives a direct acces to the clock recovery circuit.This input is selected when TEST1=”1”. - Pin 10 (TEST1): Test input,a”1”on this pin cancels the automatic switching from transmit to receive mode, and validates the TEST3 input to the clock recovery circuit. - Pin 11(TEST2): Test input,a”1”on this pin reduces the automatic switching time (from transmit to receive mode) to 1.48ms.On the applicationboard TEST 2/3/4 are not used,and Pins 3, 4, and 11 are thereforeset at 0V.With a switch TEST1 can be set at”0”or”1”.See also the Rx/Tx control input. III.8- IFO/DEMIOutput/Input - Pin 19 (IFO): Intermediate frequency filter output - Pin 20 (DEMI): FSK demodulator input The connection between the intermediate frequency filter output and the FSK demodulator input should be made externally with a capacitor (C5, 1uF/10V). III.9 - Transmit Output and Receive Input - Pin 24 (RAI): Receive analog input nts- pin 28 (ATO): Analog transmit output Pin 24 is the receive input of the ST7536. The receive output of the powerline interface should be connected to this pin.The maximum input voltageis 2VRMS. The receive sensitivity of the ST7536 is 2mVRMS on channel 1 and 2 (600 baud),and 3mVRMS on channel 3 and 4 (1200 baud).Pin 28 is the transmit output of the ST7536. The transmit input of the powerline interface should be connected to this pin. The ATO output is regulated by the ALCI circuit. The maximum output voltage is 3.5VPP. The second harmonic distortion is about -53dB. III.10 - Rx/Tx Control Input - Pin 1 (Rx/Tx): Receive or transmit mode selection input . The ST7536 is a half duplex modem and has therefore two operation modes: receive and transmit. This mode selection is done with the Rx/Tx input. The transmit mode is selected when Rx/Tx is”0”.If Rx/Tx is held a”0”longer than 3 seconds, the ST7536 switches back to receive mode. To set the ST7536 again in transmit mode, Rx/Tx should be held at”1”for a minimum of 3s before being set to”0”.The carrier activation time is 1msec. To be able to observe the transmit output of the ST7536 on the power line interfacefor a longer time than3 seconds it is possible to use the test 1 Input. If this input is set at”1”the automatic switching is disactivated. Then it is possible to transmit a signal but not to receive. III.11 - Reset Input - Pin 2 (RESET): Logic reset and power-down input When this input is set at” 0”the ST7536 is in power-down mode.All the internal logic is then reset.For normal operation this input should be set at”1”.On the application board this input is controlled by the micro-controller. Technical Data Sheet SSC P300 PL Network Interface Controller Features -Enables Low-cost CEBus compatible products -EIA-600 (CEBus) Data Link Layer services -EIA-600 Physical Layer transceiver -Spread Spectrum Carrier Power Line technology -SPI Host Processor interface -Data Link, Controller, and Monitor modes -Single +5 Volt power supply requirement -20 pin SOIC package ntsIntroduction The Intellon SSC P300 PL Network Interface Controller is a highly integrated power line transceiver and channel access interface for implementing CEBus compatible products.The SSC P300 provides the Data Link Layer (DLL) control logic for EIA-600 channel access and communication services, a Spread Spectrum Carrier(SSC) power line transceiver, signal conditioning circuitry, and a serial peripheral interface (SPI) compatible host interface. A minimum of external circuitry is required to connect the SSC P300 to the power line. Superior performance is achieved using the SSC P300 in conjunction with the SSC P111 Media Interface IC. The SSC P300 is used with a host microcontroller to construct CEBus compatible products, and serves as the basic communications element in a variety of low-cost power line networking applications. The inherent reliability of SSC signaling technology and incorporation of basic Data Link functionality combine to provide substantial improvement in network and communication performance over other power line communication methods. The SSC P300 also makes an excellent low cost network interface for twisted pair and DC power systems. A typical CEBus power line node using the SSC P300 is illustrated below. SSC P300 Node Block Diagram VDD DC Supply Voltage -0.3to 7.0V VIN Input Voltage at any Pin VSS-0.3 to VDD+0.3V TSTG Storage Temperature -65 to +150C TL Lead Temperature(Soldering,10 seconds)300C Note: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages. Recommended Operating Conditions VDD DC Supply Voltage 4.5、 5.0、 5.5V FOSC Oscillator Frequency 12 +/- 0.01% MHz TA Operating Temperature -40、 +25、 +85C Humidity non-condensing Electrical Characteristics Conditions:VDD = 4.5 to 5.5 V T=-40 to +85C Symbol Parameter Min Typical Max Units VOH Minimum High-level Output Voltage 2.4V VOL Maximum Low-level Output Voltage (1) 0.4V VIH Minimum High-level Input Voltage 2.0V ntsVIL Maximum Low-level Input Voltage 0.8V Hys Minimum Input hysteresis 350 mV IIL Maximum Input Leakage Current +/-10A vSO SSC Signal Output Voltage (2) 4 VP-P IDD Total Power Supply Current 25 mA Latchup (3) 150 mA Notes: 1. IOL = 2 mA 2. ZL = 2K | 10 pF 3. JEDEC JC -40.2 SSC PL P300 Network Interface Controller SSC P300 Pin Assignments 1 4MHZ 4 MHz clock out 4 MHz clock output available for host microcontroller. 2 CS*Chip select Digital input, active low. Enables serial peripheral interface. 3 VSSD Digital ground Digital ground reference. 4 XIN Crystal input Connected to external crystal to excite the ICs internal oscillator and digital clock. 5 XOUT Crystal output Connected to external crystal to excite the ICs internal oscillator and digital clock. 6 VDDD Digital supply 5.0 VDC +/- 10% digital supply voltage with respect to VSSD. 7 INT* Interrupt Digital output, active low. Attention request to host microcontroller. 8 SCLK SPI data clock Serial peripheral interface clock input from host microcontroller. 9 SDO SPI data out Data output to host microcontroller serial peripheral interface. SDO istristate when CS* is false. 10 SDI SPI data in Data input from host microcontroller serial peripheral interface. 11 TS Tristate Active low digital output signal driven from the same internal signal that enables the output amplifier. 12 RST* Reset Active low digital input. 13 VSSA Analog ground Analog ground reference. 14 SO Signal output Analog signal output. Tristate enabled with internal TS signal. 15 C2 Capacitor 2 Connection for 680pF capacitor to ground. 16 C1 Capacitor 1 Connection for 680pF capacitor to ground. 17 SI Signal input Analog signal input. 18 VDDA Analog supply 5.0 VDC +/- 10% analog supply voltage with respect to VSSA. 19 TP0 Test point 0 Reserved pin for testing. 20 VSSD Digital ground Digital ground reference.SSC PL P300 Network Interface Controller ntsSSC P300 Node Overview The SSC P300 is de