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杭州电子科技大学信息工程学院毕业设计（论文）任务书系电子工程专 业电子信息科学与技术班 级07091911学生姓名陶李梅指导教师刘国华学 号07094404一、题目低频信号发生器设计二、内容和要求（理、工科类：包括需达到的技术指标、规定阅读的文献、应完成的图纸和说明书等；经管类：包括实习期间应收集的实际材料、论文要求解决的问题及重点、规定阅读的文献等）自己搜集和查找有关低频信号发生器的技术资料，理解低频信号发生器的工作原理和设计方法，用纯硬件电路的方法设计一个可产生正弦波、方波、三角波和占空比可调脉冲波的低频信号发生器，并用Pspice软件对设计电路进行仿真，给出仿真结果。需要完成的工作内容和技术指标如下：1. 设计内容自己搜集和查找有关低频信号发生器的资料，学习Pspice电路设计与仿真软件的使用方法，在现有资料基础上自己设计一个低频函数波形发生器，并对设计电路进行仿真，给出仿真结果。功能要求如下：(1) 输出正弦波、方波、三角波、锯齿波和脉冲波；(2) 幅度频率可调；(3) 脉冲波宽度可调；2. 技术指标(1) 频率范围：0.1Hz3MHz可调;(2) 幅度范围：1mV20V可调;(3) 占空比可调范围：5%80%可调.3.参考文献1康华光编著.电子技术基础（模拟部分），北京：高等教育出版社，1999.2 谢嘉荃，宣月清，冯军电子线路T北京：高等教育出版社，20073任为民. 电子技术基础课程设计J.北京：中央广播电视大学出版社，1997 5 曾兴雯，刘兴安，陈建高频电子线路T北京：高等教育出版社，20043江蓉，CMOS高速锁相环的研究与设计D，暨南大学，2007年5弘道工作室.融会贯通 Protel99电路设计J.北京：人民交通出版设，2000 6王长江;王志军;变容二极管调频器获得线性调频的条件J;四川职业技术学院学报;2006年04期7 阎石数字电子技术基础M北京：北京航空航天大学出版社，2008，(03)8 何希才，尤克振荡电路的设计与应用T北京：科学出版社，2008(3)9 刘国华，林弥，王光义编著.通信电路实验与设计. 北京：科学出版社，2009.8 10 曾兴雯，刘兴安，陈建高频电子线路T北京：高等教育出版社，2004三、起止日期及进度安排起止日期：2010年10月26日 至2011年3月23日进度安排：序号时间内容12010.10.26-2010.11.9搜集、整理相关资料22010.11.10-2010.11.16撰写开题报告32010.11.17开题报告会42010.11.18-2010.12.1熟悉Pspice软件以及VCO电路52010.12.2-2010.12.15确立硬件电路应用方案62010.12.16-2010.12.29文献综述和外文文献翻译72010.12.30-2011.1.12硬件、软件成型、调试、检测、改进完善82011.13-2011.3.8撰写毕业论文92011.3.9-2011.3.16论文盲审及修改102011.3.23毕业答辩指导教师（签名）2010年11月10日四、教研室审查意见：教研室主任（签名）2010年11月11日系批准人（签名）2010年11月12日杭州电子科技大学信息工程学院毕业设计（论文）外文文献翻译毕业设计（论文）题目低频信号发生器的设计翻译题目直接数字频率合成器（DDS）的设计系电子工程专 业电子信息科学与技术姓 名陶李梅班 级07091911学 号07094404指导教师刘国华直接数字频率合成器（DDS）的设计 978-1-4244-5668-0/09/$25.00 2009 IEEE. Email: LChao Huang, Li-xiang Ren, Er-ke Mao and Pei-kun He(Beijing Institute of Technology Beijing, China 100081) 摘要：直接数字频率合成器（DDS）的频率是重要的表现雷达。有效的频率规划在DDS设计中仍然是一个不变问题。传统的软件基础在DDS的设计上只能得到一个在每次的运行中推动性能的频点。新提出的一个的DDS频率规划方法可以表明DDS的输出，是一个“干净”的频率波段图解法。这个简单而实用的方法可以告诉设计人员在整体频率合成器设计的早期阶段可用DDS的输出频率波段。因此，它是实现具有重要意义的高性能合成器。最后，一个真正的S波段的频率合成器是开发出一种用于频率步进雷达，频率合成器的运作良好，其测试结果证明了频率规划方法的有效性。关键词：DDS；频率规划；频率合成一导言直接数字频率合成器（DDS）已经成为大多数的频率合成器设计者的首选。其实，这是由于DDS的很多优势，如速度快跳频高速，高频率分辨率，输出相位的连续性等。但是，如果DDS作为频率合成器的核心，每个设计师都要面对鞭策问题。这是马刺队的DDS，防止它完全取代了传统的频率合成器。一般来说，频率规划是唯一可以消除了DDS马刺的实际方法。但是不幸的是，目前没有一个有效的频率规划方法。传统的基于软件的方法在每次运行时只能得到一个频点的性能。当然，这是远远不够。一个没有适当的频率规划的DDS设计可能会导致主输出伴随着附近的很多骨刺出现。这附近的马刺能成为频率成倍增加后产生的灾难。例如，如果我们把输出乘上N，功率输出的DDS附近的马刺将增加了N倍。在功率附近的马刺将增加了20lg(N)倍。因此，只有当DDS输出一个全貌马刺，我们方可做一个“干净”的DDS的输出。本文提出了一种DDS的频率规划图形最终解决了马刺问题。该图解法提供了一个对DDS的输出性能的总体设计方案，因此，DDS的马刺问题在设计阶段就可以解决以便输出一个干净的波形。 在本文中，第二节是传统的DDS的频率规划方法。第三节给出了DAC的谐波分析。第四节是图形频率规划方法的改进措施。第五节是个真正的S波段频率合成器的实验结果，第六节是结论。 二传统DDS频率规划方法一个DDS芯片通常是由一个DDS内核加上一个DAC。在应用上，马刺过滤器通常连接DAC的背后压制马刺（如图1所示）。这是一个相当典型的结构。 DDS内核用来生成数字输出振幅。该DAC的数字调幅桥梁为模拟波形。马刺过滤器是用来衰减DAC输出必不可少的。模拟马刺滤波器的衰减能力（包括通道的能力，带宽，停止带宽，订单等）是有限的，这就很有必要做好DDS频率规划设计。图1 DDS芯片的结构目前，DDS的频率规划往往是在一些模拟软件的援助下完成的。例如，ADI公司在其网站上提供了一个名为“ADIsimDDS”的模拟工具。软件模拟方法是很快的。并且，还可以表示DAC的谐波和相位截断马刺。然而，软件模拟法毕竟是一个尝试的方法。在每次运行时设计者只能得到一个频点性能;整体的性能输出表现任然未知即便尝试给出很多的频点 例如，图2显示了一个软件的模拟输出。这是由一个时钟驱动为1GHz并且输出为336MHz的DDS。该软件显示有两个马刺同时存在的情况下，一个是附近的刺激，另一个是遥远的鞭策。因为附近存在一个336兆赫的明显的马刺，所以该输出被认为是一个坏的输出。但是，如果DDS的输出一个337MHz，340MHz频率，那又会怎样呢？如果有一个强制性的规定，即马刺应远离主输出50MHz呢？太多的问题不能在“尝试”的方法中得到解决。图2 DDS的软件模拟输出三DAC的谐波分析 DAC输出的和谐波失真（HDS）不同阶，包括HD1的（所求的主要输出）和高阶HDS的。这是由于DAC核的非线性积分特性9。在HD1通道是主要输出谐波失真。当HDn（n2）时的马刺是需要被过滤掉的。 高阶DAC HDS是麻烦的，因为它们混淆了DAC的输出。幸运的是，他们的位置是可预见的。公式1显示了他们的理论位置：5。其中fs表示的是DDS芯片驱动的时钟频率，fi表示的是预期输出和实际输出。这就很容易理解，当它作为一个混合过程中采用的频率fs和fi时，公式1给出了就给出了HDs的位置。相比很合过程，他的振幅信息可估计，也就是高阶数低幅度。在实际应用中，我们只考虑HD2和HD3的影响力，较高的阶数太薄弱，往往被忽视。四一种新型图解频率规划方法在这一部分，图形频率规划的计算方法是一步一步来的。此外，总结过程是整个DDS的频率合成器设计的基础。在第三节中，m在方程1中只限于小于或等于3。此外，由于在DDS芯片上输出的DAC有一个网络连接和一个奈奎斯特约束。因此，应适用下列限制：其中m是HDS的秩序。当f0的范围在0，fs / 2时，可采取的n的数值范围将会大大减少。根据公式1和公式2，对下面的结果HD1（m = 1时），HD2（m= 2）和HD3（m= 3）可以推导：由方程式3，4，5，HD1， HD2和HD3的行为，可以得出如图3：图3 HD1，HD2和HD3的行为下一步是设置一个门槛，决定一个“干净”区域和一个“脏”的地区。通常情况下，根据马刺的过滤器（通性能带宽，停止带宽，衰减等）原因决定阈值。假设一个带宽为100MHz滤波器，它是合理的，我们希望任何马刺距离主输出至少50MHz，如图4所示。 如果我们希望任何一个马刺距离HD1 有a* fs，马刺应该是在阴影区，相应的阈值计算公式如下：图4 “干净“和“肮脏“区域比较图3和图4，我们可以得出图5，马刺和阈值同时显示。图5 HD1，HD2和HD3的显示与阈值。该延曲线的六个路口和图5阴影区域是确定 “干净”和“脏”的地区的最后边界。x坐标的六个路口可以通过如下六方程求解。六个x坐标x1，x2，x3，x 4，x 5，x 6定义三个“干净”的时间间隔为： 区间1x1, x2区间1x3, x4区间1x5, x6 这三个区间是“干净”区域，至少马刺应该远离他们afs。最后的结果归纳如下：此外，由于各区域的宽度必须是积极的，有三点结论：（1） 当0a1/7.处于三个区间都。（2） 当1/7a 1/5，处于区间1和区间3 。（3） 1/5 a，不在区间中。以上三个结论表明，我们应该在计过滤器时应该谨慎一些。五，实验结果一个真正的S波段频率合成器是开发出一种频率步进雷达。正如图6所示，频率合成器是由一个DDS和一个锁相环组成。此外， DDS的驱动时钟是一千兆赫。频率合成器输出的需要2728兆赫频率，并根据刺激滤波器参数（在DDS+ PLL的结构，推动循环实际上是由在确定过滤器PLL滤波器的参数），有一项规定，任何马刺间的距离应在100MHz到2728MHz之间。在设计阶段，这两项计划已得到审议。方案1是让DDS输出341MHz和PLL设置为x8模式，因此，最终得到一个输出为341*8 =2728MHz。方案二是输出为170.5 MHz的DDS加上X16的锁相环，同样也可以得到1700.5*16 =2728MHz的输出。图 6 S波段频率合成器的照片上面介绍的频率规划方法是用来说明那个方案更好。如上所述，当fs=1GHz时, 马刺的距离应为100MHz，可以计算为a=100/1000=0.1,他满足0a1/7. 第四节使用给出的结论，我们可以很快得到三个“干净“的输出区间：区间1：100,25MHZ区间2：275,300MHZ区间3：367,450MHZ很明显在方案1中，DDS输出341MHz是一个“干净“的部门；而在方案2中，DDS输出的170. 5MHz的是在“干净”区间；因此，方案2是更好的选择。测试条件和比较列于下表：S波段频率合成器输出频谱显示的两项方案的实验结果如图7。显然，在频率规划中，方案2提供了较佳的结果，马刺被压抑大大提高了合成器的无杂散动态范围。六结论在论文中，呈现DDS的频率规划方法。此图形方法可以给出一个可用的DDS输出频率的波段来设计阶段的整体表现的描述，因此，它大大的消除了马刺的影响。此外，一个真正的S波段频率合成器是一个频率步进雷达的发展，频率合成器工作良好，其测试结果。此外，一个真正的S波段频率合成器是一个频率步进雷达的发展，频率合成器工作良好，其测试结果证明了论文中的频率规划方法的有效性。方案1光谱方案2光谱图7 方案1和方案2在2728MHz输出七参考文献1 Eric D A, Edward A V, and Tuan T. Direct digital synthesis application for radar development. IEEE International Radar Conference, 1995.2 David B. Choose dacs for dds system applications. Microwaves and RF, 1992.3 David Brandon. DDS design. Technical report, Analog Devices, 2004.4 David Brandon. Determining if a spur is related to the dds/dac or to some other source. Technical report, Analog Devices, 2007.5 Analog Devices. 1 gsps direct digital synthesizer. page 19, 2003.6 Wheatley C E. Spurious suppression in direct digital synthesizers. Proc. 41th Annual Frequency Control Symposium, 1986.7 Venseslav F K. Spectral purity of dirict digital frequency synthesizers. Proc. 44th Annual Frequency Control Symposium, 1990.8 Venseslav F K. Discrete spurious signal and background noise in direct digital frequency synthesizers. IEEE International Frequency Control Symposium, 1993.9 Walt Kester. High speed dacs and dds systems. Technical report,Analog Devices, 1998.10 V. S. Reinhardt. Spur reduction techniques in direct digital synthesizers. In Proc. IEEE International Frequency Control Symposium 47th, pages 230241, June 24, 1993.A Systematic Frequency Planning Method inDirect Digital Synthesizer (DDS) DesignChao HuangBeijing Institute of TechnologyBeijing, China 100081Li-xiang RenBeijing Institute of TechnologyBeijing, China 100081Email: LEr-ke Maoand Pei-kun HeBeijing Institute of TechnologyAbstractDirect Digital Synthesizer (DDS) based fre-quency synthesizer is important to the performance ofradar. Effective DDS frequency planning is a problemstill untouched in DDS design. Traditional software basedmethod in DDS design can only get one frequency pointspur performance at each run. A new DDS frequencyplanning method is proposed in the paper, this methodcan indicate DDSs output ”clean” frequency band with agraphic method. This simple and useful method can tellthe designer the usable DDSs output frequency band inthe early stage of the overall frequency synthesizer design.As a result, it is of great significance in realizing a highperformance synthesizer. Finally, a real S band frequencysynthesizer was developed for a stepped frequency radar,the frequency synthesizer works well and its test resultsprove the effectiveness of the frequency planning method.Index TermsDDS, Frequency planning, frequency syn-thesizer.I. INTRODUCTIONDirect Digital Synthesizer (DDS) has already becomethe first choice of most frequency synthesizer designers.Actually, this is due to DDSs advantages such as fastfrequency hopping speed, high frequency resolution,output phase continuity and so on. However, if DDS ischosen as the frequency synthesizer core, every designerhas to face a spur issue. It is the spurs of DDS that pre-vents it from replacing traditional frequency synthesizercompletely.Generally speaking, frequency planning is the onlyway that works in eliminating the spurs of DDS inreal circumstances. Unfortunately, there isnt an effectivefrequency planning method at present. Traditional soft-ware based method can only get one frequency pointperformance at each run. Certainly, this is far fromenough. A bad DDS design without proper frequencyplanning may lead to a DDS main output accompaniedby lots of nearby spurs. This nearby spurs can becomedisaster after frequency multiplying. For example, ifwe multiply the output of DDS by N, the power ofthe nearby spurs will increase by a factor of 20lg(N).Consequently, Only when a full view of DDS outputspurs is obtained can we make a ”clean” DDS output.This paper presents a graphic DDS frequency planningmethod which gives a final solution to the spur issue. Thegraphic method provides the designer an overall pictureof the DDSs output performance, as a result, the spurperformance of the DDS is cleanly shown and spur issuecan be solved in design stage.In this paper, first, traditional DDS frequency planningmethod is introduced in section II. The DAC harmonicsanalysis is given in section III. In section IV, the graphicfrequency planning method is proposed in details. Theexperimental results based on a real S band frequencysynthesizer are presented in section V and a conclusionis given in section VI.II.TRADITIONALDDSFREQUENCY PLANNINGMETHODA DDS chip is usually made of a DDS core plus aDAC. In applications, a spur filter is usually connectedbehind to suppress DAC spurs(as depicted in Figure 1).This is a quite classic structure. DDS core is used togenerate digital output amplitude. The DAC bridges thedigital amplitude to analog waveform. The spur filteris used to attenuate unwanted spurs of DAC output. Asthe analog spur filters attenuation ability (including PassBandwidth, Stop Bandwidth, order and etc.) is limited,it is necessary to do DDS frequency planning in designstage.?Fig. 1.DDS chip structure.At present, DDS frequency planning is often donewith the aid of some simulation softwares. For example,the ADI company has provided with a simulation tool978-1-4244-5668-0/09/$25.00 2009 IEEEnamed ”ADIsimDDS” on its website. Software simula-tion method is fast. Furthermore; both the DAC harmon-ics and phase truncation spurs are indicated. However,after all, software simulation method is a try method.The designer can only get a frequency point performanceat each run; the overall output band performance is stillunknown even though lots of frequency points have beentried.For example, Figure 2 shows a software simulationoutput. This is a DDS driven by a clock of 1GHz, andthe DDS output is 336MHz. The software shows thatthere are two spurs exist in the circumstance, one is anearby spur and another is a far away spur. Because thereis an obvious nearby spur near 336MHz, this outputis considered as a bad output. However, what if DDSoutputs a frequency of 337MHz, 340MHz, .? whatif that there is a mandatory requirement that the spursshould be 50MHz away from main output? Too manyproblems cant be resolved with the ”try” method.Fig. 2.DDS software simulation output.III. ANALYSIS OF DAC HARMONICSThe DAC outputs different orders of harmonic dis-tortions(HDs), including HD1(the wanted main output)and higher order HDs. This is due to DAC cores integralnon-linearity characteristics 9. The HD1 is main outputharmonic distortion. The HDn (n 2) are spurs thatneed to be filtered out.The higher order DAC HDs are troublesome, becausethey contaminate DAC output. Fortunately, their posi-tions are predicable. Equation 1 shows their theoreticalposition: 5.fo= mfi+ nfs(1)Where fsis the frequency of DDS chip driven clock,fiis intended output and fois actual output. It becomeseasy to understand when it is taken as a mixing processof frequency fsand fi. Equation 1 gives the positions ofHDs, while the amplitude information can be estimatedwhen compared to mixing process, that is, the higherorder, the lower amplitude. In practical applications, weonly consider the influence of HD2 and HD3, higherorders are too weak and are often neglected.IV. A NOVEL GRAPHIC FREQUENCYPLANNING METHODIn this part, a graphic frequency planning method isderived step by step. Furthermore, a sum-up is madeto guide the whole DDS based frequency synthesizerdesign. Based on the analysis in section III, m inEquation 1 is confined to be less than or equal to 3.Furthermore, because of the DAC at the output of theDDS chip, there is a Nyquist constraint on fiand fo.Therefore the following constraints should apply:0 fi fs/20 fo fs/2m = 1,2,3(2)Where m is the order of HDs. When fois consideredonly within the range of 0,fs/2, the possible numbersthat n could be taken are greatly reduced. Based onEquation 1 and Equation 2, the following results onHD1(m = 1), HD2(m = 2) and HD3(m = 3) arededuced:fo1= fifor 0 fi fs/2(3)fo2=?2fifor 0 fi fs/4fs 2fifor fs/4 fi fs/2(4)fo3=3fifor 0 fi fs/6fs 3fifor fs/6 fi fs/33fi 2fsfor fs/3 fi fs/2(5)From Equation 3, 4, 5, the behavior of HD1, HD2 andHD3 can be drawn in Figure 3:ofifFig. 3.HD1, HD2 and HD3 behavior.The next step is to set a threshold that determinesthe ”clean” area and ”dirty” area. Usually, the thresholdis decided by the performance of spur filter (the passbandwidth, the stop bandwidth, the attenuation and etc).Suppose a spur filter with a stop bandwidth of 100MHz,it is reasonable that we want any spurs be at least50MHz away from main output, as depicted in Figure 4,if we want any spurs be afsaway from HD1, the spursshould be out of the shaded area, and the correspondingthreshold formulas are as follows:Threshold1 = afs+ fiThreshold2 = afs+ fi(6)?ofif1siThresholdaff?2siThresholdaff? ?Fig. 4.”Clean” and ”Dirty” area.Comparing Figure 3 and Figure 4, we can drawFigure 5 in which spurs and thresholds are showedsimultaneously.1Threshold2Thresholdofif?Fig. 5.HD1, HD2 and HD3 with threshold indicated.The six intersections of the spur curves and theshaded area in Figure 5 determine the final boundaries of”clean” and ”dirty” areas. The x-coordinates of the sixintersections can be obtained by solving the followingsix equations.(1)?fo= fi+ afsfo= 2fi fi= x1= afs(2)?fo= fi+ afsfo= 3fi+ fs fi= x2=1a4fs(3)?fo= fi afsfo= 3fi+ fs fi= x3=1+a4fs(4)?fo= fi+ afsfo= 2fi+ fs fi= x4=1a3fs(5)?fo= fi afsfo= 2fi+ fs fi= x5=1+a3fs(6)?fo= fi afsfo= 3fi fs fi= x6=1a2fsThe six x-coordinates x1,x2,x3,x4,x5,x6 define theboundaries of three ”clean” intervals as:Sector 1: x1,x2Sector 2: x3,x4Sector 3: x5,x6The three intervals are ”clean” sectors with all thespurs at least afsaway from them. The final results aresummed up as follows:SectorsboundaryBandwidthCenter frequencySector 1afs,1a4fs15a2fs1+3a8fsSector 21+a4fs,1a3fs17a12fs7a24fsSector 31+a3fs,1a2fs15a6fs5a12fsFurthermore, as the width of sectors must be positive,there are three conclusions:(1): when 0 a 17, all of three sectors are available.(2): when17 a 15, Sector 1 and Sector 3 areavailable.(3): when15 a, no sector is available.The above three conclusions indicate that we shouldbe cautious in filter design. Loose limit on filter designincurs a penalty of a large a, which leads to fewer cleansectors and may increase design difficulty.V. EXPERIMENTAL RESULTSA real S band frequency synthesizer was developedfor a stepped frequency radar. As depicted in Figure 6,The frequency synthesizer is composed of a DDS and aPLL. Furthermore; the driving clock of DDS is 1GHz.The frequency synthesizer is required to output a fre-quency of 2728MHz and according to spur filter param-eters(in the DDS+PLL structure, spur filter parametersactually are determined by loop filter in PLL), there isa requirement that any spurs should be 100MHz awayfrom 2728MHz.In design stage, two schemes have been considered.Scheme 1 is to let DDS output 341MHz and the PLLis set as X8 mode, thus a final output of 341 8 =2728MHz is obtained. Scheme 2 is a 170.5MHz output Fig. 6.Photograph of a S band frequency synthesizer.DDS plus a X16 PLL, the same output of 170.5 16 =2728MHz can also be obtained.The frequency planning method presented above wasused to tell which scheme is better. As discussed above,fs= 1GHz, as any spurs should be 100MHz away,a can be calculated as a = 100/1000 = 0.1, whichsatisfies 0 a 1/7. Using the conclusions givenin section IV, we can quickly get three ”clean” outputsectors:Sector 1: 100,225MHzSector 2: 275,300MHzSector 3: 367,450MHzIt is obvious that in Scheme 1, DDS output 341MHzis out of the ”clean” sector; while in Scheme 2, DDSoutput 170.5MHz is within the ”clean” Sector 1, con-sequentially, Scheme 2 is a better choice.The test conditions and comparisons are listed in thefollowing table:Compared contentsScheme 1Scheme 2DDS output sectors”dirty”clean”DDS output341MHz170.5MHzPLL configurationX8X16DDS+PLL output2728MHz2728MHzSpectrum resultstop of Fig 7bottom of Fig 7The spectrum output of the S band frequency synthe-sizer shows the experimental results of the two schemesin Figure 7. Obviously, after frequency planning, Scheme2 gives a better result that most of the spurs havebeen suppressed which greatly improve the synthesizersSpurious Free Dynam