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DZ213
单片机
实现
步进
电机
通用
控制器
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DZ213单片机实现的步进电机通用控制器,DZ213,单片机,实现,步进,电机,通用,控制器
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? ? ? ? ?SLAS272F JULY 2000 REVISED JUNE 20041POST OFFICE BOX 655303 DALLAS, TEXAS 75265?Low Supply-Voltage Range, 1.8 V . . . 3.6 V?Ultralow-Power Consumption: Active Mode: 280 A at 1 MHz, 2.2V Standby Mode: 1.6 A Off Mode (RAM Retention): 0.1 A?Five Power-Saving Modes?Wake-Up From Standby Mode in less than 6 s?16-Bit RISC Architecture,125-ns Instruction Cycle Time?12-Bit A/D Converter With InternalReference, Sample-and-Hold and AutoscanFeature?16-Bit Timer_B With SevenCapture/Compare-With-Shadow Registers?16-Bit Timer_A With ThreeCapture/Compare Registers?On-Chip Comparator?Serial Onboard Programming,No External Programming Voltage NeededProgrammable Code Protection by SecurityFuse?Serial Communication Interface (USART),Functions as Asynchronous UART orSynchronous SPI Interface Two USARTs (USART0, USART1) MSP430x14x(1) Devices One USART (USART0) MSP430x13xDevices?Family Members Include: MSP430F133:8KB+256B Flash Memory,256B RAM MSP430F135:16KB+256B Flash Memory,512B RAM MSP430F147, MSP430F1471:32KB+256B Flash Memory,1KB RAM MSP430F148, MSP430F1481:48KB+256B Flash Memory,2KB RAM MSP430F149, MSP430F1491:60KB+256B Flash Memory,2KB RAM?Available in 64-Pin Quad Flat Pack (QFP)and 64-pin QFN?For Complete Module Descriptions, See theMSP430x1xx Family Users Guide,Literature Number SLAU049The MSP430F14x1 devices are identical to the MSP430F14xdevices with the exception that the ADC12 module is notimplemented. descriptionThe Texas Instruments MSP430 family of ultralow-power microcontrollers consist of several devices featuringdifferent sets of peripherals targeted for various applications. The architecture, combined with five low powermodes is optimized to achieve extended battery life in portable measurement applications. The device featuresa powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6 s.The MSP430x13x and the MSP430x14x(1) series are microcontroller configurations with two built-in 16-bittimers, a fast 12-bit A/D converter (not implemented on the MSP430F14x1 devices), one or two universal serialsynchronous/asynchronous communication interfaces (USART), and 48 I/O pins.Typical applications include sensor systems that capture analog signals, convert them to digital values, andprocess and transmit the data to a host system. The timers make the configurations ideal for industrial controlapplications such as ripple counters, digital motor control, EE-meters, hand-held meters, etc. The hardwaremultiplier enhances the performance and offers a broad code and hardware-compatible family solution.Copyright 2000 2004, Texas Instruments Incorporated? ? ? ? !?#? ? ? $%&?!? ?#(?!? !? ? ?$#!?!? $#? ?)# ?#? ? ?#? ?#? *?+( ?!? $?!#?, ?#? ? ?#!#?&+ ?!&#?#?, ? ?& $?#?#?(Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.? ? ? ? ?SLAS272F JULY 2000 REVISED JUNE 20042POST OFFICE BOX 655303 DALLAS, TEXAS 75265AVAILABLE OPTIONSPACKAGED DEVICESTAPLASTIC 64-PIN QFP(PM)PLASTIC 64-PIN QFP(PAG)PLASTIC 64-PIN QFN(RTD)40C to 85CMSP430F133IPMMSP430F135IPMMSP430F147IPMMSP430F1471IPMMSP430F148IPMMSP430F1481IPMMSP430F149IPMMSP430F1491IPMMSP430F133IPAGMSP430F135IPAGMSP430F147IPAGMSP430F148IPAGMSP430F149IPAGMSP430F133IRTDMSP430F135IRTDMSP430F147IRTDMSP430F1471IRTDMSP430F148IRTDMSP430F1481IRTDMSP430F149IRTDMSP430F1491IRTDpin designation, MSP430F133, MSP430F13517 18 19P5.4/MCLKP5.3P5.2P5.1P5.0P4.7/TBCLKP4.6P4.5P4.4P4.3P4.2/TB2P4.1/TB1P4.0/TB0P3.7P3.6P3.5/URXD0484746454443424140393837363534332012345678910111213141516DVCCP6.3/A3P6.4/A4P6.5/A5P6.6/A6P6.7/A7VREF+XINXOUTVeREF+VREF/VeREFP1.0/TACLKP1.1/TA0P1.2/TA1P1.3/TA2P1.4/SMCLK21 22 23 24P5.6/ACLKTDO/TDI63 62 61 60 596458AVP6.2/A2P6.1/A1P6.0/A0RST/NMITCKTMSP2.6/ADC12CLKP2.7/TA0P3.0/STE0P3.1/SIMO0P1.7/TA2P2.1/TAINCLKP2.2/CAOUT/TA0P2.3/CA0/TA1P2.4/CA1/TA2P2.5/Rosc56 55 545725 26 27 28 2953 52P1.5/TA0XT2INXT2OUT51 50 4930 31 32P3.2/SOMI0P3.3/UCLK0P3.4/UTXD0P5.7/TBOUTHTDI/TCLKP5.5/SMCLKAVDVPM, PAG, RTD PACKAGE(TOP VIEW)P1.6/TA1P2.0/ACLKCCSSSS? ? ? ? ?SLAS272F JULY 2000 REVISED JUNE 20043POST OFFICE BOX 655303 DALLAS, TEXAS 75265pin designation, MSP430F147, MSP430F148, MSP430F14917 18 19P5.4/MCLKP5.3/UCLK1P5.2/SOMI1P5.1/SIMO1P5.0/STE1P4.7/TBCLKP4.6/TB6P4.5/TB5P4.4/TB4P4.3/TB3P4.2/TB2P4.1/TB1P4.0/TB0P3.7/URXD1P3.6/UTXD1P3.5/URXD0484746454443424140393837363534332012345678910111213141516DVCCP6.3/A3P6.4/A4P6.5/A5P6.6/A6P6.7/A7VREF+XINXOUTVeREF+VREF/VeREFP1.0/TACLKP1.1/TA0P1.2/TA1P1.3/TA2P1.4/SMCLK21 22 23 24P5.6/ACLKTDO/TDI63 62 61 60 596458AVP6.2/A2P6.1/A1P6.0/A0RST/NMITCKTMSP2.6/ADC12CLKP2.7/TA0P3.0/STE0P3.1/SIMO0P1.7/TA2P2.1/TAINCLKP2.2/CAOUT/TA0P2.3/CA0/TA1P2.4/CA1/TA2P2.5/Rosc56 55 545725 26 27 28 2953 52P1.5/TA0XT2INXT2OUT51 50 4930 31 32P3.2/SOMI0P3.3/UCLK0P3.4/UTXD0P5.7/TBOUTHTDI/TCLKP5.5/SMCLKAVDVPM, PAG, RTD PACKAGE(TOP VIEW)P1.6/TA1P2.0/ACLKCCSSSS? ? ? ? ?SLAS272F JULY 2000 REVISED JUNE 20044POST OFFICE BOX 655303 DALLAS, TEXAS 75265pin designation, MSP430F1471, MSP430F1481, MSP430F149117 18 19P5.4/MCLKP5.3/UCLK1P5.2/SOMI1P5.1/SIMO1P5.0/STE1P4.7/TBCLKP4.6/TB6P4.5/TB5P4.4/TB4P4.3/TB3P4.2/TB2P4.1/TB1P4.0/TB0P3.7/URXD1P3.6/UTXD1P3.5/URXD0484746454443424140393837363534332012345678910111213141516DVCCP6.3P6.4P6.5P6.6P6.7ReservedXINXOUTDVSSDVSSP1.0/TACLKP1.1/TA0P1.2/TA1P1.3/TA2P1.4/SMCLK21 22 23 24P5.6/ACLKTDO/TDI63 62 61 60 596458AVP6.2P6.1P6.0RST/NMITCKTMSP2.6P2.7/TA0P3.0/STE0P3.1/SIMO0P1.7/TA2P2.1/TAINCLKP2.2/CAOUT/TA0P2.3/CA0/TA1P2.4/CA1/TA2P2.5/Rosc56 55 545725 26 27 28 2953 52P1.5/TA0XT2INXT2OUT51 50 4930 31 32P3.2/SOMI0P3.3/UCLK0P3.4/UTXD0P5.7/TBOUTHTDI/TCLKP5.5/SMCLKAVDVPM, RTD PACKAGE(TOP VIEW)P1.6/TA1P2.0/ACLKCCSSSS? ? ? ? ?SLAS272F JULY 2000 REVISED JUNE 20045POST OFFICE BOX 655303 DALLAS, TEXAS 75265functional block diagramsMSP430x13xOscillatorACLKSMCLKCPUIncl. 16 Reg.BusConvMCBXINXOUTP3P4P2XT2INXT2OUTTMSTCKMDB, 16 BitMAB, 16 BitMCLK4TDI/TCLKTDO/TDIP5P6MAB,4 BitDVCCDVSSAVCCAVSSRST/NMISystemClockROSCP116KB Flash8KB Flash512B RAM256B RAMADC1212-Bit8 Channels10s Conv.WatchdogTimer15/16-BitTimer_B33 CC RegShadowRegTimer_A33 CC RegTestJTAGEmulationModuleI/O Port 1/216 I/Os,withInterruptCapabilityI/O Port 3/416 I/OsPORComparatorAUSART0UART ModeSPI ModeI/O Port 5/616 I/OsMDB, 8 BitMDB, 16-BitMAB, 16-Bit888888MSP430x14xOscillatorACLKSMCLKCPUIncl. 16 Reg.BusConvMCBXINXOUTP3P4P2XT2INXT2OUTTMSTCKMDB, 16 BitMAB, 16 BitMCLK4TDI/TCLKTDO/TDIP5P6MAB,4 BitDVCCDVSSAVCCAVSSRST/NMISystemClockROSCP1HardwareMultiplierMPY, MPYSMAC,MACS60KB Flash48KB Flash32KB Flash2KB RAM2KB RAM1KB RAMADC1212-Bit8 Channels R5Single operands, destination onlye.g. CALL R8PC (TOS), R8 PCRelative jump, un/conditionale.g. JNEJump-on-equal bit = 0Table 2. Address Mode DescriptionsADDRESS MODESDSYNTAXEXAMPLEOPERATIONRegister? ?MOV Rs,RdMOV R10,R11R10 R11Indexed? ?MOV X(Rn),Y(Rm)MOV 2(R5),6(R6)M(2+R5) M(6+R6)Symbolic (PC relative)? ?MOV EDE,TONIM(EDE) M(TONI)Absolute? ?MOV &MEM,&TCDATM(MEM) M(TCDAT)Indirect?MOV Rn,Y(Rm)MOV R10,Tab(R6)M(R10) M(Tab+R6)Indirectautoincrement?MOV Rn+,RmMOV R10+,R11M(R10) R11R10 + 2 R10Immediate?MOV #X,TONIMOV #45,TONI#45 M(TONI)NOTE: S = source D = destination? ? ? ? ?SLAS272F JULY 2000 REVISED JUNE 200412POST OFFICE BOX 655303 DALLAS, TEXAS 75265operating modesThe MSP430 has one active mode and five software selectable low-power modes of operation. An interruptevent can wake up the device from any of the five low-power modes, service the request and restore back tothe low-power mode on return from the interrupt program.The following six operating modes can be configured by software:?Active mode AM;All clocks are active?Low-power mode 0 (LPM0);CPU is disabledACLK and SMCLK remain active. MCLK is disabled?Low-power mode 1 (LPM1);CPU is disabledACLK and SMCLK remain active. MCLK is disabledDCOs dc-generator is disabled if DCO not used in active mode?Low-power mode 2 (LPM2);CPU is disabledMCLK and SMCLK are disabledDCOs dc-generator remains enabledACLK remains active?Low-power mode 3 (LPM3);CPU is disabledMCLK and SMCLK are disabledDCOs dc-generator is disabledACLK remains active?Low-power mode 4 (LPM4);CPU is disabledACLK is disabledMCLK and SMCLK are disabledDCOs dc-generator is disabledCrystal oscillator is stopped? ? ? ? ?SLAS272F JULY 2000 REVISED JUNE 200413POST OFFICE BOX 655303 DALLAS, TEXAS 75265interrupt vector addressesThe interrupt vectors and the power-up starting address are located in the address range 0FFFFh 0FFE0h.The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.INTERRUPT SOURCEINTERRUPT FLAGSYSTEM INTERRUPTWORD ADDRESSPRIORITYPower-upExternal ResetWatchdogFlash memoryWDTIFGKEYV(see Note 1)Reset0FFFEh15, highestNMIOscillator FaultFlash memory access violationNMIIFG (see Notes 1 & 4)OFIFG (see Notes 1 & 4)ACCVIFG (see Notes 1 & 4)(Non)maskable(Non)maskable(Non)maskable0FFFCh14Timer_B7 (see Note 5)TBCCR0 CCIFG (see Note 2)Maskable0FFFAh13Timer_B7 (see Note 5)TBCCR1 to 6 CCIFGs,TBIFG (see Notes 1 & 2)Maskable0FFF8h12Comparator_ACAIFGMaskable0FFF6h11Watchdog timerWDTIFGMaskable0FFF4h10USART0 receiveURXIFG0Maskable0FFF2h9USART0 transmitUTXIFG0Maskable0FFF0h8ADC12 (see Note 6)ADC12IFG (see Notes 1 & 2)Maskable0FFEEh7Timer_A3TACCR0 CCIFG (see Note 2)Maskable0FFECh6Timer_A3TACCR1 CCIFG,TACCR2 CCIFG,TAIFG (see Notes 1 & 2)Maskable0FFEAh5I/O port P1 (eight flags)P1IFG.0 to P1IFG.7(see Notes 1 & 2)Maskable0FFE8h4USART1 receiveURXIFG1Maskable0FFE6h3USART1 transmitUTXIFG10FFE4h2I/O port P2 (eight flags)P2IFG.0 to P2IFG.7(see Notes 1 & 2)Maskable0FFE2h10FFE0h0, lowestNOTES:1. Multiple source flags2.Interrupt flags are located in the module.3.Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.4.(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable can not disableit.5.Timer_B7 in MSP430x14x(1) family has 7 CCRs; Timer_B3 in MSP430x13x family has 3 CCRs. In Timer_B3 there are only interruptflags TBCCR0, 1, and 2 CCIFGs and the interrupt-enable bits TBCCTL0, 1, and 2 CCIEs.6.ADC12 is not implemented on the 14x1 devices.? ? ? ? ?SLAS272F JULY 2000 REVISED JUNE 200414POST OFFICE BOX 655303 DALLAS, TEXAS 75265special function registersMost interrupt and module-enable bits are collected in the lowest address space. Special-function register bitsnot allocated to a functional purpose are not physically present in the device. This arrangement provides simplesoftware errupt enable 1 and 276540UTXIE0OFIEWDTIE321 rw-0 rw-0 rw-0Address0hURXIE0ACCVIENMIIE rw-0 rw-0 rw-0WDTIE:Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdogtimer is configured in interval timer mode.OFIE:Oscillator-fault-interrupt enableNMIIE:Nonmaskable-interrupt enableACCVIE:Flash access violation interrupt enableURXIE0:USART0: UART and SPI receive-interrupt enableUTXIE0:USART0: UART and SPI transmit-interrupt enable76540UTXIE1321 rw-0 rw-0Address01hURXIE1URXIE1:USART1: UART and SPI receive-interrupt enableUTXIE1:USART1: UART and SPI transmit-interrupt enableinterrupt flag register 1 and 276540UTXIFG0OFIFGWDTIFG321 rw-0 rw-1 rw-(0)Address02hURXIFG0NMIIFG rw-1 rw-0WDTIFG:Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on VCCpower up or a reset condition at the RST/NMI pin in reset mode.OFIFG:Flag set on oscillator faultNMIIFG:Set via RST/NMI pinURXIFG0:USART0: UART and SPI receive flagUTXIFG0:USART0: UART and SPI transmit flag76540UTXIFG1321 rw-1 rw-0Address03hURXIFG1URXIFG1:USART1: UART and SPI receive flagUTXIFG1:USART1: UART and SPI transmit flag? ? ? ? ?SLAS272F JULY 2000 REVISED JUNE 200415POST OFFICE BOX 655303 DALLAS, TEXAS 75265module enable registers 1 and 276540UTXE0321 rw-0 rw-0Address04hURXE0USPIE0URXE0:USART0: UART receive enableUTXE0:USART0: UART transmit enableUSPIE0:USART0: SPI (synchronous peripheral interface) transmit and receive enable76540UTXE1321 rw-0 rw-0Address05hURXE1USPIE1URXE1:USART1: UART receive enableUTXE1:USART1: UART transmit enableUSPIE1:USART1: SPI (synchronous peripheral interface) transmit and receive enable rw-0:Legend: rw:Bit Can Be Read and WrittenBit Can Be Read and Written. It Is Reset by PUC.SFR Bit Not Present in Devicememory organizationMSP430F133MSP430F135MSP430F147MSP430F1471MSP430F148MSP430F1481MSP430F149MSP430F1491MemoryMain: interrupt vectorMain: code memorySizeFlashFlash8KB0FFFFh 0FFE0h0FFFFh 0E000h16KB0FFFFh 0FFE0h0FFFFh 0C000h32KB0FFFFh 0FFE0h0FFFFh 08000h48KB0FFFFh 0FFE0h0FFFFh 04000h60KB0FFFFh 0FFE0h0FFFFh 01100hInformation memorySizeFlash256 Byte010FFh 01000h256 Byte010FFh 01000h256 Byte010FFh 01000h256 Byte010FFh 01000h256 Byte010FFh 01000hBoot memorySizeROM1KB0FFFh 0C00h1KB0FFFh 0C00h1KB0FFFh 0C00h1KB0FFFh 0C00h1KB0FFFh 0C00hRAMSize256 Byte02FFh 0200h512 Byte03FFh 0200h1KB05FFh 0200h2KB09FFh 0200h2KB09FFh 0200hPeripherals16-bit8-bit8-bit SFR01FFh 0100h0FFh 010h0Fh 00h01FFh 0100h0FFh 010h0Fh 00h01FFh 0100h0FFh 010h0Fh 00h01FFh 0100h0FFh 010h0Fh 00h01FFh 0100h0FFh 010h0Fh 00hbootstrap loader (BSL)The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serialinterface. Access to the MSP430 memory via the BSL is protected by user-defined password. For completedescription of the features of the BSL and its implementation, see the Application report Features of the MSP430Bootstrap Loader, Literature Number SLAA089.BSL FunctionPM, PAG & RTD Package PinsData Transmit13 - P1.1Data Receive22 - P2.2? ? ? ? ?SLAS272F JULY 2000 REVISED JUNE 200416POST OFFICE BOX 655303 DALLAS, TEXAS 75265flash memoryThe flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. TheCPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:?Flash memory has n segments of main memory and two segments of information memory (A and B) of 128bytes each. Each segment in main memory is 512 bytes in size.?Segments 0 to n may be erased in one step, or each segment may be individually erased.?Segments A and B can be erased individually, or as a group with segments 0n.Segments A and B are also called information memory.?New devices may have some bytes programmed in the information memory (needed for test duringmanufacturing). The user should perform an erase of the information memory prior to the first use. Segment 0w/ Interrupt VectorsSegment 1Segment 2Segment n-1Segment nSegment ASegment BMainMemoryInformationMemory8 KB0FFFFh0FE00h0FDFFh0FC00h0FBFFh0FA00h0F9FFh16 KB0FFFFh0FE00h0FDFFh0FC00h0FBFFh0FA00h0F9FFh32 KB0FFFFh0FE00h0FDFFh0FC00h0FBFFh0FA00h0F9FFh48 KB0FFFFh0FE00h0FDFFh0FC00h0FBFFh0FA00h0F9FFh60 KB0FFFFh0FE00h0FDFFh0FC00h0FBFFh0FA00h0F9FFh0E400h0E3FFh0E200h0E1FFh0E000h010FFh01080h0107Fh01000h0C400h0C3FFh0C200h0C1FFh0C000h010FFh01080h0107Fh01000h08400h083FFh08200h081FFh08000h010FFh01080h0107Fh01000h04400h043FFh04200h041FFh04000h010FFh01080h0107Fh01000h01400h013FFh01200h011FFh01100h010FFh01080h0107Fh01000h? ? ? ? ?SLAS272F JULY 2000 REVISED JUNE 200417POST OFFICE BOX 655303 DALLAS, TEXAS 75265peripheralsPeripherals are connected to the CPU through data, address, and control busses and can be handled usingall instructions. For complete module descriptions, see the MSP430x1xx Family Users Guide, literature numberSLAU049.digital I/OThere are six 8-bit I/O ports implementedports P1 through P6:?All individual I/O bits are independently programmable.?Any combination of input, output, and interrupt conditions is possible.?Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.?Read/write access to port-control registers is supported by all instructions.oscillator and system clockThe clock system in the MSP430x13x and MSP43x14x(1) family of devices is supported by the basic clockmodule that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator(DCO) and a high frequency crystal oscillator. The basic clock module is designed to meet the requirementsof both low system cost and low-power consumption. The internal DCO provides a fast turn-on clock sourceand stabilizes in less than 6 s. The basic clock module provides the following clock signals:?Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.?Main clock (MCLK), the system clock used by the CPU.?Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.watchdog timerThe primary function of the watchdog timer (WDT) module is to perform a controlled system restart after asoftware problem occurs. If the selected time interval expires, a system reset is generated. If the watchdogfunction is not needed in an application, the module can be configured as an interval timer and can generateinterrupts at selected time intervals.hardware multiplier (MSP430x14x and MSP430x14x1 Only)The multiplication operation is supported by a dedicated peripheral module. The module performs 16?16,16?8, 8?16, and 8?8 bit operations. The module is capable of supporting signed and unsigned multiplicationas well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessedimmediately after the operands have been loaded into the peripheral registers. No additional clock cycles arerequired.USART0The MSP430x13x and the MSP430x14x(1) have one hardware universal synchronous/asynchronous receivetransmit (USART0) peripheral module that is used for serial data communication. The USART supportssynchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-bufferedtransmit and receive channels.USART1 (MSP430x14x and MSP430x14x1 Only)The MSP430x14x(1) has a second hardware universal synchronous/asynchronous receive transmit (USART1)peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels.Operation of USART1 is identical to USART0.? ? ? ? ?SLAS272F JULY 2000 REVISED JUNE 200418POST OFFICE BOX 655303 DALLAS, TEXAS 75265 comparator_AThe primary function of the comparator_A module is to support precision slope analogtodigital conversions,batteryvoltage supervision, and monitoring of external analog signals.ADC12 (Not implemented in the MSP430x14x1)The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SARcore, sample select control, reference generator and a 16 word conversion-and-control buffer. Theconversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored withoutany CPU intervention.timer_A3Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiplecapture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.Interrupts may be generated from the counter on overflow conditions and from each of the capture/compareregisters.Timer_A3 Signal ConnectionsInput Pin NumberDevice Input SignalModule Input NameModule BlockModule Output SignalOutput Pin Number12 - P1.0TACLKTACLKACLKACLKTimerNASMCLKSMCLKTimerNA21 - P2.1TAINCLKINCLK13 - P1.1TA0CCI0A13 - P1.122 - P2.2TA0CCI0BCCR0TA017 - P1.5DVSSGNDCCR0TA027 - P2.7DVCCVCC14 - P1.2TA1CCI1A14 - P1.2CAOUT (internal)CCI1BCCR1TA118 - P1.6DVSSGNDCCR1TA123 - P2.3DVCCVCCADC12 (internal)15 - P1.3TA2CCI2A15 - P1.3ACLK (internal)CCI2BCCR2TA219 - P1.7DVSSGNDCCR2TA224 - P2.4DVCCVCCtimer_B3 (MSP430x13x Only)Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiplecapture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.Interrupts may be generated from the counter on overflow conditions and from each of the capture/compareregisters.? ? ? ? ?SLAS272F JULY 2000 REVISED JUNE 200419POST OFFICE BOX 655303 DALLAS, TEXAS 75265timer_B7 (MSP430x14x and MSP430x14x1 Only)Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiplecapture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities.Interrupts may be generated from the counter on overflow conditions and from each of the capture/compareregisters.Timer_B3/B7 Signal ConnectionsInput Pin NumberDevice Input SignalModule Input NameModule BlockModule Output SignalOutput Pin Number43 - P4.7TBCLKTBCLKACLKACLKTimerNASMCLKSMCLKTimerNA43 - P4.7TBCLKINCLK36 - P4.0TB0CCI0A36 - P4.036 - P4.0TB0CCI0BCCR0TB0ADC12 (internal)DVSSGNDCCR0TB0DVCCVCC37 - P4.1TB1CCI1A37 - P4.137 - P4.1TB1CCI1BCCR1TB1ADC12 (internal)DVSSGNDCCR1TB1DVCCVCC38 - P4.2TB2CCI2A38 - P4.238 - P4.2TB2CCI2BCCR2TB2DVSSGNDCCR2TB2DVCCVCC39 - P4.3TB3CCI3A39 - P4.339 - P4.3TB3CCI3BCCR3TB3DVSSGNDCCR3TB3DVCCVCC40 - P4.4TB4CCI4A40 - P4.440 - P4.4TB4CCI4BCCR4TB4DVSSGNDCCR4TB4DVCCVCC41 - P4.5TB5CCI5A41 - P4.541 - P4.5TB5CCI5BCCR5TB5DVSSGNDCCR5TB5DVCCVCC42 - P4.6TB6CCI6A42 - P4.6ACLK (internal)CCI6BCCR6TB6DVSSGNDCCR6TB6DVCCVCCTimer_B3 implements three capture/compare blocks (CCR0, CCR1 and CCR2 only).? ? ? ? ?SLAS272F JULY 2000 REVISED JUNE 200420POST OFFICE BOX 655303 DALLAS, TEXAS 75265peripheral file mapPERIPHERALS WITH WORD ACCESSWatchdogWatchdog Timer controlWDTCTL0120hTimer_B7/Timer_B3Timer_B interrupt vectorTBIV011EhTimer_B7/Timer_B3(see Note 1)Timer_B controlTBCTL0180h(see Note 1)Capture/compare control 0TBCCTL00182hCapture/compare control 1TBCCTL10184hCapture/compare control 2TBCCTL20186hCapture/compare control 3TBCCTL30188hCapture/compare control 4TBCCTL4018AhCapture/compare control 5TBCCTL5018ChCapture/compare control 6TBCCTL6018EhTimer_B registerTBR0190hCapture/compare register 0TBCCR00192hCapture/compare register 1TBCCR10194hCapture/compare register 2TBCCR20196hCapture/compare register 3TBCCR30198hCapture/compare register 4TBCCR4019AhCapture/compare register 5TBCCR5019ChCapture/compare register 6TBCCR6019EhTimer_A3Timer_A interrupt vectorTAIV012EhTimer_A3Timer_A controlTACTL0160hCapture/compare control 0TACCTL00162hCapture/compare control 1TACCTL10164hCapture/compare control 2TACCTL20166hReserved0168hReserved016AhReserved016ChReserved016EhTimer_A registerTAR0170hCapture/compare register 0TACCR00172hCapture/compare register 1TACCR10174hCapture/compare register 2TACCR20176hReserved0178hReserved017AhReserved017ChReserved017EhHardwareMultiplierSum extendSUMEXT013EhHardwareMultiplier(MSP430x14x andResult high wordRESHI013Ch(MSP430x14x andMSP430x14x1Result low wordRESLO013AhMSP430x14x1only)Second operandOP20138honly)Multiply signed +accumulate/operand1MACS0136hMultiply+accumulate/operand1MAC0134hMultiply signed/operand1MPYS0132hMultiply unsigned/operand1MPY0130hNOTE 1:Timer_B7 in MSP430x14x(1) family has 7 CCRs, Timer_B3 in MSP430x13x family has 3 CCRs.? ? ? ? ?SLAS272F JULY 2000 REVISED JUNE 200421POST OFFICE BOX 655303 DALLAS, TEXAS 75265peripheral file map (continued)PERIPHERALS WITH WORD ACCESS (CONTINUED)FlashFlash control 3FCTL3012ChFlashFlash control 2FCTL2012AhFlash control 1FCTL10128hADC12(Not implemented inConversion memory 15ADC12MEM15015EhADC12(Not implemented inthe MSP430x14x1)Conversion memory 14ADC12MEM14015Chthe MSP430x14x1)Conversion memory 13ADC12MEM13015AhConversion memory 12ADC12MEM120158hConversion memory 11ADC12MEM110156hConversion memory 10ADC12MEM100154hConversion memory 9ADC12MEM90152hConversion memory 8ADC12MEM80150hConversion memory 7ADC12MEM7014EhConversion memory 6ADC12MEM6014ChConversion memory 5ADC12MEM5014AhConversion memory 4ADC12MEM40148hConversion memory 3ADC12MEM30146hConversion memory 2ADC12MEM20144hConversion memory 1ADC12MEM10142hConversion memory 0ADC12MEM00140hInterrupt-vector-word registerADC12IV01A8hInerrupt-enable registerADC12IE01A6hInerrupt-flag registerADC12IFG01A4hControl register 1ADC12CTL101A2hControl register 0ADC12CTL001A0hADC memory-control register15ADC12MCTL1508FhADC memory-control register14ADC12MCTL1408EhADC memory-control register13ADC12MCTL1308DhADC memory-control register12ADC12MCTL1208ChADC memory-control register11ADC12MCTL1108BhADC memory-control register10ADC12MCTL1008AhADC memory-control register9ADC12MCTL9089hADC memory-control register8ADC12MCTL8088hADC memory-control register7ADC12MCTL7087hADC memory-control register6ADC12MCTL6086hADC memory-control register5ADC12MCTL5085hADC memory-control register4ADC12MCTL4084hADC memory-control register3ADC12MCTL3083hADC memory-control register2ADC12MCTL2082hADC memory-control register1ADC12MCTL1081hADC memory-control register0ADC12MCTL0080h? ? ? ? ?SLAS272F JULY 2000 REVISED JUNE 200422POST OFFICE BOX 655303 DALLAS, TEXAS 75265peripheral file map (continued)PERIPHERALS WITH BYTE ACCESSUSART1(MSP430x14x andTransmit bufferU1TXBUF07FhUSART1(MSP430x14x andMSP430x14x1 only)Receive bufferU1RXBUF07EhMSP430x14x1 only)Baud rateU1BR107DhBaud rateU1BR007ChModulation controlU1MCTL07BhReceive controlU1RCTL07AhTransmit controlU1TCTL079hUSART controlU1CTL078hUSART0Transmit bufferU0TXBUF077hUSART0Receive bufferU0RXBUF076hBaud rateU0BR1075hBaud rateU0BR0074hModulation controlU0MCTL073hReceive controlU0RCTL072hTransmit controlU0TCTL071hUSART controlU0CTL070hComparator_AComparator_A port disableCAPD05BhComparator_AComparator_A control2CACTL205AhComparator_A control1CACTL1059hBasic ClockBasic clock system control2BCSCTL2058hBasic ClockBasic clock system control1BCSCTL1057hDCO clock frequency controlDCOCTL056hPort P6Port P6 selectionP6SEL037hPort P6Port P6 directionP6DIR036hPort P6 outputP6OUT035hPort P6 inputP6IN034hPort P5Port P5 selectionP5SEL033hPort P5Port P5 directionP5DIR032hPort P5 outputP5OUT031hPort P5 inputP5IN030hPort P4Port P4 selectionP4SEL01FhPort P4Port P4 directionP4DIR01EhPort P4 outputP4OUT01DhPort P4 inputP4IN01ChPort P3Port P3 selectionP3SEL01BhPort P3Port P3 directionP3DIR01AhPort P3 outputP3OUT019hPort P3 inputP3IN018hPort P2Port P2 selectionP2SEL02EhPort P2Port P2 interrupt enableP2IE02DhPort P2 interrupt-edge selectP2IES02ChPort P2 interrupt flagP2IFG02BhPort P2 directionP2DIR02AhPort P2 outputP2OUT029hPort P2 inputP2IN028h? ? ? ? ?SLAS272F JULY 2000 REVISED JUNE 200423POST OFFICE BOX 655303 DALLAS, TEXAS 75265peripheral file map (continued)PERIPHERALS WITH BYTE ACCESS (CONTINUED)Port P1Port P1 selectionP1SEL026hPort P1Port P1 interrupt enableP1IE025hPort P1 interrupt-edge selectP1IES024hPort P1 interrupt flagP1IFG023hPort P1 directionP1DIR022hPort P1 outputP1OUT021hPort P1 inputP1IN020hSpecial FunctionsSFR module enable 2ME2005hSpecial FunctionsSFR module enable 1ME1004hSFR interrupt flag2IFG2003hSFR interrupt flag1IFG1002hSFR interrupt enable2IE2001hSFR interrupt enable1IE1000habsolute maximum ratings over operating free-air temperature (unless otherwise noted)Voltage applied at VCC to VSS 0.3 V to + 4.1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage applied to any pin (see Note) 0.3 V to VCC+0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diode current at any device terminal . 2 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage temperature (unprogrammed device) 55C to 150C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage temperature (programmed device) 40C to 85C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.NOTE: All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is appliedto the TDI/TCLK pin when blowing the JTAG fuse.? ? ? ? ?SLAS272F JULY 2000 REVISED JUNE 200424POST OFFICE BOX 655303 DALLAS, TEXAS 75265recommended operating conditionsPARAMETERMINNOMMAXUNITSSupply voltage during program execution, VCC (AVCC = DVCC = VCC)MSP430F13x,MSP430F14x(1)1.83.6VSupply voltage during flash memory programming, VCC(AVCC = DVCC = VCC)MSP430F13x,MSP430F14x(1)2.73.6VSupply voltage, VSS (AVSS = DVSS = VSS)0.00.0VOperating free-air temperature range, TAMSP430x13xMSP430x14x(1)4085CLFXT1 crystal frequency, f(LFXT1) LF selected, XTS=0Watch crystal32768HzLFXT1 crystal frequency, f(LFXT1) (see Notes 1 and 2)XT1 selected, XTS=1Ceramic resonator4508000kHz(see Notes 1 and 2)XT1 selected, XTS=1Crystal10008000kHzXT2 crystal frequency, f(XT2)Ceramic resonator4508000kHzXT2 crystal frequency, f(XT2)Crystal10008000kHzProcessor frequency (signal MCLK), f(System)VCC = 1.8 VDC4.15MHzProcessor frequency (signal MCLK), f(System)VCC = 3.6 VDC8MHzNOTES:1. In LF mode, the LFXT1 oscillator requires a watch crystal. A 5.1M resistor from XOUT to VSS is recommended when VCC VREF/VeREF (see Note 2)1.4VAVCCVVREF /VeREFNegative externalreference voltage inputVeREF+ VREF/VeREF (see Note 3)01.2V(VeREF+VREF/VeREF)Differential externalreference voltage inputVeREF+ VREF/VeREF (see Note 4)1.4VAVCCVIVeREF+Static input current0V VeREF+ VAVCC2.2 V/3 V1AIVREF/VeREFStatic input current0V VeREF VAVCC2.2 V/3 V1ANOTES:1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, Ci, is alsothe dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow therecommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.2.The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reducedaccuracy requirements.3.The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reducedaccuracy requirements.4.The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied withreduced accuracy requirements.? ? ? ? ?SLAS272F JULY 2000 REVISED JUNE 200435POST OFFICE BOX 655303 DALLAS, TEXAS 75265electrical characteristics over recommended operating free-air temperature (unless otherwisenoted) (continued)12-bit ADC, built-in referencePARAMETERTEST CONDITIONSMINNOMMAXUNITVREF+Positive built-in referenceREF2_5V = 1 for 2.5 VIVREF+ IVREF+max3 VVVREF+Positive built-in referencevoltage outputREF2_5V = 0 for 1.5 VIVREF+ IVREF+max2.2 V/3 V1.441.51.56VAVCC minimum voltage,REF2_5V = 0, IVREF+ 1mA2.2AVCC(min)AVCC minimum voltage,Positive built-in referenceactiveREF2_5V = 1, IVREF+ 0.5mAVREF+ + 0.15VAVCC(min)Positive built-in referenceactiveREF2_5V = 1, IVREF+ 1mAVREF+ + 0.15VIVREF+Load current out of VREF+2.2 V0.010.5mAIVREF+Load current out of VREF+terminal3 V1mAIVREF+ = 500 A +/ 100 AAnalog input voltage 0.75 V; 2.2 V2LSBIL(VREF)+ Load-current regulationVREF+Analog input voltage 0.75 V; REF2_5V = 03 V2LSBIL(VREF)+ Load-current regulationVREF+ terminalIVREF+ = 500 A 100 AAnalog input voltage 1.25 V;REF2_5V = 13 V2LSBIDL(VREF) +Load current regulationIVREF+ =100 A 900 A,CVREF+=5 F, ax 0.5 x VREF+ 3 V20nsIDL(VREF) +Load current regulationVREF+ terminalVREF+CVREF+=5 F, ax 0.5 x VREF+ Error of conversion result 1 LSB3 V20nsCVREF+Capacitance at pin VREF+(see Note 1)REFON =1,0 mA IVREF+ IVREF+max2.2 V/3 V510FTREF+Temperature coefficient ofbuilt-in referenceIVREF+ is a constant in the range of0 mA IVREF+ 1 mA2.2 V/3 V100ppm/CtREFONSettle time of internalreference voltage (seeFigure 13 and Note 2)IVREF+ = 0.5 mA, CVREF+ = 10 F,VREF+ = 1.5 V, VAVCC = 2.2 V17msNot production tested, limits characterizedNot production tested, limits verified by designNOTES:1. The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests usestwo capacitors between pins VREF+ and AVSS and VREF/VeREF and AVSS: 10 F tantalum and 100 nF ceramic.NOTES:2. The condition is that the error in a conversion started after tREFON is less than 0.5 LSB. The settling time depends on the externalcapacitive load.CVREF+1 F01 ms10 ms100 mstREFONtREFON .66 x CVREF+ ms with CVREF+ in F100 F10 FFigure 13. Typical Settling Time of Internal Reference tREFON vs External Capacitor on VREF+? ? ? ? ?SLAS272F JULY 2000 REVISED JUNE 200436POST OFFICE BOX 655303 DALLAS, TEXAS 75265+10 F100 nFAVSSMSP430F13xMSP430F14x+10 F100 nF10 F100 nFAVCC10 F100 nFDVSSDVCCFromPowerSupplyApplyExternalReference+Apply External Reference VeREF+or Use Internal Reference VREF+VREF+ or VeREF+VREF/VeREFFigure 14. Supply Voltage and Reference Voltage Design VREF/VeREF External Supply+10 F100 nFAVSSMSP430F13xMSP430F14x+10 F100 nFAVCC10 F100 nFDVSSDVCCFromPowerSupply+Apply External Reference VeREF+or Use Internal Reference VREF+VREF+ or VeREF+VREF/VeREFReference Is InternallySwitched to AVSSFigure 15. Supply Voltage and Reference Voltage Design VREF/VeREF = AVSS, Internally Connected? ? ? ? ?SLAS272F JULY 2000 REVISED JUNE 200437POST OFFICE BOX 655303 DALLAS, TEXAS 75265electrical characteristics over recommended operating free-air temperature (unless otherwisenoted) (continued)12-bit ADC, timing parametersPARAMETERTEST CONDITIONSMINNOMMAXUNITfADC12CLKFor specified performance of ADC12linearity parameters2.2V/3V0.4556.3MHzfADC12OSCInternal ADC12oscillatorADC12DIV=0,fADC12CLK=fADC12OSC2.2 V/3V3.76.3MHztCONVERTConversion timeCVREF+ 5 F, Internal oscillator,fADC12OSC = 3.7 MHz to 6.3 MHz2.2 V/3 V2.063.51stCONVERTConversion timeExternal fADC12CLK from ACLK, MCLK or SMCLK:ADC12SSEL 013ADC12DIV1/fADC12CLKstADC12ONTurn on settling time ofthe ADC(see Note 1)100nstSampleSampling timeRS = 400 , RI = 1000 , CI = 30 pF3 V1220nstSampleSampling timeSICI = 30 pF = RS + RI x CI;(see Note 2)2.2 V1400nsNot production tested, limits characterizedNot production tested, limits verified by designNOTES:1. The condition is that the error in a conversion started after tADC12ON is less than 0.5 LSB. The reference and input signal are alreadysettled.2.Approximately ten Tau () are needed to get an error of less than 0.5 LSB:tSample = ln(2n+1) x (RS + RI) x CI+ 800 ns where n = ADC resolution = 12, RS = external source resistance.12-bit ADC, linearity parametersPARAMETERTEST CONDITIONSMINNOMMAXUNITEIIntegral linearity error1.4 V (VeREF+ VREF/VeREF) min 1.6 V2.2 V/3 V2LSBEIIntegral linearity error1.6 V (VeREF+ VREF/VeREF) min V(AVCC)2.2 V/3 V1.7LSBEDDifferential linearityerror(VeREF+ VREF/VeREF)min (VeREF+ VREF/VeREF),CVREF+ = 10 F (tantalum) and 100 nF (ceramic)2.2 V/3 V1LSBEOOffset error(VeREF+ VREF/VeREF)min (VeREF+ VREF/VeREF),Internal impedance of source RS 100 ,CVREF+ = 10 F (tantalum) and 100 nF (ceramic)2.2 V/3 V24LSBEGGain error(VeREF+ VREF/VeREF)min (VeREF+ VREF/VeREF),CVREF+ = 10 F (tantalum) and 100 nF (ceramic)2.2 V/3 V1.12LSBETTotal unadjustederror(VeREF+ VREF/VeREF)min (VeREF+ VREF/VeREF),CVREF+ = 10 F (tantalum) and 100 nF (ceramic)2.2 V/3 V25LSB? ? ? ? ?SLAS272F JULY 2000 REVISED JUNE 200438POST OFFICE BOX 655303 DALLAS, TEXAS 75265electrical characteristics over recommended operating free-air temperature (unless otherwisenoted) (continued)12-bit ADC, temperature sensor and built-in VMIDPARAMETERTEST CONDITIONSMINNOMMAXUNITISENSOROperating supply current intoREFON = 0, INCH = 0Ah,2.2 V40120AISENSOROperating supply current intoAVCC terminal (see Note 1)REFON = 0, INCH = 0Ah,ADC12ON=NA, TA = 25?C3 V60160AVSENSORADC12ON = 1, INCH = 0Ah, 2.2 V9869865%mVVSENSORADC12ON = 1, INCH = 0Ah, TA = 0C3 V9869865%mVTCSENSORADC12ON = 1, INCH = 0Ah2.2 V3.553.553%mV/CTCSENSORADC12ON = 1, INCH = 0Ah3 V3.553.553%mV/CtSENSOR(sample)Sample time required if channelADC12ON = 1, INCH = 0Ah,2.2 V30stSENSOR(sample)Sample time required if channel10 is selected (see Note 2)ADC12ON = 1, INCH = 0Ah,Error of conversion result 1 LSB3 V30sIVMIDCurrent into divider at channel 11ADC12ON = 1, INCH = 0Bh2.2 VNAAIVMIDCurrent into divider at channel 11(see Note 3)ADC12ON = 1, INCH = 0Bh3 VNAAVMIDAVCC divider at channel 11ADC12ON = 1, INCH = 0Bh,2.2 V4VVMIDAVCC divider at channel 11ADC12ON = 1, INCH = 0Bh,VMID is 0.5 x VAVCC3 V1.51.500.04VtVMID(sample)Sample time required if channelADC12ON = 1, INCH = 0Bh,2.2 V1400nstVMID(sample)Sample time required if channel11 is selected (see Note 4)ADC12ON = 1, INCH = 0Bh,Error of conversion result 1 LSB3 V1220nsNot production tested, limits characterizedNOTES:1. The sensor current ISENSOR is consumed if (ADC12ON = 1 and REFON=1), or (ADC12ON=1 AND INCH=0Ah and sample signalis high). Therefore it includes the constant current through the sensor and the reference.2.The typical equivalent impedance of the sensor is 51 k. The sample time required includes the sensor-on time tSENSOR(on).3.No additional current is needed. The VMID is used during sampling.4.The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.? ? ? ? ?SLAS272F JULY 2000 REVISED JUNE 200439POST OFFICE BOX 655303 DALLAS, TEXAS 75265electrical characteristics over recommended operating free-air temperature (unless otherwisenoted) (continued)Flash MemoryPARAMETERTESTCONDITIONSVCCMINNOMMAXUNITVCC(PGM/ERASE)Program and Erase supply voltage2.73.6VfFTGFlash Timing Generator frequency257476kHzIPGMSupply current from DVCC during program2.7 V/ 3.6 V35mAIERASESupply current from DVCC during erase2.7 V/ 3.6 V37mAtCPTCumulative program timesee Note 12.7 V/ 3.6 V4mstCMEraseCumulative mass erase timesee Note 22.7 V/ 3.6 V200msProgram/Erase endurance104105cyclestRetentionData retention durationTJ = 25C100yearstWordWord or byte program time35tBlock, 0Block program time for 1st byte or word30tBlock, 1-63Block program time for each additional byte or wordsee Note 321tFTGtBlock, EndBlock program end-sequence wait timesee Note 36tFTGtMass EraseMass erase time5297tSeg EraseSegment erase time4819NOTES:1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programmingmethods: individual word/byte write and block write modes.2.The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/fFTG,max = 5297x1/476kHz). Toachieve the required cumulative mass erase time the Flash Controllers mass erase operation can be repeated until this time is met.(A worst case minimum of 19 cycles are required).3.These values are hardwired into the Flash Controllers state machine (tFTG = 1/fFTG).JTAG InterfacePARAMETERTESTCONDITIONSVCCMINNOMMAXUNITfTCKTCK input frequencysee Note 12.2 V05MHzfTCKTCK input frequencysee Note 13 V010MHzRInternalInternal pull-up resistance on TMS, TCK, TDI/TCLKsee Note 22.2 V/ 3 V256090kNOTES:1. fTCK may be restricted to meet the timing requirements of the module selected.2.TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.JTAG Fuse (see Note 1)PARAMETERTESTCONDITIONSVCCMINNOMMAXUNITVCC(FB)Supply voltage during fuse-blow conditionTA = 25C2.5VVFBVoltage level on TDI/TCLK for fuse-blow: F versions67VIFBSupply current into TDI/TCLK during fuse blow100mAtFBTime to blow fuse1msNOTES:1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switchedto bypass mode.? ? ? ? ?SLAS272F JULY 2000 REVISED JUNE 200440POST OFFICE BOX 655303 DALLAS, TEXAS 75265APPLICATION INFORMATIONinput/output schematicport P1, P1.0 to P1.7, input/output with Schmitt-triggerP1.0/TACLK .P1IN.xModule X INPad LogicInterruptFlagEdgeSelectInterruptP1SEL.xP1IES.xP1IFG.xP1IE.xP1IRQ.xENDSetENQP1OUT.xP1DIR.xP1SEL.xModule X OUTDirection ControlFrom Module0101P1.7/TA2PnSel.xPnDIR.xDir. CONTROLFROM MODULEPnOUT.xMODULE X OUTPnIN.xMODULE X INPnIE.xPnIFG.xPnIES.xP1Sel.0P1DIR.0P1DIR.0P1OUT.0DVSSP1IN.0TACLKP1IE.0P1IFG.0P1IES.0P1Sel.1P1DIR.1P1DIR.1P1OUT.1Out0 signalP1IN.1CCI0AP1IE.1P1IFG.1P1IES.1P1Sel.2P1DIR.2P1DIR.2P1OUT.2Out1 signalP1IN.2CCI1AP1IE.2P1IFG.2P1IES.2P1Sel.3P1DIR.3P1DIR.3P1OUT.3Out2 signalP1IN.3CCI2AP1IE.3P1IFG.3P1IES.3P1Sel.4P1DIR.4P1DIR.4P1OUT.4SMCLKP1IN.4unusedP1IE.4P1IFG.4P1IES.4P1Sel.5P1DIR.5P1DIR.5P1OUT.5Out0 signalP1IN.5unusedP1IE.5P1IFG.5P1IES.5P1Sel.6P1DIR.6P1DIR.6P1OUT.6Out1 signalP1IN.6unusedP1IE.6P1IFG.6P1IES.6P1Sel.7P1DIR.7P1DIR.7P1OUT.7Out2 signalP1IN.7unusedP1IE.7P1IFG.7P1IES.7Signal from or to Timer_A? ? ? ? ?SLAS272F JULY 2000 REVISED JUNE 200441POST OFFICE BOX 655303 DALLAS, TEXAS 75265APPLICATION INFORMATIONinput/output schematic (continued)port P2, P2.0 to P2.2, P2.6, and P2.7 input/output with Schmitt-triggerP2IN.xP2OUT.xPad LogicP2DIR.xP2SEL.xModule X OUTEdgeSelectInterruptP2SEL.xP2IES.xP2IFG.xP2IE.xP2IRQ.xDirection ControlP2.0/ACLK0101InterruptFlagSetENQModule X INENDBus KeeperCAPD.XP2.1/TAINCLKP2.2/CAOUT/TA0P2.6/ADC12CLKP2.7/TA00: Input1: Outputx: Bit Identifier 0 to 2, 6, and 7 for Port P2From ModulePnSel.xPnDIR.xDir. CONTROLFROM MODULEPnOUT.xMODULE X OUTPnIN.xMODULE X INPnIE.xPnIFG.xPnIES.xP2Sel.0P2DIR.0P2DIR.0P2OUT.0ACLKP2IN.0unusedP2IE.0P2IFG.0P2IES.0P2Sel.1P2DIR.1P2DIR.1P2OUT.1DVSSP2IN.1INCLKP2IE.1P2IFG.1P2IES.1P2Sel.2P2DIR.2P2DIR.2P2OUT.2CAOUTP2IN.2CCI0BP2IE.2P2IFG.2P2IES.2P2Sel.6P2DIR.6P2DIR.6P2OUT.6ADC12CLKP2IN.6unusedP2IE.6P2IFG.6P2IES.6P2Sel.7P2DIR.7P2DIR.7P2OUT.7Out0 signalP2IN.7unusedP2IE.7P2IFG.7P2IES.7Signal from Comparator_ASignal to Timer_ASignal from Timer_AADC12CLK signal is output of the 12-bit ADC module? ? ? ? ?SLAS272F JULY 2000 REVISED JUNE 200442POST OFFICE BOX 655303 DALLAS, TEXAS 75265APPLICATION INFORMATIONinput/output schematic (continued)port P2, P2.3 to P2.4, input/output with Schmitt-triggerBus KeeperP2IN.3P2OUT.3Pad LogicP2DIR.3P2SEL.3Module X OUTEdgeSelectInterruptP2SEL.3P2IES.3P2IFG.3P2IE.3P2IRQ.3Direction ControlFrom ModuleP2.3/CA0/TA10101InterruptFlagSetENQModule X INENDP2IN.4P2OUT.4Pad LogicP2DIR.4P2SEL.4Module X OUTEdgeSelectInterruptP2SEL.4P2IES.4P2IFG.4P2IE.4P2IRQ.4Direction ControlFrom ModuleP2.4/CA1/TA20101InterruptFlagSetENQModule X INENDComparator_A+Reference BlockCCI1BCAFCAREFP2CACAEXCAREFBus KeeperCAPD.3CAPD.4To Timer_A30: Input1: Output0: Input1: OutputPnSel.xPnDIR.xDIRECTIONCONTROLFROM MODULEPnOUT.xMODULE X OUTPnIN.xMODULE X INPnIE.xPnIFG.xPnIES.xP2Sel.3P2DIR.3P2DIR.3P2OUT.3Out1 signalP2IN.3unusedP2IE.3P2IFG.3P2IES.3P2Sel.4P2DIR.4P2DIR.4P2OUT.4Out2 signalP2IN.4unusedP2IE.4P2IFG.4P2IES.4Signal from Timer_A? ? ? ? ?SLAS272F JULY 2000 REVISED JUNE 200443POST OFFICE BOX 655303 DALLAS, TEXAS 75265APPLICATION INFORMATIONinput/output schematic (continued)port P2, P2.5, input/output with Schmitt-trigger and Rosc function for the basic clock moduleP2IN.5P2OUT.5Pad LogicP2DIR.5P2SEL.5Module X OUTEdgeSelectInterruptP2SEL.5P2IES.5P2IFG.5P2IE.5P2IRQ.5Direction ControlP2.5/Rosc0101InterruptFlagSetENQDCORModule X INENDto01DC GeneratorBus KeeperCAPD.5DCOR: Control Bit From Basic Clock ModuleIf it Is Set, P2.5 Is Disconnected From P2.5 PadInternal toBasic ClockModuleVCC0: Input1: OutputFrom ModulePnSel.xPnDIR.xDIRECTIONCONTROLFROM MODULEPnOUT.xMODULE X OUTPnIN.xMODULE X INPnIE.xPnIFG.xPnIES.xP2Sel.5P2DIR.5P2DIR.5P2OUT.5DVSSP2IN.5unusedP2IE.5P2IFG.5P2IES.5? ? ? ? ?SLAS272F JULY 2000 REVISED JUNE 200444POST OFFICE BOX 655303 DALLAS, TEXAS 75265APPLICATION INFORMATIONinput/output schematic (continued)port P3, P3.0 and P3.4 to P3.7, input/output with Schmitt-triggerP3.0/STE0P3IN.xModule X INPad LogicENDP3OUT.xP3DIR.xP3SEL.xModule X OUTDirection ControlFrom Module0101P3.4/UTXD0P3.5/URXD00: Input1: Outputx: Bit Identifier, 0 and 4 to 7 for Port P3P3.6/UTXD1P3.7/URXD1PnSel.xPnDIR.xDIRECTIONCONTROLFROM MODULEPnOUT.xMODULE X OUTPnIN.xMODULE X INP3Sel.0P3DIR.0DVSSP3OUT.0DVSSP3IN.0STE0P3Sel.4P3DIR.4DVCCP3OUT.4UTXD0P3IN.4UnusedP3Sel.5P3DIR.5DVSSP3OUT.5DVSSP3IN.5URXD0P3Sel.6P3DIR.6DVCCP3OUT.6UTXD1P3IN.6UnusedP3Sel.7P3DIR.7DVSSP3OUT.7DVSSP3IN.7URXD1Output from USART0 moduleOutput from USART1 module in x14x(1) configuration, DVSS in x13x configurationInput to USART0 moduleInput to USART1 module in x14x(1) configuration, unused in x13x configuration? ? ? ? ?SLAS272F JULY 2000 REVISED JUNE 200445POST OFFICE BOX 655303 DALLAS, TEXAS 75265APPLICATION INFORMATIONinput/output schematic (continued)port P3, P3.1, input/output with Schmitt-triggerP3.1/SIMO0P3IN.1Pad LogicENDP3OUT1P3DIR.1P3SEL.1(SI)MO00101DCM_SIMOSYNCMMSTESTCFrom USART0SI(MO)0To USART00: Input1: Outputport P3, P3.2, input/output with Schmitt-triggerP3.2/SOMI0P3IN.2Pad LogicENDP3OUT.2P3DIR.2P3SEL.20101DCM_SOMISYNCMMSTESTCSO(MI)0From USART0(SO)MI0To USART00: Input1: Output? ? ? ? ?SLAS272F JULY 2000 REVISED JUNE 200446POST OFFICE BOX 655303 DALLAS, TEXAS 75265APPLICATION INFORMATIONinput/output schematic (continued)port P3, P3.3, input/output with Schmitt-triggerP3.3/UCLK0P3IN.3Pad LogicENDP3OUT.3P3DIR.3P3SEL.3UCLK.00101DCM_UCLKSYNCMMSTESTCFrom USART0UCLK0To USART00: Input1: OutputNOTE: UART mode:The UART clock can only be an input. If UART mode and UART function are selected, the P3.3/UCLK0 is alwaysan input.SPI, slave mode:The clock applied to UCLK0 is used to shift data in and out.SPI, master mode:The clock to shift data in and out is supplied to connected devices on pin P3.3/UCLK0 (in slave mode).? ? ? ? ?SLAS272F JULY 2000 REVISED JUNE 200447POST OFFICE BOX 655303 DALLAS, TEXAS 75265APPLICATION INFORMATIONinput/output schematic (continued)port P4, P4.0 to P4.6, input/output with Schmitt-triggerP4.0/TB0 .P4IN.xModule X INPad LogicENDx: bit identifier, 0 to 6 for Port P4P4OUT.xP4DIR.xP4SEL.xModule X OUTDirection ControlFrom Module0101Bus KeeperTBOUTHiZP4.6/TB60: Input1: OutputP5SEL.7Module X IN?PnSel.xPnDIR.xDIRECTIONCONTROLFROM MODULEPnOUT.xMODULE X OUTPnIN.xMODULE X INP4Sel.0P4DIR.0P4DIR.0P4OUT.0Out0 signalP4IN.0CCI0A / CCI0BP4Sel.1P4DIR.1P4DIR.1P4OUT.1Out1 signalP4IN.1CCI1A / CCI1BP4Sel.2P4DIR.2P4DIR.2P4OUT.2Out2 signalP4IN.2CCI2A / CCI2BP4Sel.3P4DIR.3P4DIR.3P4OUT.3Out3 signalP4IN.3CCI3A / CCI3BP4Sel.4P4DIR.4P4DIR.4P4OUT.4Out4 signalP4IN.4CCI4A / CCI4BP4Sel.5P4DIR.5P4DIR.5P4OUT.5Out5 signalP4IN.5CCI5A / CCI5BP4Sel.6P4DIR.6P4DIR.6P4OUT.6Out6 signalP4IN.6CCI6ASignal from Timer_BSignal to Timer_BFrom P5.7? ? ? ? ?SLAS272F JULY 2000 REVISED JUNE 200448POST OFFICE BOX 655303 DALLAS, TEXAS 75265APPLICATION INFORMATIONinput/output schematic (continued)port P4, P4.7, input/output with Schmitt-triggerP4.7/TBCLKP4IN.7Timer_B,Pad LogicENDP4OUT.7P4DIR.7P4SEL.70101TBCLK0: Input1: OutputDVSSport P5, P5.0 and P5.4 to P5.7, input/output with Schmitt-triggerP5.0/STE1P5IN.xModule X INPad LogicENDP5OUT.xP5DIR.xP5SEL.xModule X OUTDirection ControlFrom Module0101P5.4/MCLKP5.5/SMCLKP5.6/ACLKP5.7/TBOUTHx: Bit Identifier, 0 and 4 to 7 for Port P50: Input1: OutputPnSel.xPnDIR.xDir. CONTROL FROM MODULEPnOUT.xMODULE X OUTPnIN.xMODULE X INP5Sel.0P5DIR.0DVSSP5OUT.0DVSSP5IN.0STE.1P5Sel.4P5DIR.4DVCCP5OUT.4MCLKP5IN.4unusedP5Sel.5P5DIR.5DVCCP5OUT.5SMCLKP5IN.5unusedP5Sel.6P5DIR.6DVCCP5OUT.6ACLKP5IN.6unusedP5Sel.7P5DIR.7DVSSP5OUT.7DVSSP5IN.7TBOUTHiZNOTE: TBOUTHiZ signal is used by port module P4, pins P4.0 to P4.6. The function of TBOUTHiZ is mainly useful when used with Timer_B7.? ? ? ? ?SLAS272F JULY 2000 REVISED JUNE 200449POST OFFICE BOX 655303 DALLAS, TEXAS 75265APPLICATION INFORMATIONinput/output schematic (continued)port P5, P5.1, input/output with Schmitt-triggerP5.1/SIMO1P5IN.1Pad LogicENDP5OUT.1P5DIR.1P5SEL.10101DCM_SIMOSYNCMMSTESTC(SI)MO1From USART1SI(MO)1To USART10: Input1: Outputport P5, P5.2, input/output with Schmitt-triggerP5.2/SOMI1P5IN.2Pad LogicENDP5OUT.2P5DIR.2P5SEL.20101DCM_SOMISYNCMMSTESTCSO(MI)1From USART1(SO)MI1To USART10: Input1: Output? ? ? ? ?SLAS272F JULY 2000 REVISED JUNE 200450POST OFFICE BOX 655303 DALLAS, TEXAS 75265APPLICATION INFORMATIONinput/output schematic (continued)port P5, P5.3, input/output with Schmitt-triggerP5.3/UCLK1P5IN.3Pad LogicENDP5OUT.3P5DIR.3P5SEL.30101DCM_SIMOSYNCMMSTESTCUCLK1From USART1UCLK1To USART10: Input1: OutputNOTE: UART mode:The UART clock can only be an input. If UART mode and UART function are selected, the P5.3/UCLK1 directionis always input.SPI, slave mode:The clock applied to UCLK1 is used to shift data in and out.SPI, master mode:The clock to shift data in and out is supplied to connected devices on pin P5.3/UCLK1 (in slave mode).? ? ? ? ?SLAS272F JULY 2000 REVISED JUNE 200451POST OFFICE BOX 655303 DALLAS, TEXAS 75265APPLICATION INFORMATIONinput/output schematic (continued)port P6, P6.0 to P6.7, input/output with Schmitt-triggerP6.0 . P6.7P6IN.xModule X INPad LogicENDP6OUT.xP6DIR.xP6SEL.xModule X OUTDirection ControlFrom Module0101Bus KeeperTo ADCFrom ADC0: Input1: Outputx: Bit Identifier, 0 to 7 for Port P6Note: Not implemented in the MSP430x14x1 devicesNOTE: Analog signals applied to digital gates can cause current flow from the positive to the negative terminal. The throughput current flows ifthe analog signal is in the range of transitions 01 or 10. The value of the throughput current depends on the driving capability of thegate. For MSP430, it is approximately 100 A.Use P6SEL.x=1 to prevent throughput current. P6SEL.x should be set, even if the signal at the pin is not being used by the ADC12.PnSel.xPnDIR.xDIR. CONTROLFROM MODULEPnOUT.xMODULE X OUTPnIN.xMODULE X INP6Sel.0P6DIR.0P6DIR.0P6OUT.0DVSSP6IN.0unusedP6Sel.1P6DIR.1P6DIR.1P6OUT.1DVSSP6IN.1unusedP6Sel.2P6DIR.2P6DIR.2P6OUT.2DVSSP6IN.2unusedP6Sel.3P6DIR.3P6DIR.3P6OUT.3DVSSP6IN.3unusedP6Sel.4P6DIR.4P6DIR.4P6OUT.4DVSSP6IN.4unusedP6Sel.5P6DIR.5P6DIR.5P6OUT.5DVSSP6IN.5unusedP6Sel.6P6DIR.6P6DIR.6P6OUT.6DVSSP6IN.6unusedP6Sel.7P6DIR.7P6DIR.7P6OUT.7DVSSP6IN.7unusedNOTE: The signal at pins P6.x/Ax is used by the 12-bit ADC module.? ? ? ? ?SLAS272F JULY 2000 REVISED JUNE 200452POST OFFICE BOX 655303 DALLAS, TEXAS 75265APPLICATION INFORMATIONJTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt-triggerTDITDOTMSTCKTestJTAG&EmulationModuleBurn & TestFuseControlled by JTAGControlled by JTAGControlledby JTAGDVCCDVCCDVCCDuring Programming Activity andDuring Blowing of the Fuse, PinTDO/TDI Is Used to Apply the TestInput Data for JTAG CircuitryTDO/TDITDI/TCLKTMSTCKFuseDVCC? ? ? ? ?SLAS272F JULY 2000 REVISED JUNE 200453POST OFFICE BOX 655303 DALLAS, TEXAS 75265APPLICATION INFORMATIONJTAG fuse check modeMSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuityof the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse checkcurrent, ITF, of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TDI/TCLK pin to ground if the fuse is not burned.Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system powerconsumption.Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if theTMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse checkmode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR thefuse check mode has the potential to be activated.The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (seeFigure 16). Therefore, the additional current flow can be prevented by holding the TMS pin high (defaultcondition).Time TMS Goes Low After PORTMSITFITDI/TCLKFigure 16. Fuse Check Mode Current: MSP430F13x, MSP430F14x(1)IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,enhancements, improvements, and other changes to its products and services at any time and to discontinueany product or service without notice. Customers should obtain the latest relevant information before placingorders and should verify that such information is current and complete. All products are sold subject to TIs termsand conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale inaccordance with TIs standard warranty. Testing and other quality control techniques are used to the extent TIdeems necessary to support this warranty. Except where mandated by government requirements, testing of allparameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design. Customers a
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