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高频正弦信号发生器的设计与制作,高频,正弦,信号发生器,设计,制作
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杭 州 电 子 科 技 大 学毕业设计（论文）任务书学 院电子信息学院专 业电子信息工程班 级06041813学生姓名马希通指导教师刘国华学 号06072108一、题目高频正弦信号发生器的设计与制作二、内容和要求（理、工科类：包括需达到的技术指标、规定阅读的文献、应完成的图纸和说明书等；经管类：包括实习期间应收集的实际材料、论文要求解决的问题及重点、规定阅读的文献等） 自己搜集、查找、学习有关锁相环和锁相频率合成的文献资料，了解锁相环和锁相频率合成的主要芯片和工作原理。设计一个基于锁相频率合成技术的高频正弦信号发生器。 1. 设计内容 搜集和学习有关锁相频率合成和压控振荡器（VCO）的资料。翻译相关英文文献，写出锁相频率合成的文献综述。设计高频信号发生器的电路原理图，PCB印制电路版图，能够实现高频正弦信号的稳定输出。 2. 技术指标 (1) 电源电压：9V； (2) 输出频率：40MHz60MHz； (3) 输出信号幅度最大值500mv； (4) 信号频率稳定度（10分钟内）：优于10-4；随毕业论文应提供完整的元器件清单、电路原理图、设计图纸、PCB印制电路版图、实物照片、测试过程和测试结果数据。3. 参考文献1 刘国华，林弥，王光义编著.通信电路实验与设计. 北京：科学出版社，2009.82 曾兴雯，刘兴安，陈建高频电子线路T北京：高等教育出版社，20043 谢嘉荃，宣月清，冯军电子线路T北京：高等教育出版社，20074 何希才，尤克振荡电路的设计与应用T北京：科学出版社，2008(3)5 王长江，王志军变容二极管调频器获得线性调频的条件J：四川职业技术学院学报；2006年04期6 阎石数字电子技术基础M北京：北京航空航天大学出版社，2008，(03)三、起止日期及进度安排起止日期：09年10月12日 至10年3月24日进度安排：序号时间内容12009.10.122009.10.21搜集、整理相关资料22009.10.222009.11.3撰写开题报告32009.11.4开题报告会42009.11.5-2009.11.25熟悉PLL以及VCO电路52009.11.26-2009.12.16确立硬件电路应用方案62009.12.17-2009.1.6文献综述和外文文献翻译72009.1.7-2009.1.21硬件、软件成型、调试、检测、改进完善82009.1.22-2010.3.14撰写毕业论文92010.3.15-2010.3.19论文盲审及修改102010.3.24毕业答辩指导教师（签名）2009年10月26日四、教研室审查意见：教研室主任（签名）2009年10月28日学院批准人（签名）2009年10月28日杭州电子科技大学毕业设计（论文）外文文献翻译毕业设计（论文）题目高频正弦信号发生器的设计与制作翻译题目自动调整带宽的PLL/DLL的设计学 院电子信息学院专 业电子信息工程姓 名马希通班 级06041813学 号06072108指导教师刘国华自动调整带宽的PLL/DLL的设计Jaeha Kim,Member,IEEE,Mark A.Horowitz,Fellow,IEEE,and Gu-Yeon Wei,Member,IEEE摘要：带自动调整带宽功能的锁相环（PLL）和延迟锁相环（DLL）在很大的频率、电压、温度范围内总能表现最优的特性，下面就对此类的PLL/DLL的设计方法作简要说明。 为了得到每个电路参数对PLL/DLL性能的直接影响，我们得到PLL/DLL的离散时间开环动态参数的模型，这个模型描绘了输出变量对应于采样误差的变化，同时我们自定义了一些关于开环增益的自适应带宽的标准，以取代观察传统的闭环参数n和。为了应用这些标准，我们首先必须了解电流泵的缩放方程和滤波器的等效阻抗可以完成PLL/DLL对带宽的自动调整。 我们证明了自动调整带宽的PLL/DLL、自调节的PLL/DLL、电源调节的PLL/DLL可以在压控振荡器（VCO）的控制下完成小信号对大信号的自动跟踪，只有当电压的变化范围要高过阈值电压Vth时，才可以维持n/ref和是一个常数。这篇文章还展示了如何从开环动态响应来估计开环动态参数。介绍：PLL/DLL的动态参数随着中心频率的变化而发生相应的变化。例如，一个线性锁相环PLL4，即自适应带宽锁相环能在工艺，温度和电压变化的情况下，保持环路带宽和参考频率是一个固定的比例、保持阻尼因子恒定不变。实现自适应带宽的锁相环技术已出现PLL1 - 3中。本文试图找出这些不同的电路技术设计的共同的基本原则，并提供一个为那些希望使用100nmCMOS技术设计一个自适应带宽的PLL/DLL 的人提供一个指导性的准则。具有带宽自动调整功能的PLL/DLL 图(1) 在宽频内自适应带宽对固定带宽可以自动跟踪工作频率，因此可以在很大的范围内表现最优的性能。PLL/DLL本质上是一个数据采样系统，其中环路带宽必须至少高于10倍的参考频率，以避免不稳定的采样延时。对于固定带宽的锁相环，带宽必须限制是10倍以上所需的最低工作频率，如图(1)所示。因此，当频率低于此最小频率时，锁相 环的带宽应该超过其可能的最大值。由于带宽决定了环路的响应速率，从而可以减小自身产生的噪声，例如压控振荡器（VCO）的噪声，这就意味着PLL在高频率的范围内会有次优的表现。相反，可自动调整带宽的PLL在所有的频率点上均能表现最佳的性能。图2（a）VCO频率的变化（b）由于过程、电压、温度的变化导致VCO增益的变化自动调整带宽的PLL即使是在目标带宽很窄的情况下，同样可以达到很好的性能。过程、电压、温度的变化可能导致环路参数的不确定性，例如压控振荡器（VCO）的电压、电流泵的电流、反馈零点频率都可能发生变化。这些不确定性促使设计者必须选择一个合适的工作点来保证在所有的条件下电路的参数都保持稳定，然而在大多数情况下，这个合适的工作点是不存在的。图2（a）描述了一个典型的CMOS工艺的环路振荡器以及过程、电压、温度的变化引发中心频率的变化的快慢情况。因此，振荡器必须有一个足够宽的调谐范围，以确保工作在目标频率上，尽管它只是一个点。图2（b）上环路带宽的改变是由于压控振荡器增益的改变而引起的，而最终是由于压控振荡器调谐曲线的改变而引起的。为了确保稳定性，设计者必须在最坏的情况下选择带宽，在这种情况下，压控振荡器最大的斜率点处会在所有的条件下，变现次优的性能。换言之，这些设计余量用于减小参考频率的抖动幅度。我们意识到带带宽自动调整功能的PLL调整电流泵电路和环路滤波器的等效阻抗来适应压控振荡器的工作条件，因此压控振荡器的增益被有效的补偿了。由于期望的频率落在很窄的范围内，因此设计者必须减小余量并且设计适合高带宽的工作条件。本文为带宽自动调整功能的PLL/DLL制订了一些标准，并且基于这些标准发表了一些文献。描述PLL/DLL最流行的方式就是使用闭环的参数，例如带宽、阻尼因数。尽管他们对环路的频率响应和稳定性有直接的影响，PLL电路的设计者常常觉得把闭环的标准和开换的标准联系在一起是异常繁琐的，例如为了保证PLL可以工作很宽的频率范围内找到环路滤波器和电荷泵电路的比例需求是很麻烦的。因此第二部分介绍了关于PLL/DLL新的动态模型，这个模型关注的是相位差，而不是输入输出的相位的传递函数。本文所介绍的PLL/DLL标准用开环参数表示。第三部分应用关于PLL/DLL的新的标准，导出电荷泵电路和环路滤波器的阻抗的需求，来满足带宽自动调整的功能。第四部分讨论了使用自偏置锁相环和电源调节锁相环的共同设计规则，每一种方法都可以使用不同的电路技术来实现锁相环的带宽自动调整功能。分析结果显示他们的设计原则实际上和确切的要求相似，并且满足大摆度制度的标准。我们将在新一代CMOS工艺的基础上讨论追求宽频率范围的极限或者是理论上的电压差。第五部分讨论从时域瞬态来计算或模拟开环参数的方法。图3（a）系统框图（b）二阶线性PLL的连续时间模型图(3)a是一个二阶线性锁相环的框图。锁相环是一个反馈系统，它试图去匹配压控振荡器的输出相位out.输出频率out，和参考时钟的输出相位ref输出频率ref。在倍频输出情况下，out和out是压控振荡器的vco和vco的1/N,因此当out锁定ref时，vco等于Nref，因此vco和vco更具实际的意义，我们将替代out和out作为分析时的输出变量。我们将会看到out和out的使用会消除倍频因子N的感念，从而使分析更加简单。如果需要的话，vco和vco可以等效为Nout和Nout。实际上存在很多锁相环的实现方法，从模拟实现到完全的数字实现，但是所有的高于两阶的锁相环都具有下面的动态控制。一个鉴相器（PD）测量ref和out的相位差，环路滤波器（LF）把压控振荡器（VCO）的输出频率out做适当的调节以减小这个相位差。首先，环路滤波器（LF）典型的使用了积分控制，他设置压控振荡器（VCO）的基本频率I是相位差时间积分的KI倍。积分控制抑制静态相位偏置因为只有当相位差eer为零的时候环路才会保持稳定。然而，积分控制会导致控制的不稳定，因为它产生了两个极点，第二个极点是由于频率通过压控振荡器到相位的积分。为了使环路稳定，环路滤波器（LF）也需要零点补偿或一个比例控制，增加一个p，如图3（b）所示。这个p是电路相位差的一个比例倍数。这I和P的和共同构成了压控振荡器（VCO）的输出频率out。高于两阶的锁相环需要在子环路上增加额外的零点或及极点，然而高阶的零极点对环路的带宽几乎不构成影响。因此二阶锁相环的分析足够讨论带宽自动调整功能的标准。固有频率n和阻尼因子可以从锁相环的闭环传递函数中得出，积分系数KI，比例系数KP是环路的全部的增益，包括鉴相器、环路滤波器、压控振荡器、还有分数因子1/N。首先开环传递函数定义为GPLL(s)=out(s)/err(s)。 因此，闭环传递函数HPLL(s)=out(s)/ref(s),也就是： 第二个公式我们可以推导出n、与KP、KI的关系如下：带自动带宽调整功能的PLL必须在特定的ref范围内保持n/ref和为恒定值。等式三揭示了开环增益KP和KI必须满足的关系， 和 ，尽管这些条件对于一个可自动调整带宽的PLL来说足够啦，但我们会进行更多的分析，从带宽调整的标准去找出开环的直观的意义。开环传递函数GPLL(s)指出了相位差err和输出相位out的关系。尽管err在图3中被描述成连续时间特性，但是时间上他是离散采样得到的值。对于二进制的时钟波形，由于相位检测器可以在每一个时钟边沿检测时间差，因此每一个周期都会进行一次相位的比较。据此可知，锁相环本质上是一个离散时间系统，每一个参考周期进行一次相位差的采样。从这个角度来看，我们可以在离散时间域里面重新描述PLL的开环传递函数，如公式（4）所示。其中Tref定义为参考时钟周期，也就是2/ref。相似的，如果结果相位当作输出的话，比例控制同样也可以看作是离散时间的综合。 另一种观点就是在每一个周期环路滤波器都会更新频率I和相位P以确保他们同当前的采样误差err成正比。因此I和I是n和n的响应的集合。公式（6）是一个开环动态函数，它对相位和频率的变化进行建模，而这个变化是由采样误差决定的。由于和，公式（6）将变成因此这个方程和自适应带宽的标准，即恒定的n/ref和阻尼因子，指出了/ref的相对变化和PLL的相位的变化可以由相位差err来决定。把那些常量记作C和C响应的我们得到可自动调整带宽的PLL的动态方程自动调整带宽标准的这种形式，即恒定的开环增益（C和C）可以从闭环频的定义也可以扩展到更高级的PLL，也同样可以用这种方法来估算带宽。对更高阶的PLL也可以从开环响应来估算C和C，这种技术将在第五部分描述。就像第三部分提到的那样，开环动态方程式（8）为优化电路的参数提供了一个好的解决方案，也可以帮助解决频率的范围问题自动调整带宽标准的这种形式，即恒定的开环增益（C和C）可以从闭环频的定义也可以扩展到更高级的PLL，也同样可以用这种方法来估算带宽。对更高阶的PLL也可以从开环响应来估算C和C，这种技术将在第五部分描述。就像第三部分提到的那样，开环动态方程式（8）为优化电路的参数提供了一个好的解决方案，也可以帮助解决频率的范围问题。 记住开环参数到闭环参数是非常容易的：和，例如C为0.02，C为0.7，相应的n/ref为0.056，为0.99，这样就设计出了一个很宽的PLL。参考文献：1 J. G. Maneatis,”Low-jitter process-indeendent DLL and PLL based on self-biased techniques,” IEEE J. Solid-State Circuits, vol. 31, pp.1723-1732,Nov.1996.2 S. Sidiropoulos, D. Liu, J, Kim,G. Wei, and M, Horowitz,”Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers,” in IEEE Symp.VLSI Circuits Dig. Tech,Papers,June 2000,pp.124-127.3 J.Kim and M.A.Horowitz,”Adaptive-supply serial links with sub-1 V operationand per-pin clock recovery .”IEEE J.Solid-state Circuits,vol.37.pp.1403-1413, Nov,2002.4 F.M.Gardner, Paselock Tehniques,2nd ed.New York:Wiley,1979.5 R.E.Best,Phase-Locked Loops:Design ,Simulation,and Applications,3rd ed.New York:McGraw-Hill,1997.6 B.Tazavi,Ed,Monolithic Phase-Locked Loops and Clock Recovery Circuits;Theory and Design,Piscataway,NJ:IEEE Press 1996. 7 B.Razavi,Ed,Phase-Locking in Hign-Prefirmance Systems:From Device to Architectures.Piscataway ,NJ: IEEE press ,2003.860IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 11, NOVEMBER 2003Design of CMOS Adaptive-Bandwidth PLL/DLLs:A General ApproachJaeha Kim, Member, IEEE, Mark A. Horowitz, Fellow, IEEE, and Gu-Yeon Wei, Member, IEEEAbstractA phase-locked loop (PLL) and delay-locked loop(DLL) design with adaptively adjusting bandwidth enablesoptimal performance over a wide frequency range and acrossprocess, voltage, and temperature variations. A design method-ology of such adaptive-bandwidth PLLs and DLLs is described.To assess the impact of each circuit parameter directly, we derivea discrete-time, open-loop dynamic model of the PLL/DLL thatcharacterizes the change in output variables in response to thesampled error and we express the adaptive-bandwidth criteria interms of the open-loop gains, instead of the traditional closed-loopparameters,and. Applying these criteria, we derive scalingequations for the charge-pump current and filter resistance thatachieve adaptive bandwidth in charge-pump PLL/DLLs. Weshow that previously published adaptive-bandwidth PLL/DLLs,a self-biased PLL/DLL and a regulated-supply PLL/DLL, relyon the small-signal conductance tracking the large-signal con-ductance of the voltage-controlled oscillator/voltage-controlleddelay-line and, thus, sustain constant?andonly if thevoltage swing is sufficiently higher than the device thresholdvoltage?. The paper also presents procedures to estimate theopen-loop parameters from an open-loop impulse response of thePLL/DLL.Index TermsAdaptive bandwidth, delay-locked loop (DLL),phase-locked loop (PLL).I. INTRODUCTIONADAPTIVE-BANDWIDTH phase-locked loops (PLLs)and delay-locked loops (DLLs) refer to a class of PLLsand DLLs that scale their loop dynamics proportionally withthe reference frequency 1, 2. For example, in a linear PLL4, an adaptive-bandwidth PLL maintains a constant ratiobetween the loop bandwidth and the reference frequencyand keeps the damping factor constant regardless of process,temperature, and voltage variation. Various circuit techniquesto realize adaptive bandwidth have been published 13.This paper tries to find a common underlying design principlein those different circuit techniques and to provide a guidelinefor those who wish to design an adaptive-bandwidth PLL orDLL in a sub100-nm CMOS technology.An adaptive bandwidth that tracks with the operating fre-quency helps sustain the best jitter performance of the PLL orDLL over a wide frequency range. A PLL or DLL is inher-ently a sampled-data system, in which the loop bandwidth mustManuscript received May 1, 2003; revised July 2003. This paper was recom-mended by Guest Editors M. Perrott and G.-Y. Wei.J.KimiswithSeoulNationalUniversity,Seoul151-742,Korea(email:jaehaisdl.snu.ac.kr).M. A. Horowitz is with the Department of Electrical Engineering, StanfordUniversity, Stanford, CA 94305 USA.G.-Y. Wei is with the Department of Electrical Engineering, Harvard Univer-sity, Cambidge, MA 02138 USA.Digital Object Identifier 10.1109/TCSII.2003.819120Fig. 1.Adaptive bandwidth versus fixed bandwidth in case of a widefrequency range. The fixed bandwidth results in performance loss in most ofthe range.be at least a decade below the reference frequency in order toavoidinstabilityduetothesamplingdelay.Inafixed-bandwidthPLL, the bandwidth is thus constrained to be a decade belowthe lowest desired operating frequency, as depicted in Fig. 1.Therefore, at frequencies other than this minimum, the PLL hasa bandwidth lower than its possible maximum. Since the band-width determines a loops response rate to reject self-inducednoise, e.g., voltage-controlled oscillator (VCO) noise, it meansthatthePLLhassuboptimalperformanceintheupperfrequencyrange. On the other hand, in an adaptive-bandwidth PLL, thebandwidth scales with the operating frequency and maintainsoptimal performance of the PLL for all frequencies.The adaptive bandwidth helps achieve the best performanceeven when the target frequency range is narrow. Variations inprocess, voltage, and temperature can lead to uncertainties inloop parameters such as VCO gain, charge-pump current, andfeedforward zero frequency. These uncertainties force a de-signer to choose a conservative operating point that guaranteesstable operation for all conditions, which is unfortunately notthe best-performance point in most cases. Fig. 2(a) illustratesthe case with a typical CMOS ring oscillator. Variations inprocess, voltage, and temperature cause the VCO frequencyto vary by a factor ofbetween its slowest and fastestconditions. Therefore, the oscillator must have a wide enoughtuning range to ensure operation at the target frequency, evenif the target frequency is just a single point. Fig. 2(b) plotsthe variation in loop bandwidth due to variation in VCO gain,which is derived from the slope of the VCO tuning curvesin Fig. 2(a). To ensure stability, the designer must select thebandwidth based on the worst-case conditionin this case, thefastest cornerresulting in suboptimal bandwidths for all othercases. In other words, the design margins to cope with uncer-tainties reduce the best jitter performance achievable. As weshall see, an adaptive-bandwidth PLL adapts the charge-pumpcurrent and loop-filter (LF) resistance to the VCOs operating1057-7130/03$17.00 2003 IEEEAuthorized licensed use limited to: HANGZHOU DIANZI UNIVERSITY. Downloaded on November 21, 2009 at 02:04 from IEEE Xplore. Restrictions apply. KIM et al.: DESIGN OF CMOS ADAPTIVE-BANDWIDTH PLL/DLLS861(a)(b)Fig. 2.(a) Variation in VCO frequency. (b) Variation in VCO gain due toprocess, voltage, and temperature (PVT) variations. Design margins to ensurestability against uncertainties cause performance loss.condition, so that the variation in VCO gain is effectivelycompensated. Since the expected bandwidth then falls into anarrower range, the designer can reduce margin and design forhigher bandwidth operation.This paper derives the criteria for adaptive-bandwidthPLL/DLLs and examines the implementations published inliterature based on these criteria. The most popular way ofdescribing a PLL or DLL is to use closed-loop parameters suchas bandwidthand damping factor. Despite their directimplication on the loops frequency response and stability,PLL circuit designers often find it cumbersome to translateclosed-loop criteria into open-loop criteria. For example, it ischallenging to find the scaling requirement for the charge-pumpcurrent or the LF resistance to maintain adaptive-bandwidthoperation over a wide frequency range. Thus, Section II intro-duces a new dynamical model for a PLL/DLL that focuses onthe open-loop transfer function between the phase error and theresulting change in output variables, rather than the closed-looptransfer function between the input and output phases. Theadaptive-bandwidth criteria are then expressed in open-loopparameters,and.Section III applies these new criteria to the charge pumpPLL/DLL and derives the requirements for scaling thecharge-pump current and the LF resistance to satisfy the con-ditions necessary for adaptive-bandwidth operation. Section IVthen discusses the common design principles used in theself-biased PLL 1 and the regulated-supply PLL 2, each ofwhich implements adaptive bandwidth using different circuittechniques. The analysis reveals that their design principles arein fact approximations to the exact requirements and meet thecriteria only in the large-swing regime. We will discuss theirlimitations as a wider frequency range is pursued or as the(a)(b)Fig.3.(a)Blockdiagram.(b)Continuous-time modelofasecond-orderlinearPLL.nominal supply voltage drops in future generations of CMOStechnology. Section V comments on the methods to estimatethe open-loop parameters from the time-domain transientsobtained from simulation or measurement.II. DISCRETE-TIMEOPEN-LOOPCRITERIA OFADAPTIVE-BANDWIDTHPLL/DLLSFig. 3(a) is a block diagram of a second-order linear PLL 4.A PLL is a feedback system that tries to match the VCO outputphaseand frequencyto those of the reference clock,and, respectively. In case of frequency multiplication,theoutputsandaresomefractions()oftheVCOsdirect outputsand. Thus, whenis locked to,is equal toand the frequency is multiplied. Whileandare of more practical interest, we will instead useandas the output variables in the analysis. As we willsee, the use ofandeliminates the explicit notationof the multiplication factorand keeps the analysis simple. Ifdesired,andcan be easily calculated asand, respectively.A variety of PLL implementations exists, ranging fromanalog implementations to fully digital ones 7, 8, but mostlinear PLLs with orders higher than two have the followingcontrol dynamics. A phase detector (PD) measures the errorbetween the two phases,and. Upon the detectionof the phase error, a LF makes appropriate adjustmentson the VCO frequencyto reduce this error. First, the LFtypically employs an integral control, which sets the VCObase frequencyto a time-integral of the past phase errorscaled by a gain. The integral control helps suppress staticphase offset because it ensures that the loop will not settle untilreaches zero. However, the integral control can make thefeedback unstable since it results in two poles placed at dc,where the second pole comes from the time-integration of thefrequency to a phase via the VCO. To stabilize this feedbackloop, the LF also needs a compensating zero or a proportionalcontrol, which adds another term, as shown in Fig. 3(b).The frequencyis set proportional to the current phase error.The sum ofandconstitutes the VCO frequency.PLLs with orders higher than two may have additional polesAuthorized licensed use limited to: HANGZHOU DIANZI UNIVERSITY. Downloaded on November 21, 2009 at 02:04 from IEEE Xplore. Restrictions apply. 862IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 11, NOVEMBER 2003and/or zeros in their LFs to gain extra control over subcyclebehaviors, for instance, frequency spurs 11, 13. However,since those high-order poles/zeros are placed well beyond theloop bandwidth to ensure stability, they have little effect ondetermining the loop bandwidth. The second-order analysisprovided here should suffice to derive the necessary criteria foradaptive-bandwidth operation.The natural frequencyand the damping factorare de-rived from the closed-loop transfer function of the PLL 14.Note that the integral and the proportional gains, denoted asandin Fig. 3(b), are the total gains around the loop, in-cluding the gains of the phase detector, the LF, the VCO, andalso the dividing ratio. First, the open-loop transfer func-tion of the PLL, defined as, is(1)Then,theclosed-looptransferfunctionis(2)From the definition shown in the last line of (2), we can expressandin terms ofand(3)An adaptive-bandwidth PLL requires thatandareheld constant over the desired range of. Equation (3) thenimplies that the open-loop gainsandmust satisfy therelations,and, re-spectively. Although these conditions are sufficient to design anadaptive-bandwidth PLL, we will carry out a little more anal-ysis to find an intuitive meaning of this open-loop form of theadaptive-bandwidth criteria.The open-loop transfer functionin (1) character-izes the relationship between the phase errorand the outputphase. Althoughwas described as a continuous-timequantity in Fig. 3(b), it is in fact a discrete-time sampled value.For binary clock waveforms, since the phase detector can de-tect a timing error only by comparing the clock edge positions,the phase comparison can occur only once per cycle. Therefore,the PLL is essentially a discrete-time system that acts upon thesampled phase error every reference cycle.From this point of view, we can redescribe the open-looptransferfunctionofthePLLinadiscrete-timedomain,asshownin Fig. 4. The integral controlcan be re-garded as a discrete-time summation(4)Fig. 4.A discrete-time PLL modeling the changes in phase?and infrequency?of each cycle due to the sampled phase error?.whereis the reference cycle time,. Similarly, theproportional controlcan also be regardedas a discrete-time summation if the resulting phaseis considered as the output(5)An alternative view is that in each cycle the LF updates the fre-quencyand phaseby quantities that are proportional tothe current sampled error(6)Thenandare the sums of the pasts ands,respectively. The output phaseis the sum ofand thetime-integral of,.Equation (6) is an open-loop dynamic equation that modelsthe change in phase and frequency due to each sampled phaseerror. Sinceand, (6) becomes(7)Therefore, this equation and the adaptive-bandwidth criteria,i.e., the constantratio and damping factor , imply thatthe relative change in frequencyand the change inphaseof an adaptive-bandwidth PLL are equivalent to thephase errorscaled by some constant values. By denotingtheseconstantsasand,respectively,wegettheopen-loopdynamic equation of the adaptive-bandwidth PLL as below(8)whereis defined asandas.This new form of adaptive bandwidth criteria, i.e., constantopen-loop gains,and, implies that instead of estimatingandfrom the closed-loop frequency response, one canverify an adaptive-bandwidth PLL by measuring the changes inthe output phase and frequency made upon a unit phase error.Although these open-loop gains were derived from a second-order analysis, their definitions can also be extended to higher-Authorized licensed use limited to: HANGZHOU DIANZI UNIVERSITY. Downloaded on November 21, 2009 at 02:04 from IEEE Xplore. Restrictions apply. KIM et al.: DESIGN OF CMOS ADAPTIVE-BANDWIDTH PLL/DLLS863(a)(b)Fig. 5.DLL dynamic models. (a) Continuous-time model. (b) Discrete-timemodel characterizing?of each cycle.order PLLs and used to evaluate their bandwidths. The method-ology for estimatingandfrom the open-loop responseand the case with higher order PLLs will be described in Sec-tion V. As will be seen in Section III, this open-loop dynamicequation of (8) also provides better intuition to optimize thecircuit parameters and helps derive the exact scaling require-ments for those circuit parameters that achieve adaptive band-width over the desired frequency range of operation.It is handy to remember the formulas that convert theopen-loop parameters back to the closed-loop parameters:and. For instance,of 0.02 andof 0.7 corresponds toof 0.056 andof0.99, a design target of most wide-bandwidth PLLs.We can derive similar criteria for adaptive-bandwidth DLLs.A DLL modeled in Fig. 5(a) locks the delay of a voltage-con-trolled delay-line (VCDL)to a desired delay. Themain difference from a PLL is that the VCDL does not involvean integration. Therefore, the feedback loop is stable with onlyan integral control that suppresses static delay offset. The re-sulting system is then a first-order system with only one statevariable,.Let us first find the bandwidthfrom the continuous-timeDLL model shown in Fig. 5(a). With integral control alone,is equal to a gaintimes the time-integral of the pastdelay error,. As in the PLL analysis, thisgainencompassesthegaincontributionsfromthephasede-tector, LF, and VCDL. The closed-loop transfer function of theDLL,is then(9)From (9), we find that. Fora DLLto satisfy the adap-tive-bandwidth criteria, i.e., constantratio, the loopgainmust scale proportionally with reference frequency.Like a PLL, a DLL is also a discrete-time system since itsphase detector can measure the delay difference only onceevery cycle. Therefore, we can derive a discrete-time open-looptransfer function similar to (8). The integral control is convertedFig. 6.A charge-pump PLL. The main parameters that must vary to keepadaptive bandwidth are?and?.to a discrete-time summation ofand thechange indue to each sampled delay error is(10)Therefore, the adaptive-bandwidth criterion of constantimplies that the gainin the following open-loopdynamic equation must be constant(11)whereisequalto.Ateachcycle,theoutputdelayis adjusted bywhich is equal to the sampled delay errorscaled by. Aof 0.5 corresponds to aratioof 0.08.III. ADAPTIVE-BANDWIDTHCHARGE-PUMPPLL/DLLSSection II derived the adaptive-bandwidth criteria expressedin open-loop gains: constantandfor PLL and constantfor DLL. This section applies these criteria to charge-pumpPLLs and DLLs, one of the most popular forms of PLL/DLLimplementations today. For the case of charge-pump PLLs, themain parameters that determine the open-loop gains are thecharge-pump currentand filter resistance. A job of anadaptive-bandwidth PLL designer is therefore to select propervalues forand, and to design circuits that scale theseparameters with respect to. This section derives the scalingrequirements forandof adaptive-bandwidth PLL/DLLsand Section IV will discuss how these scalings can be realizedwith CMOS circuits.A block diagram of a charge-pump PLL is shown in Fig. 65. The LF consists of a charge pump followed by a passiveRC filter. The phase-frequency detector generates pulses whosewidths are proportional to the phase error and the charge pumpdumps either positive or negative charge onto a capacitor ( )forthedurationofthosepulses.Whileinactive,thechargepumphas infinite output impedance, which enables a robust realiza-tion of pure integration (the pole located at dc). Therefore, theAuthorized licensed use limited to: HANGZHOU DIANZI UNIVERSITY. Downloaded on November 21, 2009 at 02:04 from IEEE Xplore. Restrictions apply. 864IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 11, NOVEMBER 2003loop gain at dc is ideally infinite and the gain-related static off-setsareeliminated.1Theresistance( )inserieswiththecapac-itor implements the proportional control (the zero). During thecharge transfer, the transient current through the resistor resultsin a voltage whose aggregate effect over a full period is propor-tional to the present phase error.Toapplytheopen-loopadaptive-bandwidthcriteriain(8),thechange in frequencyand that in phaseare first calcu-lated(12)(13)whereis the charge-pump current,is the LF resistance,is the LF capacitance,is the VCO gain (in rad/s/V),andis the dividing ratio of the clock divider. Since adaptive-bandwidth operation requires the two open-loop gainsandbe constant, we get the fol-lowing scaling requirements onandas the reference fre-quencyvaries.First,from(12)andconstant,thecharge-pumpcurrentmust satisfy(14)assuming that the loop capacitanceis held at a fixed value.In other words,and the charge-pumpcurrent must scale with the rate of change of the finalfor a unit change in the reference cycle. Second, by applying(13) and (14), and constant, the scaling requirement on thefilter resistanceis obtained(15)The filter resistancemust vary proportional to the referencecycle. Equations (14) and (15) are, therefore, the key require-ments for an adaptive-bandwidth charge-pump PLL.A charge-pump DLL has a similar configuration to a PLLshowninFig.6,exceptthattheLFdoesnothaveaseriesresistor.1The maincauses of the remaining static offsets in charge-pump PLLs are themismatch between the up and down currents of the charge pump, the mismatchwithin the phase-frequency detector, and the mismatch between the referenceclock path and the feedback clock path.Every cycle, the phase detector generates a pulse whose widthis equal to the delay error and the charge pump either charges ordischarges a capacitorwhile the pulse is asserted. Changeson the voltage across the capacitorthen result in theadjustment of the VCDL delay. The change in delaydueto a delay erroris calculated(16)whereis theVCDLgaindefinedas.2Then, the constantrequired for an adaptive-bandwidth DLL implies that the charge-pump currentmustsatisfy(17)This criterion (17) is in fact an identical criterion to (14), espe-cially if the PLL and the DLL use the same buffer stages fortheir VCO and VCDL, respectively. The circuit techniques toscale the charge-pump current for an adaptive-bandwidth PLLcan thus be applied directly to an adaptive-bandwidth DLL.IV. CMOS IMPLEMENTATIONEXAMPLESSection IV-A and IV-B visit two CMOS adaptive-bandwidthPLLs published in the literature: a self-biased PLL with sym-metric-load buffers 1 and a regulated-supplyPLL with CMOSinverters 2. Both designs rely on scaling the charge-pump cur-rent as the control voltageto compensate for changeswith VCO gain. Equations (14) and (15) will help us under-stand why these designs work and what can be a challenge aswe stretch these designs to next-generation CMOS processes.We will find that the assumptions that these designs are basedon break down as the voltage swing in the buffer gets closerto the device threshold voltage. Therefore, the operatingrange that satisfies adaptive bandwidth will shrink as the nom-inal supply of the CMOS process continues to scale down rela-tiveto; someways toget aroundtheselimits are suggested.Discussions focus mainly on the design of the adaptive-band-width PLLs, since the criterion (17) for the adaptive-bandwidthDLL is identical to that of the PLL in (14).A. Self-Biased PLLs With Symmetric-Load BuffersFig. 7 presents the VCO of the self-biased PLL proposed in1.Eachbufferisadifferentialstagewithaso-calledsymmetricload,whichisaparallelcombinationofadiode-connectedpMOSdevice and a near-triode pMOS device with its gate connectedto. Within the output voltage range betweenand,thesymmetricloadexhibitssymmetric character-isticsandthusanearlyconstantoutputresistance,averagedthroughout the swing. This attribute enables the buffer to rejecthigh-frequency noise by equalizing the rising and falling outputtransitions and, thus, reduces jitter 9.A replica-feedback biasing circuit in Fig. 7 dynamicallycontrols the voltage swing and the bias current of the oscillator.2The negative sign is from the assumption that the delay?decreases as?increases, for being consistent with the VCO case where the frequency?increases as?increases.Authorized licensed use limited to: HANGZHOU DIANZI UNIVERSITY. Downloaded on November 21, 2009 at 02:04 from IEEE Xplore. Restrictions apply. KIM et al.: DESIGN OF CMOS ADAPTIVE-BANDWIDTH PLL/DLLS865Fig. 7.The VCO and the replica-feedback biasing circuit of the self-biasedPLL.A feedback amplifier adjusts the bias currentso that thevoltage drop across the symmetric load, i.e., the voltage swingof the VCO buffers, is equal to. A half-bufferreplica in the bias generator translatestothrough a diode-connected device, whose output resistancemimics that of the symmetric load conducting at its full swing.Therefore, replica-feedback biasing dynamically maintains therelation,against process, temperature, and supply variations. Since thecontrol voltage and the voltage swing are both referenced to thehigher supply rail, their potential differences with,and,will be used to simplify the forthcoming expressions.Given the voltage swingand bias current, the VCOs oscillation period, is expressed as(18)whereis the total load capacitance seen by the buffer stagesin the ring oscillator. The frequency of the self-biased VCO isthustunablebyvaryingtheeffectiveresistanceofthesymmetricload, with the control voltage.The self-biasedPLL claims constantratio byscalingthe charge-pump currentproportionally with the VCO biascurrentand inversely proportional to the multiplicationfactor11(19)This is realized by replicating the bias currentvia a pro-grammable current mirror, which sets the ratio betweenandaccording to the desiredratio and the multipli-cation factor. The PLL in 1 even uses a charge pump whichhas an almost identical topology to a VCO buffer in order tomaximize matching between the two current scalings.To verify if (19) indeed achieves constant, we com-bine (14) and (18) to derive the scaling requirement on(20)(a)(b)Fig. 8.(a)?characteristics of the symmetric load. (b) Scalings of?and?and the variation of their ratio,? ?.We find that (19) is in fact an approximation that satisfiesadaptive bandwidth only if the relative transconductance ofthe symmetric load, isconstant within the operating range. The relative transconduc-tance is also a ratio between the small-signal transconductanceand the large-signal conductance. Also, note that instead of detecting, the self-bi-ased PLL adjustsbased on, since it is equal towhen the PLL is locked.Fig. 8 plots thecharacteristics of the symmetric loadand its small-signal and large-signal conductances,and. The small-signal transconductance is the tangentialslopeonthe curvewhilethelarge-signalconductanceistheslope of the line connecting the origin and the operating point.As seen in Fig. 8(b), the ratio, i.e., the gap be-tween the two curves on a log-scale plot, is fairly constant forhigh. However, since thecurve is offset from theorigin due to the device threshold, as the voltage swingapproaches,decreases at a faster rate thanAuthorized licensed use limited to: HANGZHOU DIANZI UNIVERSITY. Downloaded on November 21, 2009 at 02:04 from IEEE Xplore. Restrictions apply. 866IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 11, NOVEMBER 2003(a)(b)Fig. 9.(a)? ?ratio. (b) Damping factor?of the self-biased PLL as afunction of the voltage swing?. As a result, the ratio of conductancesin-creases as the voltage swing decreases.Fig. 9(a) plots the resulting bandwidth-to-frequency ratioof the self-biased PLL simulated in a 0.25- m CMOStechnology, which has a nominal supply of 2.5 V andof0.55 V. In the low-swing regime, the increasing conductanceratio makes the charge-pump current scaling that follows (19)higher than the ideal current in (20). Therefore, theratio, which is fairly constant in the high-swing regime, grad-ually increases as the voltage swing approaches the devicethreshold. This unwanted variation inratio willbe more pronounced in finer-feature CMOS processes, sincethe nominal supply is scaling down at a faster rate than thethreshold voltage is 12. On the other hand, when the voltageswing istoolarge,thetransistors falloutofthesaturationregionand the oscillator no longer satisfies (18). Hence, decreasingthe supply voltage also limits the high end of the operatingrange. The frequency range where theratio is keptconstant is thus shrinking with CMOS process scaling and thisposes a challenge for future adaptive-bandwidth PLL designs.There are a few possible ways to address this challenge.First, since the difference betweenandscalingsis basically due to the device threshold, one can thinkof using zero-threshold devices for the symmetric load. Thenthe-offset of thecurve in Fig. 8(a) is removed andthe variation inis reduced. Second, to copewith the effective reduction in frequency range, one can adda programmable output divider that automatically adjusts itsdividing ratio depending on. For example, whenislow, the dividing ratio is increased so that the VCO itselfcan be kept oscillating at a high frequency, while the dividerprovides the lower-frequency clock. However, this schemerequires a priori information onor a frequency detector(based on a known fixed reference) that selects an appropriatedividing ratio for each.An adaptive-bandwidth PLL must also scale the filter resis-tanceto keep the damping factorconstant. Equation (15)says thatmust scale proportionally withor with.Sincefrom (18), it follows thatmust scale as(21)The self-biased PLL again approximateswith.An additional charge-pump injects a currentonto the nodein Fig. 7, while the PD error pulse is asserted. This currentthen develops a voltage offset betweenand,which is proportional to. Therefore, the self-bi-ased PLL effectively scales the filter resistanceas the small-signal resistance of the replica symmetric load,. Thedependency ofon the multiplication factorcan be imple-mented either bya programmable current mirror thatadjusts theratio between the second charge-pump currentandorbyasampledfeedforwardfilterwhichholdsthesamplederrorcharge for the entire reference cycle11. The latter ismore desirable to reduce the reference spur on the output clock,especially ifis large.Similar to the case of the charge-pump current, the approxi-mationmade by the self-biased PLL is validonly in the high-swing regime. Fig. 9(b) plots the variation ofthe damping factor of a self-biased PLL with respect to.While the damping factoris fairly constant for large voltageswings, it gradually increases as theapproaches.Since the nonideal scalings ofandare both due to thevariationintherelativetransconductanceofthesymmetricload, the aforementioned solutions can also help ex-tend the frequency range in which the damping factor is con-stant.B. Regulated-Supply PLLs With CMOS InvertersFig. 10 illustrates the VCO and its supporting bias gener-ator of a regulated-supply PLL, proposed in 2. The VCO ismade up of CMOS inverters and the bias generator is basicallya linear voltage regulator that controls the VCO supply to ad-just its frequency and to reject unwanted noise from the ex-ternalsupply.Similartotheself-biased PLL,thecontrol voltagesetsthedesiredvoltageswingoftheoscillatorand abiasgenerator adjusts the supplied currentso that the voltageswingmatches. Unlike a differential stage, aAuthorized licensed use limited to: HANGZHOU DIANZI UNIVERSITY. Downloaded on November 21, 2009 at 02:04 from IEEE Xplore. Restrictions apply. KIM et al.: DESIGN OF CMOS ADAPTIVE-BANDWIDTH PLL/DLLS867Fig. 10.The inverter-based VCO and its supporting biasing generator of theregulated-supply PLL.CMOS inverter does not dissipate constant current and thereexists no replica that can model the effective resistance of theVCO,. Therefore, the feedback-biasingcircuitry directly regulates the voltage swing of the oscillator,. Stabilizing its feedback can be an issue since boththe nodesandhave high capacitance. For ex-ample,thePLLin2sufficientlyreducedtheresistanceseenontomakethepoleassociatedwithnodedominant,and the PLL in 3 used a compensating capacitor to achievethe same. An inverter-based VCO has large voltage swings andsharptransitions,whichareadvantageousforreducingjitter9,butan inverterisinherently asingle-endedbufferthat cannotre-ject common-mode noise.The regulated-supply PLL achieves adaptive bandwidth byapplying similar design principles to those of the self-biasedPLL. Equations (18)(21) still hold for the regulated-supplyPLL except thatandin the expressions are re-placed withand, respectively, as both the con-trol voltage and the voltage swing are referenced to ground.The charge-pump currentis scaled proportional toand the filter resistanceis scaled proportional tousing a second charge-pump injecting current onto the node, whereis the small-signal conductance of theVCO seen at the node. As in the self-biased PLL, theregulated-supply PLL then achieves constantandbyrelying on the fact that the relative transconductanceis constant, i.e., thatis proportional to.Therefore, the regulated-supply PLL suffers from similarlimitations to those of the self-biased PLL. Fig. 11 plots thenormalized bandwidthand the damping factorof theregulated-supply PLL simulated in a 0.25- m CMOS process.Theratio andare fairly constant for high, butthe slope steepens asapproaches, for the same rea-sons as seen in the self-biased PLL. To mitigate this problem,the designers of the regulated-supply PLLs have varied thechannel lengths of the charge pumps current source devices tofind thecharacteristics that can minimize the variation in. However, this ad hoc solution is sensitive to processvariations, environmental conditions, and the correctness ofthe device models. Also, the highest voltage swing is limitedby the saturation requirement of the current source in the biasgenerator. Hence, as CMOS processes scale down and the-to-ratio decreases, the effective frequency range ofthe regulated-supply PLL will be narrowed.(a)(b)Fig. 11.(a) The? ?ratio and (b) the damping factor?of theregulated-supply PLL as a function of the voltage swing?.V. ESTIMATION OF THEPLL/DLL OPEN-LOOPPARAMETERSThis section describes how to estimate open-loop gains, i.e.,andfor PLLs andfor DLLs, from a time-domaintransient response, so that one can verify the bandwidth scalingafter the PLL/DLL is designed or fabricated. There are a fewother methods to characterize a PLL/DLL, but the time-domaincharacterization is the most general and can be used for bothsimulation and measurement results. For example, one can es-timate open-loop gains of a PLL by evaluating (12) and (13)after measuring the individual parameters such as VCO gain,charge-pumpcurrent,filterresistance,etc.Althoughstraightfor-ward in simulation where each PLL block is accessible, it is im-possibletomeasurethemafterthePLLhasbeen fabricated.An-other method is to measure the frequency response of the PLL,by sweeping the frequency of a sinusoidal phase noise sourcepurposely added to the input and observing the resulting outputphase. This approach is most commonly used in testing equip-ments, but it is time-consuming to do the same using SPICE10. Previous time-domain characterizations are mostly basedAuthorized licensed use limited to: HANGZHOU DIANZI UNIVERSITY. Downloaded on November 21, 2009 at 02:04 from IEEE Xplore. Restrictions apply. 868IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 11, NOVEMBER 2003on closed-loopresponses 6,where a certainlinearmodel is as-sumed and its model parameters are estimated by least-squaresfitting 16. Unfortunately, this estimation is often inaccurate,especially when the loop is overdamped. It is because the pur-pose of a feedback is to desensitize the systems response fromits parameter variations and, thus, the closed-loop response of awell-designed PLL is not a sensitive measure of its parameters.To overcome these limitations, this section introduces a methodof using the discrete-time, open-loop impulse function to char-acterize a PLL/DLL. First, ways to measure the open-loop im-pulse function of a PLL/DLL, directly or indirectly, are de-scribed. Then, we discuss how to estimate the open-loop gainsfrom the impulse response.One of the easiest ways to construct the impulse responsefrom the input/output transients is to use deconvolution. Oncethe time-sequences of the input phaseand the outputphaseare measured, the phase erroris calculated and the impulse transfer functionisderived by(22)where it is assumed that the system is causal and the input andoutput settle to 0 before15. The impulse response of aDLL can be derived similarly by usingandasthe input and output variables of the open-loop system, respec-tively. Since noise on the early samples of the input and outputsequences can largely distort, one can use an averaged re-sponse over multiple measurements when estimatingfromnoisy data.Alternatively, the impulse response of a PLL/DLL can be di-rectly measured in simulation or experimentally measured byphysically disabling the feedback momentarily. For example,the phase detector outputs can be gated so that the PLL/DLLruns in open-loop for a fixed time interval. The response of thePLL/DLLduringthatperiodisthentheimpulseresponsescaledby the error applied at the beginning of the period. Cautionshould be taken when measuring the open-loop response of aPLLsinceitsimpulseresponseisunbounded.ItmustbeensuredthatthePLLislocked beforedisablingthefeedbackandthatthedisablingperiodisshortenoughsothattheVCOfrequencydoesnot reach its tuning limits. On the other hand, no such caution isrequired for a first-order DLL since it has a bounded open-loopimpulseresponse.Ifnoinitialerrorisapplied,thesetupformea-suring the open-loop response can also measure the noise char-acteristics of the PLL, e.g., the phase noise of the VCO and itsclock buffers. By measuring the rms jitter correlations at dif-ferenttimepoints,itmayevenbepossibletoestimateeachnoisecontribution separately, e.g., the flicker noise and thermal noiseof the VCO 9.Note that the aforementioned methods to estimate theopen-loop impulse responsedo not assume a particularsystem order for the PLL/DLL under test. They assume only(a)(b)Fig. 12.Discrete-time, open-loop impulse responses of a PLL. (a) DLL. (b)Estimation of their loop parameters.that the PLL/DLL is a causal, linear time-invariant system.Thus, they can be generally applied to linear PLL/DLLswith orders higher than two and can even help identify theirhigh-order effects. The rest of this section describes how toestimate the open-loop gains from the impulse responseand how to identify some of the high-order effects.Fig. 12 shows the open-loop impulse responses of a PLL anda DLL obtained from simulation. In case of the PLL, the im-pulse error gives rise both to the phaseand frequency.The rise inappears as the initial rise inwhich staysconstant for the rest of the period. On the other hand, the riseinappears as a constant increase in. Therefore, fromthe impulse response shown in Fig. 12(a), we can estimate theopen-loop gainfrom the asymptotic slope ofandfrom the first nonzero sample subtracted by. The impulseresponse also reveals information on more complex behaviorof the PLL. For example, the position of the first nonzerosample indicates the loop delay of the PLL. Also, ifdoesnot increase linearly after its first nonzero sample, it means thatthe system contains higher order poles. With this additional in-formation on loop delay and higher order poles, more sophisti-cated stability analysis than just usingandis possible.The impulse response of a DLL is simpler than that of thePLL, as shown in Fig. 12(b). In response to an impulse error,the output delaychanges in a step. The gainis thenestimated from the size of this step. As in the PLL case, theloop delay and the high-order poles can be estimated from theposition of the first nonzerosample and the nonideal tran-sient of, respectively. The simplicity of the DLL behaviorAuthorized licensed use limited to: HANGZHOU DIANZI UNIVERSITY. Downloaded on November 21, 2009 at 02:04 from IEEE Xplore. Restrictions apply. KIM et al.: DESIGN OF CMOS ADAPTIVE-BANDWIDTH PLL/DLLS869makes it even possible to estimateandupon inspectionof the time-domain transient.VI. CONCLUSIONThis paper described a general design methodology foradaptive-bandwidth PLLs and DLLs. We first derived thediscrete-time, open-loop dynamic model of the PLL and DLLthat characterizes the change in the output variables in responseto the sampled error. The phase and frequency of the PLLis updated each cycle by the sampled phase error scaled byand, respectively. Similarly, the delay of the DLL isupdated each cycle by the sampled error scaled by. Theadaptive-bandwidth criteria are then expressed in terms ofthese open-loop gains, simply as constantandfor PLLsand a constantfor DLLs. By applying these criteria to thepreviously published charge-pump PLL/DLLs, we found thatthe self-biased PLL/DLL and the regulated-supply PLL/DLLrely on the small-signal transconductancetracking thelarge-signal transconductanceto satisfy the scalingequations of the charge-pump current and filter resistance in(14) and (15). This approximation, however, holds only whenthe voltage swing of the VCO/VCDL is sufficiently higher thanthe device thresholdand presents design challenges insub100-nm CMOS processes.Therefore, there remains a need to design a better adap-tive-bandwidth PLL/DLL that can extend to next generationsof CMOS processes. This paper suggested the use of zero-device to mitigate the tracking problems ofand, and the use of dynamically adjusting output dividers toconstrain the VCOs operating range. Direct implementationof (14) may be possible if realized digitally with some formof background calibration. In fact, digital or semidigital im-plementations are expected to prevail in the near future as thegate leakage of MOS capacitors and the subthreshold leakageof MOS switches pose potential problems to the use of cha
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