《EDA》综合设计报告封面.doc

EDA综合设计报告题目：键盘输入电路的设计班级：电信10303学号：10016727姓名：钟恒地点：工业中心EDA机房指导老师：曹艳2012年 05 月 01 日一 课题设计简介用4*4的行列结构可以构成有16个键的键盘。设行扫描信号为keydrv3keydrv0,列线按键盘输入信号为keyin3keyin0,然后通过按键扫描电路产生keydrv3keydrv0信号，同时有按键译码电路从keydrv3keydrv0信号和keyin3keyin0信号中译码出按键的键值。二 课题设计具体思路（包括设计的原理图，主要源程序及注释）时钟程序LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY clk_gen ISPORT( clk:IN STD_LOGIC; clk_scan:OUT STD_LOGIC);END clk_gen;ARCHITECTURE rtl OF clk_gen IS SIGNAL cnt:INTEGER RANGE 0 TO 119999; BEGINPROCESS(clk) BEGINIF clkEVENT AND clk=1 THEN IF cnt=cntHIGH THEN cnt=0; ELSE cnt=cntHIGH/2 THEN clk_scan=1; ELSE clk_scan=0; END IF;END IF; END PROCESS;END rtl;键盘扫描电路程序LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY keyscan IS PORT(clk_scan:IN STD_LOGIC; keydrv:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END keyscan;ARCHITECTURE behav OF keyscan IS CONSTANT s0:STD_LOGIC_VECTOR(3 DOWNTO 0):=1110; CONSTANT s1:STD_LOGIC_VECTOR(3 DOWNTO 0):=1101; CONSTANT s2:STD_LOGIC_VECTOR(3 DOWNTO 0):=1011; CONSTANT s3:STD_LOGIC_VECTOR(3 DOWNTO 0):=0111; SIGNAL present_state,next_state:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGINPROCESS(clk_scan)BEGINIF clk_scanEVENT AND clk_scan=1 THEN present_state next_state next_state next_state next_state next_state=s0; END CASE;END PROCESS;keydrv=present_state;END behav;键盘译码和按键标志产生电路LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY keydecoder_deb IS PORT( keyin,keydrv:IN STD_LOGIC_VECTOR(3 DOWNTO 0); clk,clk_scan:IN STD_LOGIC; keyvalue:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); keypressed,functionkey:OUT STD_LOGIC);END keydecoder_deb;ARCHITECTURE rtl OF keydecoder_deb IS SIGNAL temp:STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL temp_pressed,keypressed_asy:STD_LOGIC; SIGNAL q1,q2,q3,q4,q5,q6:STD_LOGIC;BEGIN tempkeyvalue=conv_std_logic_vector(1,4);temp_pressed=1;functionkeykeyvalue=conv_std_logic_vector(2,4);temp_pressed=1;functionkeykeyvalue=conv_std_logic_vector(3,4);temp_pressed=1;functionkeykeyvalue=conv_std_logic_vector(4,4);temp_pressed=1;functionkeykeyvalue=conv_std_logic_vector(5,4);temp_pressed=1;functionkeykeyvalue=conv_std_logic_vector(6,4);temp_pressed=1;functionkeykeyvalue=conv_std_logic_vector(7,4);temp_pressed=1;functionkeykeyvalue=conv_std_logic_vector(8,4);temp_pressed=1;functionkeykeyvalue=conv_std_logic_vector(9,4);temp_pressed=1;functionkeykeyvalue=conv_std_logic_vector(0,4);temp_pressed=1;functionkeykeyvalue=conv_std_logic_vector(10,4);temp_pressed=1;functionkeykeyvalue=conv_std_logic_vector(11,4);temp_pressed=1;functionkeykeyvalue=conv_std_logic_vector(12,4);temp_pressed=1;functionkeykeyvalue=conv_std_logic_vector(13,4);temp_pressed=1;functionkeykeyvalue=conv_std_logic_vector(14,4);temp_pressed=1;functionkeykeyvalue=conv_std_logic_vector(15,4);temp_pressed=1;functionkeytemp_pressed=0; END CASE;END PROCESS;PROCESS(clk_scan)BEGINIF clk_scanEVENT AND clk_scan=1 THEN q1=temp_pressed;q2=q1;q3=q2;q4=q3;END IF;keypressed_asy=q1 OR q2 OR q3 OR q4;END PROCESS;PROCESS(clk)BEGINIF clkEVENT AND clk=1 THEN q5=keypressed_asy;q6=q5; END IF;keypressed=q5 AND NOT(q6); END PROCESS;END rtl;分频器LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;ENTITY count IS PORT ( clk50: IN STD_LOGIC ; q1khz: OUT STD_LOGIC);END count; ARCHITECTURE bhv OF count IS BEGIN HZ:PROCESS(clk50)VARIABLE cout:INTEGER:=0;BEGINIF clk50EVENT AND clk50=1 THENcout:=cout+1;IF cout=199 THEN q1khz=0; ELSIF cout=399 THEN q1khz=1; ELSE cout:=0;END IF; END IF; END PROCESS;END bhv;三 实验结果分析（要附图）键盘扫描电路产生周而复始地扫描信号111011011011011