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毕业设计论文
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基于PLL信号发生器的设计论文资料论文10,毕业设计论文
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天津工程师范学院2006届毕业设计(论文)1 引言随着通信技术、数字电视、航空航天和遥控技术的不断发展，对频率源的频率稳定度、频谱纯度、频率范围和输出频率数量的要求也越来越高。为了提高频率的稳定度，经常采用晶体振荡器等方法来解决，但它很难产生多个频率信号。而频率合成技术，可以通过对频率进行加、减、乘、除运算，从一个高稳定度和高准确度的标准信号源，产生大量具有同样高稳定度和高准确度的不同频率。频率合成器是从一个参考频率中产生多种频率的器件。基于频率合成器的这以一特点，利用锁相式频率合成技术，可以制作高稳定度、宽频带的正弦波信号发生器。2 设计要求利用锁相环技术产生一个失真度小、频率从30MHz到100MHz的可调的正弦波信号。根据频率的不同选择不同步进的标准频率。当信号处于较低频率时，选择步进为1KHz的标准频率，此时它的最小误差不大于0.8%；当信号在较高的频率段时，选择以25 KHz为标准频率，它的最小误差不大于0. 5%。3方案论证与比较3.1 压控振荡器方案论证与选择 方案1：采用分立元件构成。利用低噪声场效应管，用单个变容二极管直接接入振荡回路作为压控器件。图3-1 压控振荡电路电路是电容三点式振荡器，如图3-1所示。该方法实现简单，但是调试困难，而且输出频率不易灵活控制1。方案2：采用压控振荡器和变容二极管，及一个LC谐振回路构成变容二极管压控振荡器。只需要调节变容二极管两端的电压，便可改变压控振荡的输出频率。由于采用了集成芯片，电路设计简单，系统可靠性高，并且利用锁相环频率合成技术可以使输出频率稳定度进一步提高。综上所述，方案2具有更优良的物性和更简单的电路构成，所以使用方案2作为本次设计的方案。3.2 频率合成器的设计方案论证与选择 方案1:采用直接式频率合成器技术,将一个或几个晶体振荡器产生的标准频率通过谐波发生器产生一系列频率,然后再对这些频率进行倍频、分频或混频，获得大量的离散频率。其组成框图如3-2所示。直接式频率合成器频率稳定度高，频率转换时间短，频率间隔小。但系统中需要用大量的混频器、滤波器等，体积大，易产生过多杂散分量，而且成本高、安装调试都比较困难。晶振谐波发生器分频器倍频器混频器fOut2fOut3fOut1图3-2 直接式频率合成方案2：采用模拟锁相式频率合成器技术，通过环路分频器降频，将VCO的频率降低，与参考频率进行鉴相。优点：可以得到任意小的频率间隔；鉴相器的工作频率不高，频率变化范围不大，较容易实现，带内带外噪声和锁定时间易于处理，频率稳定度与参考晶振的频率稳定度相同。缺点是分频率的提高要通过增加循环次数来实现，电路超小型化和集成化比较复杂2。方案3：采用数字锁相环式频率合成技术，由晶振、鉴频/鉴相（FD/PD）、环路滤波器（LPF）、可变分频器（N）和压控振荡器（VCO）组成。组成框图如图5-1所示。利用锁相环，将VCO的输出频率锁定在所需频率上。此电路可以很好地选择所需频率信号，抑制杂散分量，并且避免了大量的滤波器，采用大规模的集成芯片，与前两种方案相比可以简化频率合成部分的设计，有利于集成化和小型化。频率合成采用大规模集成PLL芯片BU2614，VCO选用MC1648； 综上所述，选择方案3即采用大规模PLL芯片BU2614和其他芯片构成数字锁相环式频率合成器。4 系统组成根据要求设计信号发生器，输出信号为正弦波。设计中采用锁相环式的频率合成技术，利用锁相环，使输出的正弦波频率与晶体振荡器的稳定度一样。控制部分采用单片机来完成，利用数码管对频率进行显示并对频率值进行存储。系统框图如图4-1所示数码显示频率AT89C51频率合成器BU2614低通滤波器压控振荡器键盘控制频率测量电路输出存储电路图4-1系统框图5 锁相环介绍5.1 锁相环的概念锁相环是指使高频振荡器的频率与基准频率的整数倍频率一致时所使用的电路。通常基准振荡器都使用晶体振荡器，所以高频振荡的频率稳定度与晶体振荡器相同。5.2 锁相环基本框图图5-1是锁相环的基本结构图，由VCO、相位比较器、基准频率振荡器、环路滤波器所组成的。在这里用表示基准频率振荡器频率，则表示VCO的频率。当压控振荡器的频率由于某种原因而发生变化时，必然相应地产生相位的变化。相位利用低通滤波器把误差信号变成直流电压比较与从而产生误差信号PD鉴相器（PD）VCO（电压控制振荡器）环路滤波器基准振荡频率振荡频率随VR而变化Ud(t)C(t)UR(t)0 图5-1 PLL的基本结构图的变化在鉴相器中与参考晶体振荡器的稳定相位相比较，使鉴相器输出一个与相位误差成比例的误差电压分量C(t)。C(t)用来控制压控振荡器中的压控元件参数，一般指的是变容二极管，而这压控元件又是VCO振荡回路的组成部分，结果压控元件电容量的变化将VCO的输出频率又拉回稳定值来。这样，VCO的输出频率稳定度即由参考晶体振荡器所决定。由频率与相位的关系可知，瞬时频率与瞬时相位的关系是：（t）= (5.1)= + (5.2)式中的为初始相位，为瞬时频率。由上面讨论可知加到鉴相器的两个振荡信号的频率差为： (5.3)为参考晶体振荡器的频率， 压控荡频率。此时的瞬时相位差为=+ (5.4)当两个振荡器的频率相等时它们的瞬时相位差是一个常数，即：= (5.5)（t）= =0 (5.6)亦即当两个振荡频率相等时，有相位差，无频率差3。5.3 鉴相器的时序图当与 的关系为。也就是VCO振荡频率低于时的状态。此时相位比较器的输出PD，如图5-2所示，产生正脉冲信号，使VCO的振荡频率提高的信号。反之，当是产生负脉冲。这一PD脉波信号经过回路滤波器的积分，便可图5-2相位/频率比较器的动作以得到直流电压VR，可以控制VCO电路。由于控制电压VR的变化，VCO振荡频率会提高。结果使得=在与的相位成为一致时，PD端子会成为高阻抗状态，使PLL被锁定(Lock)。5.4 捕捉带与通频带压控振荡器本来处于失锁状态时，由于环路的作用，使压控振荡频率逐渐向标准参考频率靠近，靠近到一定程度后，环路即能进入锁定。这一过程叫做捕捉过程。系统能捕捉最大的频率失谐范围称为捕捉带或捕捉范围。当环路已锁定后，如果由于某种原因引起频率变化，这种频率变化反映为相位变化，则通过环路的作用，可使VCO的频率和相位不断跟踪变化。这时环路即处于跟踪状态。环路所能保持跟踪的最大失谐频带称为同步带，又称为同步范围或锁定范围。6 单元电路的设计6.1 压控振荡器压控振荡就是在振荡电路中采用压控元件作为频率控制器件。压控器件一般是用变容二级管，它的电容量受到输入电压的控制，当输入电压变化，就引起了起振荡频率的变化。因此，压控振荡器事实是一种电压频率变换器。它的特性可用瞬时振荡频率与控制电压C之间的关系曲线来表示，如图6-1所示。图上的中心频率是在没有外加控制电压时的固有频率。在一定范围内，与C之间是线性关系。在线性范围内，这一线性可用下列方程来表示。（t）=+KrC(t) (6.1) Kr是特性曲线的斜率，称为VCO的增益或灵敏度，量纲为rad/s.V,它表示单位电压所引起的振荡角频率变化的大小。0OC 图6-1 压控振荡器的特性曲线6.1.1 压控振荡器MC1648MC1648是一个8引线双列直插的器件，内部电路图如图6-2所示。压控振荡电路由芯片内部Q8、Q5、Q4、Q1、Q7和Q6，10脚和12脚外接LC谐振回路组成正反馈的正弦振荡电路4，其振荡频率： （6.2）（6.3） 、分别为电感、电容大小，为变容二极管的电容量。图6-2 MC1648内部原理图6.1.2 压控振荡电路设计图6-3为压控振荡电路图。压控振荡器主要由压控振荡芯片MC1648和变容二图6-3 压控振荡电路极管MV209以及谐振回路构成。MC1648需要外接一个由电感和电容组成的并联谐振回路5。为达到最佳工作性能，在工作频率要求并联谐振回路的QL100。电源采用5V 的电压，振荡器的输出频率随加在变容二极管上的电压大小变化而变化。通过切换电源来切换电感量，从而改变振荡频率。 6.1.3 变容二级管与开关二级管切换电路 变容二极管变容二级管是一种特制的二级管，它的PN结电容变化范围比较大，正常工作时，变容二级管加反相电压，在其PN结上产生电荷存储，于是相当于一个电容，当反向电压改变时，变容二级管的结电容也发生相应的变化 6。变容二级管的结电容CVD和外加反向偏压UR的关系可用下式表示。（6.4） UR 是加在变容二极管的反向电压，CVD0为UR=0时 的结电容U0 是接触电位差；n是电容变化系数。 电感切换电路为了扩大频率的带宽，通过切换电源来切换电感。图6-4是开关二级管切换频段电路图。当开S连接+5V时，开关二级管VD2截止，电感L1和L2相加，电感量较大，对应于低频段VL；当S接向地时，VD2导通，L2被大电容2000pF短接，电感只剩下L1，电感量较小，对应于高频段 7。图6-4 电感切换电路6.2 锁相环式频率合成器的设计6.2.1 BU2614的管脚图与内部组成BU2614为16管脚芯片，其管脚图如图6-5所示。管脚Xout与Xin为外接晶振管脚，一般接75KHz晶体，主要产生标准频率和时钟信号；CE、CLK和DA端分别为使能、时钟和数据输入端，PD为相位比较输出。图6-5 BU2614管脚图BU2614是一种串行码输入的锁相频率合成器，它采用标准的I2C总路线结构，可以工作在整个FM波段，具有低噪声、低功耗、高灵敏度的特点，并具有中频检测功能。BU2614内部主要有相位比较器PD、可编程分频器、参考分频器、高稳定晶体振荡器及内部控制器组成。当单片机对BU2614送入一组数据， BU2614把接收到的数据与接收的信号频率进行比较后输出一个PD，该PD信号通过外部环路低通滤波后加在VCO上，通过VD的不断调整使VCO振荡频率锁定在与单片机送入数据相对应的频率上，实现频率锁定。在内部结构中，移位锁存器作用是把单片机送来的32位串行数据送入锁存器后进行串并转换，其中16位控制可编程分频器，3位控制参考分频器，其余为内部控制字。可编程分频器按照16位数据的控制要求，把 focs振荡频率信号经过参考分频之后的频率信号fd与fr在PD中进行比较，当 fd不等于fr时由PD输出电压VD控制VCO，使 focs稳定在确定频率上。参考分频器通过状态字中R 0、R1、R2三位数据把高稳定度振荡器产生的75kHz标准频率进行分频。可输出4个固定频率fr。PD把 fr和fd进行鉴相比较，PD的输出为高电平，低电平及高阻三态输出，通过外部LF实现锁相。6.2.2 输入、输出数据形式BU2614的串行数据输入靠CE、CLK和DA三个端子完成。时钟信号、数据信号和使能信号逻辑关系如图6-6所示。其中T1应大于15s， T2大于2s，时钟宽度应大于1s。数据和状态字共32位，从低位到高位依次排列为：D0、D1D 15 、图6-6 CLK、DATA、CE的逻辑关系P0、P1、P2 、*、*、*、*、CT、R0、R1、R 2、S、PS、*、GT、TS。其中D0到D 15、表示可变分频比的16位二进制数；*表示与控制不相关的位，可为1 或0；参考分频器产生的标准频率由R0、R1、R2三位数据控制，控制关系如表6-1所示。表6-1 R0、R1、R2与标准频率的关系 R0 R1 R2 标准频率 000 25KHz 0 11 3.25 KHz 1 0 0 6.25 KHz 1 1 0 1 KHz 111*PLL关闭P0、P1、P2为输出口控制数据，可使输出通道打开或关闭。置0时为通道打开。S和PS可用于收音机中FM和AM的选择。数据输出由CD端输出，此时CLK、CD与CE的逻辑关系与数据输入类似，只不过CE要求为低电平。CT、GT等用于频率测量与计数的控制。 6.2.3 BU2614的外围电路工作原理图6-7 锁相环控制电路图BU2614的外围电路如图6-7所示。5脚接收单片机的串行数据，该数据为12脚反馈频率FMOSC提供分频系数N，内部标准频率由串行数据位中的R0、R1、R2的取直确定。该设计选择R0、R1、R2 为000或110。当频率在25MHz到54MHz之间选择标准频率为1KHz，也就是R0、R1、R2为110；当频率在54MHz到110MHz之间选择标准频率为25 KHz。所选择的标准频率与/N比较，在PD输出相位比较信号，根据PD输出端的状态，从低通滤波器得到相应的直流电压，该电压直接控制压控振荡的变容二极管，从压控振荡输出的频率通过电容耦合反馈到BU2614中使环路锁定。6.3 低通滤波器图6-8 滤波电路图低通滤波器由三极管和RC电路组成，其电路图如图6-8所示。低通滤波器用于滤除鉴相器输出的误差电压中高频分量和瞬变杂散干扰信号，以获得更纯的控制电压，提高环路稳定性和改善环路跟踪性能和噪声性能。锁相稳频系统是一个相位反馈系统，其反馈目的是使VCO的振荡频率由自有偏差的状态逐步过渡到准确的标准值。而VCO如做调频源用，其瞬时频率总是偏离标准值的。振荡器中心频率不稳主要由温度、湿度、直流电源等外界因素引起，其变化是缓慢的，锁相环路只对VCO平均中心频率不稳定所引起的分量（处于低通滤波器通带之内）起作用，使其中心频率锁定在设定的频率上。因此，输出的调频波的中心频率稳定度很高8。6.4 电源切换电路设计 电源切换电路如图6-9所示。此控制电路是用三级管和光偶来控制输出的高低电平，使开关二级管截止或导通（见图6-4），从而来切换电感量。当P3.0输出高电平时，三极管导通，导致光偶导通，使输出为低电平；当P3.0为低电平时，三极管截止，导致光偶截止，使输出为高电平9。图6-9 电源切换电路6.5 电源电路设计电源电路如图6-10所示，由于低通需要12V的工作电压、MC1648、单片机、BU2614 图6-10 电源电路等工作电压需要5V，所以变压器的输出只需要接地和15V，考虑到高频信号产生电路和单片机共用一个电源会互相干扰，所以采取对单片机单独供电。由变压器出来的交流信号分别经过两个L7812CV,一路直接接到低通和L7805CV；另一路L7812CV的输出直接接到L7805CV，它的输出单独供给给单片机。在三端稳压管的输入输出端与地之间连接大容量的滤波电容，使滤掉纹波的效果更好，输出的直流电压更稳定。接小容量高频电容以抑制芯片自激，输出引脚端连接高频电容以减小高频噪声10。6.6 存储电路设计6.6.1 AT24C02管脚介绍AT24C02是美国ATMEL公司的低功耗CMOS串行EEPROM，它是内含2568位存储空间，具有工作电压宽（2.55.5V）、擦写次数多（大于10000次）、写入速度快（小于10ms）等特点。AT24C02的1、2、3脚是三条地址线，用于确定芯片的硬件地址。，第8脚和第4脚分别为正、负电源。第5脚SDA为串行数据输入/输出，数据通过这条双向I2C总线串行传送。第6脚SCL为串行时钟输入线。SDA和SCL都需要和正电源间各接一个5.1K的电阻上拉。第7脚需要接地。I2C总线是一种用于I2C器件之间连接的二线制总线。它通过SDA（串行数据线）及SCL（串行时钟线）两根线在连到总线上的器件之间传送信息，并根据地址识别每个器件：不管是单片机、存储器、LCD驱动器还是键盘接口11。6.6.2 I2C总线的特性 I2C总线的基本结构采用I2C总线标准的单片机或I2C器件，其内部不仅有I2C接口电路，而且将内部各单元电路按功能划分为若干相对独立的模块，通过软件寻址实现片选，减少了器件片选线的连接。CPU不仅能通过指令将某个功能单元电路挂靠或摘离总线，还可对该单元的工作状况进行检测，从而实现对硬件系统的既简单又灵活的扩展与控制。 双向传输的接口特性传统的单片机串行接口的发送和接收一般都各用一条线，而I2C总线则根据器件的功能通过软件程序使其可工作于发送或接收方式。当某个器件向总线上发送信息时，它就是发送器(也叫主器件)，而当其从总线上接收信息时，又成为接收器(也叫从器件)。主器件用于启动总线上传送数据并产生时钟以开放传送的器件，此时任何被寻址的器件均被认为是从器件。I2C总线的控制完全由挂接在总线上的主器件送出的地址和数据决定。总线上主和从(即发送和接收)的关系不是一成不变的，而是取决于此时数据传送的方向。SDA和SCL均为双向I/O线，通过上拉电阻接正电源。当总线空闲时，两根线都是高电平。连接总线的器件的输出级必须是集电极或漏极开路，以具有线“与”功能。I2C总线的数据传送速率在标准工作方式下为100kbit/s，在快速方式下，最高传送速率可达400kbit/s。 I2C总线上的时钟信号在I2C总线上传送信息时的时钟同步信号是由挂接在SCL时钟线上的所有器件的逻辑“与”完成的。SCL线上由高电平到低电平的跳变将影响到这些器件，一旦某个器件的时钟信号下跳为低电平，将使SCL线一直保持低电平，使SCL线上的所有器件开始低电平期。此时，低电平周期短的器件的时钟由低至高的跳变并不能影响SCL线的状态，于是这些器件将进入高电平等待的状态。当所有器件的时钟信号都上跳为高电平时，低电平期结束，SCL线被释放返回高电平，即所有的器件都同时开始它们的高电平期。其后，第一个结束高电平期的器件又将SCL线拉成低电平。这样就在SCL线上产生一个同步时钟。可见，时钟低电平时间由时钟低电平期最长的器件确定，而时钟高电平时间由时钟高电平期最短的器件确定。 数据的传送在数据传送过程中，必须确认数据传送的开始和结束。当时钟线SCL为高电平时，数据线SDA由高电平跳变为低电平定义为“开始”信号；当SCL线为高电平时，SDA线发生低电平到高电平的跳变为“结束”信号。开始和结束信号都是由主器件产生。在开始信号以后，总线即被认为处于忙状态；在结束信号以后的一段时间内，总线被认为是空闲的。I2C总线的数据传送格式是：在I2C总线开始信号后，送出的第一个字节数据是用来选择从器件地址的，其中前7位为地址码，第8位为方向位(R/W)。方向位为“0”表示发送，即主器件把信息写到所选择的从器件；方向位为“1”表示主器件将从从器件读信息。开始信号后，系统中的各个器件将自己的地址和主器件送到总线上的地址进行比较，如果与主器件发送到总线上的地址一致，则该器件即为被主器件寻址的器件，其接收信息还是发送信息则由第8位(R/W)确定。在I2C总线上每次传送的数据字节数不限，但每一个字节必须为8位，而且每个传送的字节后面必须跟一个认可位（第9位），也叫应答位（ACK）。每次都是先传最高位，通常从器件在接收到每个字节后都会作出响应，即释放SCL线返回高电平，准备接收下一个数据字节，主器件可继续传送。如果从器件正在处理一个实时事件而不能接收数据时，（例如正在处理一个内部中断，在这个中断处理完之前就不能接收I2C总线上的数据字节）可以使时钟SCL线保持低电平，从器件必须使SDA保持高电平，此时主器件产生1个结束信号，使传送异常结束，迫使主器件处于等待状态。当从器件处理完毕时将释放SCL线，主器件继续传送。当主器件发送完一个字节的数据后，接着发出对应于SCL线上的一个时钟（ACK）认可位，在此时钟内主器件释放SDA线，一个字节传送结束，而从器件的响应信号将SDA线拉成低电平，使SDA在该时钟的高电平期间为稳定的低电平。从器件的响应信号结束后，SDA线返回高电平，进入下一个传送周期。 总线竞争的仲裁总线上可能挂接有多个器件，有时会发生两个或多个主器件同时想占用总线的情况。例如，多单片机系统中，可能在某一时刻有两个单片机要同时向总线发送数据，这种情况叫做总线竞争。I2C总线具有多主控能力，可以对发生在SDA线上的总线竞争进行仲裁，其仲裁原则是这样的：当多个主器件同时想占用总线时，如果某个主器件发送高电平，而另一个主器件发送低电平，则发送电平与此时SDA总线电平不符的那个器件将自动关闭其输出级。总线竞争的仲裁是在两个层次上进行的。首先是地址位的比较，如果主器件寻址同一个从器件，则进入数据位的比较，从而确保了竞争仲裁的可靠性。由于是利用I2C总线上的信息进行仲裁，因此不会造成信息的丢失。6.6.3 存储电路的设计存储电路如图6-11所示，由于A0、A1、A2没有被AT24C02使用，所以它们可以不接或直接接VSS、VCC。WP接到VSS表示一般存储器的操作使能，即允许读和写整个存储器，如果接到VCC写操作禁止，整个存储器是写保护，读操作不受影响，在此把WP接VSS。因为SDA是一个双向的地址和数据传送端口，它是开漏极的端口，因此必须接一个上拉电阻到VCC。它读写操作是通过单片机的控制来实现的12。VCCVCC图6-11 存储电路6.7电子控制单元电路（ECU）ECU是控制系统的核心，其作用是对输入的信号进行检测、运算处理和逻辑判断，根据预先存储的控制程序和试验数据，向各执行器发出控制指令，控制各执行器的工作。89C51是控制系统内部的主要部分，它是整个控制系统的处理单元，AT89C51是一种带4K字节可编程可擦除只读存储器的低电压，高性能CMOS 8位微处理器，俗称单片机。该器件采用ATMEL高密度非易失存储器制造技术制造，与工业标准的MCS-51 指令集和输出管脚相兼容。由于将多功能8位CPU和闪烁存储器组合在单个芯片中，ATMEL的AT89C51是一种高效微控制器，为很多嵌入式控制系统提供了一种灵活性高且价廉的方案13。6.7.1 89C51单片机的管脚说明 VCC：供电电压（5V） GND：接地P0口：P0口为一个8位漏级开路双向I/O口。当P1口的管脚第一次写1时，被定义为高阻输入。P0能够用于外部程序数据存储器，它可以被定义为数据/地址的低八位。在FIASH编程时，P0口作为原码输入口，当FIASH进行校验时，P0输出原码，此时P0外部必须被拉高。 图6-12 MCS-51的引脚P1口：P1口是一个内部提供上拉电阻的8位双向I/O口。P1口管脚写入1后，被内部上拉为高，可用作输入，P1口被外部下拉为低电平时，将输出电流，这是由于内部上拉的缘故。在FLASH编程和校验时，P1口作为低八位地址接收。 P2口：P2口为一个内部上拉电阻的8位准双向I/O口。当P2口被写“1”时，其管脚被内部上拉电阻拉高，且作为输入。并因此作为输入时，P2口的管脚被外部拉低，将输出电流。这是由于内部上拉的缘故。P2口当用于外部程序存储器或16位地址外部数据存储器进行存取时，P2口输出地址的高八位。P2口在FLASH编程和校验时接收高八位地址信号和控制信号。 P3口：P3口管脚是8个带内部上拉电阻的准双向I/O口。当P3口写入“1”后，它们被内部上拉为高电平，并用作输入。作为输入，由于外部下拉为低电平，P3口将输出电流这是由于上拉的缘故。P3口也可作为AT89C51的一些特殊功能口，如下所示：P3口管脚备选功能P3.0 RXD（串行输入口）P3.1 TXD（串行输出口）P3.2 /INT0（外部中断0）P3.3 /INT1（外部中断1）P3.4 T0（记时器0外部输入）P3.5 T1（记时器1外部输入）P3.6 /WR（外部数据存储器写选通）P3.7 /RD（外部数据存储器读选通）RST：复位输入。要保持RST脚两个机器周期的高电平时间。当8051通电，时钟电路开始工作，系统即初始复位。常见复位电路如图6-13所示。图6-13 复位电路ALE/PROG：当访问外部存储器时，地址锁存允许的输出电平用于锁存地址的低位字节。在FLASH编程期间，此引脚用于输入编程脉冲。在平时，ALE端以不变的频率周期输出正脉冲信号，此频率为振荡器频率的1/6。/PSEN：外部程序存储器的选通信号。在由外部程序存储器取指期间，每个机器周期两次/PSEN有效。但在访问外部数据存储器时，这两次有效的/PSEN信号将不出现。/EA/VPP：当/EA保持低电平时，则在此期间外部程序存储器（0000H-FFFFH），不管是否有内部程序存储器。当/EA端保持高电平时，此间内部程序存储器。在FLASH编程期间，此引脚也用于施加5V编程电源（VPP）。 XTAL1：反向振荡放大器的输入及内部时钟工作电路的输入。XTAL2：来自反向振荡器的输出。 振荡器特性：XTAL1和XTAL2分别为反向放大器的输入和输出。该反向放大器可以配置为片内振荡器。石晶振荡和陶瓷振荡均可采用。如采用外部时钟源驱动器件，XTAL2应不接。有余输入至内部时钟信号要通过一个二分频触发器，因此对外部时钟信号的脉宽无图任何要求，但必须保证脉冲的高低电平要求的宽度。 MCS-51单片机的内部结构如图6-14所示。89C51单片机包含中央处理器、程序存储器(ROM)、数据存储器(RAM)、定时/计数器、并行接口、串行接口和中断系统等几大单元及数据总线、地址总线和控制总线等三大总线14。 中央处理器中央处理器(CPU)是整个单片机的核心部件，是8位数据宽度的处理器，能处理8位二进制数据或代码，CPU负责控制、指挥和调度整个单元系统协调的工作，完成 6-14 MCS-51内部结构运算和控制输入输出功能等操作。 数据存储器（RAM）89C51内部有128个8位用户数据存储单元和128个专用寄存器单元，它们是统一编址的，专用寄存器只能用于存放控制指令数据，用户只能访问，而不能用于存放用户数据，所以，用户能使用的的RAM只有128个，可存放读写的数据，运算的中间结果或用户定义的字型表。 程序存储器89C51共有4096个E2PROM，用于存放用户程序，原始数据或表格。 定时/计数器89C51有两个16位的可编程，以实现定时或计数产生中断用于控制程序转向。 并行输入输出口89C51共有4组8位I/O口(P0、 P1、P2或P3)，用于对外部数据的传输。 全双工串行口89C51内置一个全双工串行通信口，用于与其它设备间的串行数据传送，该串行口既可以用作异步通信收发器，也可以当同步移位器使用。 中断系统89C51具备较完善的中断功能，有两个外中断、两个定时/计数器中断和一个串行中断，可满足不同的控制要求，并具有2级的优先级别选择。 时钟电路89C51内置最高频率达12MHz的时钟电路，用于产生整个单片机运行的脉冲时序，但89C51单片机需外置振荡电容。单片机的结构有两种类型，一种是程序存储器和数据存储器分开的形式，即哈佛(Harvard)结构，另一种是采用通用计算机广泛使用的程序存储器与数据存储器合二为一的结构，即普林斯顿(Princeton)结构。INTEL的MCS-51系列单片机采用的是哈佛结构的形式 。6.8 频率测量显示电路显示电路如图6-15所示15。由于锁相环产生正弦波的频率较高，无法用单片机直接来测量它的频率，必须先用高速分频器来对它进行分频，使它降低到单片机的测量范围之内。但又考虑到性价比的问题，可直接用频率合成器BU2614的控制字和分频比来送给单片机显示。当控制字是8600H时，也就是R0、R1、R2为000时，选择步进为1K的标准频率，频率范围从25MHz到54MHz，根据 (6.5)N是分频比，为输入BU2614的频率， 为标准信号源频率可计算出分频比的范围： (6.6) (6.7)转化成十六进制的变化范围是从61A8H到D2F0H。当控制字是8000H时，R0、R1、R2为110时，步进为25KHz标准频率，频率从54 MHz 到110MHz，根据上面的公式可得分频数从0870H到1130H。送显示的时候可把它的分频数乘于所选择的标准频率，然后进行BCD码转换，再送给单片机处理。分频比可通过按键来调整。设置四个按键，分别是加一、加十、减一、减十。当需要选择较大调整时，可选择加十或减十；当需要较小范围调整时，可选择加一或减一。图6-15 显示电路7 软件设计7.1软件分析本设计软件的主要作用是用来控制BU2614、存储器AT24C02以及频率的显示。 因为输出正弦波的频带范围较宽，又考虑到精确度的要求，当步进为1KHz、控制字为FFFFH时，输出频率的最大值只能为65.536MHz，所以为了达到更高的频率，又能提高精确度，必须选择两种不同的标准频率。以54MHz为分界点，当低于54MHz时，选择以1KHz为步进，当高54MHz时，选择以25KHz为步进。当控制字为8600H时，分频数乘于1KHz；当控制字为8000H时，分频数乘于25KHz。因为分频数乘于标准频率化成BCD码以后占用的字节数不同，所以要调用两个不同的显示单元。调整频率时，可通过按键来实现，根据调用不同的子程序可以完成分频比加一、加十、减一、减十，当复位键按下时，显示的频率为50MHz。每次判断有按键按下时重新调用存储，写入新的数据，以防掉电时重新复位。软件流程图如图7-1、7-2所示。高频段初始化化清屏低频段P2.7清0P2.7置1写BU2614写BU2614调用显示2调用显示1调用存储判断按键是否按下执行相应按键的功能是否高频段还是低频段图7-1主流程图按键是否按下判断哪个按键按下是否按键1按键2按键3按键4加1加10减10减1写BU2614调用显示把值写入24C02图7-2 按键流程图8 测试结果 统调以后，用示波器可测量出各个频率值与相对应的电压值，由于考虑到正弦波的频带宽不能一一列出，这里测出以10MHz为步长,从25MHz到105MHz的9个测试频率点。从表8-1测试结果可以得出，在65MHz的时候电压值最大，也就是在这个频率点的时候Q值最大。表8-1频率与电压的对应关系(频率单位MHz)理想频率2535455565758595105测得频率24.634.745.255.365.375.485.595.4105.5电压(V)1.291.421.521.682.001.500.950.650.45 9 结论由于晶体振荡器单频点的局限性，难于满足多频点的要求。本设计为了修正石英晶体振荡器的不足，运用锁相环来产生一个高稳定度、高精确度、多频点的正弦波信号。产生的正弦波信号可应用于调频、解调、通信、电视等领域。 本设计的优点是，通过切换电感可扩大锁相环的带宽，实现25MHz到110MHz可调的频率，结果满足设计要求。此设计调试比较困难，要求经过低通滤波以后的直流电压稳定性较好,如果不稳定会造成压控振荡输出频率抖动。通过对低通中的RC值反复尝试发现，如果C太小，会造成经过低通以后的直流电压有纹波成分；如果C太大，会造成了充放电的时间过长，低通滤波的变化速度跟不上PD信号变化的速度，导致压控振荡输出频率变化特别缓慢。要实现设计要求中的任务，使压控振荡输出频率在25MHz到110MHz之间可变，就必须调整电感和电容的大小。电路中的高频信号容易受到干扰，如果单片机与其它电路共用一个电源的话，会对单片机造成干扰；测试的时候不同的接地测出来的波形有较大差别，而且测试端的引线太长，会造成高频辐射而使波形失真。为了避免这种情况，一般连接线都用屏蔽线。此电路应用范围广泛，日常生活中的很多地方都有它的应用。如无线数据的收发，收音机等。随着无线通信技术的发展，PLL信号源的应用也会越来越广泛。参考文献1 铃木宪次.高频电路的设计与制作，第1版，科学出版社，2005年,103-108.2 万天才.一种锁相式频率合成器的设计，微电子学，1999年，第3期，208.3 张肃文，陆兆熊.高频电子线路，第3版，高等教育出版社，2004年，616-652.4 黄智伟，王彦，陈文光.全国大学生电子设计竞赛训练教程，第1版，电子工业出版社，2005年，304-314.5 全国大学生电子设计竞赛组委会.第五届全国大学生电子设计竞赛获奖作品选编第1版，北京理工大学出版社，2005年，10-17.6 周兴华.变容二极管和电调谐，电子世界，2000年，第6期，54.7 徐守堂，杨志民，徐大诚.电视接收技术，第1版，西安电子科技大学出版社，2003年，74.8 康华光，陈大钦.电子技术基础，第4版，高等教育出版社，2003年，447.9 稻叶保.模拟技术应用技巧101例，第1版，科学出版社，2006年，3.10 WU Xunwei,HANG Guoqiang,Massoud Pedram. Low power DC circuits employing AC power supply, SCIENCE IN CHINA (INFORMATION SCIENCES), 2002 Vol.45 No.3, 232.11 郑俭锋.I2C总线的控制与实现，电子设计应用，2004年，第7期，65.12 张俊谟.MCS-51和80C51系列单片机，电子世界，2001年，第8期，30.13 李广弟，朱月秀，王秀山.单片机基础，第2版，北京航空航天大学出版社，2001年，13-71.14 梅丽风，王艳秋，张军,et.单片机原理及接口技术，第1版，清华大学出版社，2004年，296-323.15 吴金戌，沈庆阳，郭庭吉.8051单片机实践与应用，第1版，清华大学出版社，2002年，147-167.致 谢毕业设计意味着我大学四年的学习生活即将结束，从此我将踏上新的人生征途，进入一个新的工作岗位，开始一段新的生活。在此，我要感谢在我做毕业设计期间帮助过我的老师。首先我要感谢我的毕业设计指导老师李杰的大力帮助和支持。在做毕业设计的过程中，李老师给我提出了很多宝贵的具有建设性的意见。从一开始题目的讲解，到简单的查找资料，到程序的设计及调试，再到后期元器件的买件、制作，李老师不厌其烦、尽心尽力的帮助我。还要感谢胡建明老师给予的帮助，在做毕业设计期间提供实验室，还帮助我解决许多难题。在此期间，李老师和胡老师渊博的知识，乐观的人生态度，无时无刻不在影响着我，教我学到了很多做人的道理，这将使我受益终生。同时，此次毕业设计也是对我的综合素质的一种锻炼和培养，使之能更加耐心、细致、谨慎、科学地思考遇到的难题，同时锻炼了创新能力。我还要感谢在毕业设计期间帮助过我的同学，在我最需帮助的时候，是他们无私的帮助解决了我的实际困难。同时，我要感谢我的母校天津工程师范学院，大学四年，这里给我留下了美好的回忆。特别是在我即将踏上工作岗位的同时，给了我这样一个锻炼的机会，使我加深了对以前知识的理解，拓宽了知识面，也提高了我对所学知识的综合的应用能力。祝愿母校的将来更美好。最后，我要再一次感谢所有在此期间帮助过我的人，我衷心的祝福你们！附录：程序频率显示与存储程序;30H,31H,32H,33H为BU2614所用 ;34H-39H ;50h-57hVSDA EQU P3.2 ; EEPROM数据传送口 VSCL EQU P3.1 ; EEPROM时钟传送口 SLA EQU 6AH ; EEPROM器件寻址字节存放单元 NUMBYT EQU 6BH ; EEPROM传送字节数存放单元 MTD EQU 70H ; EEPROM发送数据缓冲单元 MRD EQU 6CH ; EEPROM读出数据存放单元 SLAW EQU 0A0H ; EEPROM寻址字节写 SLAR EQU 0A1H ; EEPROM寻址字节读 ORG 0000H AJMP START ORG 0030HSTART: MOV SP,#80H MOV R4,#08H ;显示缓冲区清零 MOV R0,#50HCLEAR: MOV R0,#00H INC R0 DJNZ R4,CLEAR MOV P1,#0F0H LCALL VIICREAD ;MOV 30H,#0A8h ; MOV 31H,#61H ;MOV 32H,#00H ;MOV 33H,#86H MOV A,33H XRL A,#86H JZ CLRP27 SETB P2.7 AJMP DCZCLRP27: CLR P2.7DCZ: LCALL PUTBITANJIAN: JNB P3.3,DOU1 JNB P3.4,DOU1 JNB P3.5,DOU1 JNB P3.6,DOU1 NOPMOV A,33H XRL A,#86H JZ DD AJMP GGDD: LCALL DISP1 AJMP NETGG: LCALL DISP2NET: LCALL DELAY LJMP ANJIANDOU1: LCALL DELAY JNB P3.3,JIAYI0 JNB P3.4,JIASHI0 JNB P3.5,JIANYI0 JNB P3.6,JIANSHI0 LJMP ANJIANJIAYI0: AJMP JIAYIJIASHI0: AJMP JIASHIJIANYI0: AJMP JIANYIJIANSHI0: AJMP JIANSHIJIAYI: MOV A,33H XRL A,#86H JZ DD1 AJMP GG1DD1: LCALL DISP1 LCALL DISP1 AJMP NET1GG1: LCALL DISP2 LCALL DISP2NET1: MOV A,33H XRL A,#86H JZ CLRP271 SETB P2.7 AJMP DCZ1CLRP271: CLR P2.7DCZ1: MOV A,33H XRL A,#86H JZ DIJIAYI AJMP GAOJIAYIDIJIAYI: MOV A,31H CLR C SUBB A,#0D2H ;DIGAO JC JIA1 MOV A,30H CLR C SUBB A,#0F0H JC JIA1 SETB P2.7 MOV 30H,#08H MOV 31H,#070H MOV 32H,#00H MOV 33H,#80H LCALL PUTBIT LCALL VIICWRITE AJMP ANJIANJIA1: CLR C MOV A,30H ADD A,#05H MOV 30H,A MOV A,31H ADDC A,#00H MOV 31H,A LCALL PUTBIT LCALL VIICWRITE AJMP ANJIANGAOJIAYI: MOV A,31H CLR C SUBB A,#12H ;GAOGAO JC JIA2 MOV A,30H CLR C SUBB A,#0C0H JC JIA2 AJMP ANJIANJIA2: CLR C MOV A,30H ADD A,#05H MOV 30H,A MOV A,31H ADDC A,#00H MOV 31H,A LCALL PUTBIT LCALL VIICWRITE AJMP ANJIANJIASHI: MOV A,33H XRL A,#86H JZ DD2 AJMP GG2DD2: LCALL DISP1 LCALL DISP1 AJMP NET2GG2: LCALL DISP2 LCALL DISP2NET2: MOV A,33H XRL A,#86H JZ CLRP272 SETB P2.7 AJMP DCZ2CLRP272: CLR P2.7DCZ2: MOV A,33H XRL A,#86H JZ DIJIAYIS AJMP GAOJIAYISDIJIAYIS: MOV A,31H CLR C SUBB A,#0D2H ;DIGAO JC JIA1S MOV A,30H CLR C SUBB A,#0F0H JC JIA1S SETB P2.7 MOV 30H,#070H MOV 31H,#08H MOV 32H,#00H MOV 33H,#80H LCALL PUTBIT LCALL VIICWRITE AJMP ANJIANJIA1S: CLR C MOV A,30H ADD A,#20 MOV 30H,A MOV A,31H ADDC A,#00H MOV 31H,A LCALL PUTBIT LCALL VIICWRITE AJMP ANJIANGAOJIAYIS: MOV A,31H CLR C SUBB A,#12H ;GAOGAO JC JIA2S MOV A,30H CLR C SUBB A,#0C0H JC JIA2S AJMP ANJIANJIA2S: CLR C MOV A,30H ADD A,#20 MOV 30H,A MOV A,31H ADDC A,#00H MOV 31H,A LCALL PUTBIT LCALL VIICWRITE AJMP ANJIANJIANYI: MOV A,33H XRL A,#86H JZ DD3 AJMP GG3DD3: LCALL DISP1 LCALL DISP1 AJMP NET3GG3: LCALL DISP2 LCALL DISP2NET3: MOV A,33H XRL A,#86H JZ CLRP273 SETB P2.7 AJMP DCZ3CLRP273: CLR P2.7DCZ3: MOV A,33H XRL A,#80H JZ GAOJIANYI AJMP DIJIANYIGAOJIANYI: MOV A,31H SUBB A,#08H JZ PANDI AJMP JIAN1PANDI: MOV A,30H SUBB A,#070H JNC JIAN1 MOV 30H,#0F0H MOV 31H,#0D2H MOV 32H,#00H MOV 33H,#86H CLR P2.7 LCALL PUTBIT LCALL VIICWRITE AJMP ANJIANJIAN1: CLR C MOV A,30H SUBB A,#05H MOV 30H,A MOV A,31H SUBB A,#00H MOV 31H,A LCALL PUTBIT LCALL VIICWRITE AJMP ANJIANDIJIANYI: MOV A,31H SUBB A,#61H JZ PAND2 AJMP JIAN2PAND2: MOV A,30H SUBB A,#0A0H JNC JIAN2 AJMP ANJIANJIAN2: CLR C MOV A,30H SUBB A,#05H MOV 30H,A MOV A,31H SUBB A,#00H MOV 31H,A LCALL PUTBIT LCALL VIICWRITE AJMP ANJIANJIANSHI: MOV A,33H XRL A,#86H JZ DD4 AJMP GG4DD4: LCALL DISP1 LCALL DISP1 AJMP NET4GG4: LCALL DISP2 LCALL DISP2NET4: MOV A,33H XRL A,#86H JZ CLRP274 SETB P2.7 AJMP DCZ4CLRP274: CLR P2.7DCZ4: MOV A,33H XRL A,#80H JZ GAOJIANYIS AJMP DIJIANYISGAOJIANYIS: MOV A,31H SUBB A,#08H JZ PANDIS AJMP JIAN1SPANDIS: MOV A,30H SUBB A,#070H JNC JIAN1S MOV 30H,#0F0H MOV 31H,#0D2H MOV 32H,#00H MOV 33H,#86H CLR P2.7 LCALL PUTBIT LCALL VIICWRITE AJMP ANJIANJIAN1S: CLR C MOV A,30H SUBB A,#20 MOV 30H,A MOV A,31H SUBB A,#00H MOV 31H,A LCALL PUTBIT LCALL VIICWRITE AJMP ANJIANDIJIANYIS: MOV A,31H SUBB A,#61H JZ PAND2S AJMP JIAN2SPAND2S: MOV A,30H SUBB A,#0A0H JNC JIAN2S AJMP ANJIANJIAN2S: CLR C MOV A,30H SUBB A,#20 MOV 30H,A MOV A,31H SUBB A,#00H MOV 31H,A LCALL PUTBIT LCALL VIICWRITE AJMP ANJIANDISP1: MOV 35H,31H MOV 34H,30H MOV 36H,#00H LCALL BCDST NOP NOP RETDISP2: MOV 35H,31H MOV 34H,30HMOV 36H,#00H MOV 37H,#00H MOV 38H,#00H MOV R7,#25KLK : CLR C MOV A,36H ADD A,34H MOV 36H,A MOV A,37H ADDC A,35H MOV 37H,A MOV A,38H ADDC A,#00H MOV 38H,A DJNZ R7,KLK MOV 34H,36H MOV 35H,37H MOV 36H,38 HLCALL BCDST NOP RET; ; BCD码转换程序 ; ;将36H、35、34,单元内数据转换成十进制BCD码放在39H、38H,37H单元内。 BCDST: MOV R7,#18H CLR C MOV 39H,#00H MOV 38H,#00H MOV 37H,#00HKKK: MOV A,34H RLC A MOV 34H,A MOV A,35H RLCA MOV 35H,A MOV A,36H RLCA MOV 36H,A MOV A,37H ADDC A,37H DAA MOV 37H,A MOV A,38H ADDC A,38H DA A MOV 38H,A MOV A,39H ADDC A,39H DA A MOV 39H,A DJNZ R7,KKK MOV A,39H ANL A,#0FH MOV 56H,A MOV A,39H SWAP A ANL A,#0FH MOV 57H,A MOV A,38H ANL A,#0FH MOV 54H,A MOV A,38H SWAP A ANL A,#0FH MOV 55H,A MOV A,37H ANL A,#0FH MOV 52H,A MOV A,37H SWAP A ANL A,#0FH MOV 53H,A MOV 51H,#00H MOV 50H,#00H LCALL DISP NOP NOP RETDISP: MOV A,57H ADD A,#70H MOV P2,A LCALL DELAY MOV A,56H ADD A,#60H MOV P2,A CALL DELAY MOV A,55H ADD A,#50H MOV P2,A CALL DELAY MOV A,54H ADD A,#40H MOV P2,A CALL DELAY MOV A,53H ADD A,#30H MOV P2,A CALL DELAY MOV A,52H ADD A,#20H MOV P2,A CALL DELAY MOV A,51H ADD A,#10H MOV P2,A CALL DELAY MOV A,50H ADD A,#00H MOV P2,A CALL DELAY MOV P2,#0FFH RET;BU2614;*PUTBIT: SETB P1.0 LCALL DELAY1 MOV A,30H LCALL PUT MOV A,31H LCALL PUT MOV A,32H LCALL PUT MOV A,33H LCALL PUT CLR P1.0 CLR P1.1 CLR P1.2 RETPUT: MOV R3,#08H CLR CPUT1: RRC A MOV P1.2,C LCALL DELAY1 SETB P1.1 LCALL DELAY1 CLR P1.1 DJNZ R3,PUT1 RETDELAY1: MOV R7,#09HD1: MOV R6,# 01FHD2: DJNZ R6,D2 DJNZ R7,D1 RETDELAY: MOV R7,#02HD11: MOV R6,#0F0HD21: DJNZ R6,D21 DJNZ R7,D11 RET;VIICWRITE ;归一化EEPROM存入程序（12M时钟），存入数在50H起单元VIICWRITE: LCALL WMOV9 MOV SLA,#SLAW MOV NUMBYT,#05H LCALL WRNBYT RETWMOV9: MOV 71H,30H MOV 72H,31H MOV 73H,32H MOV 74H,33H MOV MTD,#00H RET;VIICREAD ; 归一化EEPROM读出程序（12M时钟），读出数放入60H-67H单元VIICREAD: MOV MTD,#00H ; MOV SLA,#SLAW MOV NUMBYT,#01H LCALL WRNBYT MOV SLA,#SLAR MOV NUMBYT,#04H LCALL RDNBYT LCALL RMOV8 RETRMOV8: MOV 30H,6CH MOV 31H,6DH MOV 32H,6EH MOV 33H,6FH RET;VIIC PROGRAM ; I2C串行归一化存储子程序STA: SETB VSDA SETB VSCL NOP NOP NOP NOP CLR VSDA NOP CLR VSDA NOP NOP NOP NOP CLR VSCL RETSTOP: CLR VSDA SETB VSCL NOP NOP NOP NOP SETB VSDA NOP NOP NOP NOP CLR VSDA CLR VSCL RETMACK: CLR VSDA SETB VSCL NOP NOP NOP NOP CLR VSCL SETB VSDA RETMNACK: SETB VSDA SETB VSCL NOP NOP NOP NOP CLR VSCL CLR VSDA RETCACK: SETB VSDA SETB VSCL CLR F0 MOV C,VSDA JNC CEND SETB F0CEND: CLR VSCL RETWRBYT: MOV R0,#08HWLP: RLC A JC WR1 AJMP WR0WLP1: DJNZ R0,WLP RETWR1: SETB VSDA SETB VSCL NOP NOP NOP NOP CLR VSCL CLR VSDA AJMP WLP1WR0: CLR VSDA SETB VSCL NOP NOP NOP NOP CLR VSCL AJMP WLP1RDBYT: MOV R0,#08HRLP: SETB VSDA SETB VSCL MOV C,VSDA MOV A,R2 RLC A MOV R2,A CLR VSCL DJNZ R0,RLP RETWRNBYT: MOV R3,NUMBYT LCALL STA MOV A,SLA LCALL WRBYT LCALL CACK JB F0,WRNBYT MOV R1,#MTDWRDA: MOV A,R1 LCALL WRBYT LCALL CACK JB F0,WRNBYT INC R1 DJNZ R3,WRDA LCALL STOP RETRDNBYT: MOV R3,NUMBYT LCALL STA MOV A,SLA LCALL WRBYT LCALL CACK JB F0,RDNBYTRDN: MOV R1,#MRDRDN1: LCALL RDBYT MOV R1,A DJNZ R3,ACK LCALL MNACK LCALL STOP RETACK: LCALL MACK INC R1 SJMP RDN1END附录2：总电路图英文资料及中文翻译Development and application of EDA technologyEDA (Electronics Design Automation) technology is that one kind arising at the historic moment with the development at full speed of the integrated circuit and computer technology is advanced, fast, effective electronic design automation tool. EDA tool regards hardware and software of the computer as the basic workbench, software package in common use of CAD that collect the data base, figure learning, picture theory and topological logic, computational mathematics, optimize theory,etc. multi-disciplinary latest achievement and develops. EDA is a development trend of the electronic designing technique, utilize EDA tool to replace a designer and finish most work in the electronic system design.The implementation method of the digital system has been gone through from discrete component, SSI, MSI evolution at full speed to LSI, VLSI and UVISI too. In order to improve systematic dependability and commonability, the microprocessor and special-purpose integrated circuit (ASIC) have replaced the whole hardware LSI circuit in common use gradually. Can programme the logic device (PLD) , especially can be programmed in the making that the logic device(FPLD) is applied to ASIC in a large amount at the scene. In the course of canning programme the development of the integrated circuit , the appearance of EDA technology has brought the revolutionary change that the electronic system is designed.With the constant development of the microelectric technique and computer technology，in the design work of electronic system related to fields, such as communication, national defence, spaceflight, industrial automation, instrument and apparatus,etc，the content of EDA technology is rising at the surprising speed , it has already nowadays become one of the front of the electronic technical development. This text has explained the basic conception and evolution of EDA technology at first, then introduce the essential feature of ESDA from several different respects, Analyse the workflow on two different levels of EDA technology emphatically finally, namely one grade of designs of circuit and system grade are designed，have introduced a kind of top-down high level electronic design method.1PrefaceThe human society has already entered into the highly developed information-based society, the development of the information-intensive society can not do without the progress of the electronic product. The modern electronic product has been presenting the downward trend all the time at but the price while performance improves, complexity increases, and the paces of the model change are quicker and quicker , the main reason which realizes this kind of progress is the development which produces the manufacturing technology and electronic designing technique.The former regards very small process technology as representatives, has already developed the deep submicro at present, can integrate several ten million transistors on the chip of several square centimetre ; The latters core is EDA technology. EDA refers to regarding computer as the workbench, have merged electronic CAD software package in common use that the latest achievement of application electric technology, computer technology, intelligent technology develops into , can carry on the design work of three respects auxiliarily mainly: IC designs, electronic circuit design and PCB are designed. Without the support of EDA technology, it is unimaginable that the design that wants to finish above-mentioned very large scale integration is made, conversely, produce manufacturing technology constant to progress and will put forward new request to EDA technology.2Development of EDA technologyEDA technology is following the development that the computer, integrated circuit, electronic system are designed, have gone through CAD CAD (Computer Assist Design), auxiliary engineering design CAE of computer (Computer Assist Engineering Design) Three developing stages with design automation ESDA of electronic system (Electronic System Design Automation).Review the development course of electronic designing technique in the past 30 years, can divide EDA technology into three stages .The seventies of the 20th century, with hitting the appearance and application of the small- scale integrated circuit, traditional mading maps by hand and designed the printed circuit board and integrated circuit method has been already unable to meet and design the requests of the precision and efficiency, people begin high repeated miscellaneous work connect up and work and edit and replace with CAD tool that analyse such as Butut with two-dimentional level figure products design process. This has produced the first generation of EDA tools. Limited by computer workbench at that time, the design work that can be supported is limited and performance is worseThe seventies were CAD stage, people began to carry on the domain editor of IC and PCB overall arrangement to connect up auxiliarily with the computer this stage, it is done by hand toreplace, has produced the concept of CAD . The first individual computer platform of work station (Apollo) that appeared in the eighties, has promoted the rapid development of EDA tool. For meet the electronic product in the scale and make the need that have, the second generation of EDA technology taking emulation of the computer and self routing as key technology has appeared. CAE tool with automatic integration capability has replaced some design work of the designers. Characteristic its to regard software tool as core finish design, analyse, produce, every job of testing etc. of product development through software the. However, EDA tool that the majority proceeds from principle picture still cant meet the request that the complicated electronic system is designed , and the component figure specified is restricting optimization design.The eighties were CAE stage. Compared with CAD, draw the function besides the pure figure , has increased the function of the circuit again and is designed and designed with the structure, and conbine the two together through the electric connection network form, in order to realize engineering design, this is a concept of the auxiliary project of the computer. The main function of CAE is: The principle picture is input, logic emulation , the analysis of the circuit, the automatic overall arrangement is connected up, analyse after PCBIn the 1990s, the designer was from using the hardware to be developed and turned from one grade of electronic products of circuit to one grade of electronic product development of system to design the hardware progressively . ESDA tool is designed for the core with the system grade, including the systematic behavior grade describes that comprehensive with the structure grade, with test and prove systematic emulation system divide assign. The appearance of the third generation of EDA technology, the efficiency that the improvement system is designed greatly, dream of making the designer begin to realize that the concept drive the project . The designer has got rid of a large amount of auxiliary design work, concentrate energy on creative scheme and concept to conceive , thus improved efficiency of designing greatly, has shortenned the reseach cycle of the products.The 1990s were ESDA stage. Though CAD/CAE technology has made enormous success, has not liberated people completely from the strenuous design work out . In the course of designing entirely, automation and intelligent degree are also not high, various kinds of EDA software interfaces are various, learn and use difficult, and incompatible, influence and design to link up link directly. Because the above is insufficient, people begin to pursue the automation of carrying out whole design process.3The technology of EDA is formedThe essential feature of modern EDA technology is to adopt the high-level language to describe , have one grade of emulation of system and integration capability. EDA target of technical research the whole course that electron design, have system grade, circuit grade and physics grades of each design of level. The category of technical research of EDA is quite extensive, develops and uses the angle to look from ASIC, include the following sub module : Design introduction sub module, set up and count data base sub module, analyse and prove sub module, comprehensive emulation sub module, overall arrangement connect up sub module,etc.EDA adopts the cocurrent engineering and top-down design method mainly, then designs and starts with from the system, division and structure carrying on the function block-diagram on the top floor are designed, carries on emulation , corrects error first classly in the block-diagram , and describe with the hardwares, such as VHDL, Verilog-HDL, ABEL,etc. that the language describes the high-level systematic behavior, prove in system one grade , optimizes tools and produces the concrete netlist in one grade of logical circuits of door synthetically with logic afterwards, it can be a printed circuit board or special-purpose integrated circuit that its corresponding physics is realized grade.The experience of EDA tool is two great stages: Physics tool and logic tool. The actual physics question used for finishing of physics in the design of tool, for instance the overall arrangement of the chip, printed circuit board are connected up etc. The logic tool is because of the logic of the netlist, cloth, transmit the concepts, such as time sequence,etc., described at first that designs introduction in language by the picture editing machine of principle or the hardware, then utilize EDA system to finish being synthesized, course, such as emulation, optimizing,etc., the structurization of netlist or VHDL, Verilog-HDL turning into the physics tool finally and can be accepted is described. Now common EDA tools have logic, emulation, check / analyse by tool, optimize /synthesis tool,etc.At present, PLD has already become the main means that the modern digital system is designed. Traditional programming technology to insert and go on programming at programmable device PLD device, and can be programmed the appearance of the logic device in the system (ISP, namely In- System Programmable), has reached limit of the superiority full play of the programming device. ISP technology directly among user design object system or circuit go on the technology of programming to PLD device at the board. Have broken the convention that PLD must be assembled after programming first of using, the programming after can assemble first , can also be programmed repeatedly after becoming the products. ISP allows users programming in the system and revises logic, have provided for user and construct systematic ability and hardware upgrading ability again without revising the systematic hardware to design, make the hardware revised and as convenient like the software revise , systematic dependability improves because of this.4Development trend of EDA technologyWith the introduction of Intel Company Pentium processor, the listing of FPGA of hundreds of thousands pieces of scale of company, such as Xilinx,etc., and extensive chip group and application of the high-speed, high density printed circuit board, EDA technology is in emulation , time sequence analysis, integrated circuit test automatically, high-speed printed circuit board design and expansion of operating platform,etc. face the new enormous challenge. These are developments trend in the future of EDA technology of new generation. In the face of the electronic product market that nowadays develops at full speed, the designer needs more practical, swifter EDA tool, use unified integrated design environment, change traditional mentality of designing, concentrate on and get and design and conceive energy, the scheme compares and looks for the respects, such as optimization design,etc., develop the of good performance electronic product with first-class quality at fastest speed. Of new generation EDA technology towards powerful simple to learn while being easy, the direction easy to use will be developed.5Essential feature of ESDA technologyESDA representatives are nowadays the newest developing direction of electronic designing technique, its essential feature is: The designer divides with the function conceptual design to the whole system according to the top-down design method , the key circuit of the system is realized with one or several slices of special-purposes integrated circuit (ASIC), then adopt the hardware to describe that the language (HDL) is finished the systematic behavior grade and designed, produce the final goal device through comprehensive device and adapter finally. The electronic design method known as high level of such a design method, will also do the introduction of deepenning in 4.2 in concrete procedure. Now introduce several concepts related to ESDA essential feature.5.1 the“ Top-Down” design method10 years ago, chose the standard integrated circuit to construct out a new system “ Bottom-Up” in basic train of thought that the electron is designed, such a design method build Pyramid like one brick one, it lows with high costs efficiency have to be but also easy to make mistakes.Design the brand-new design method to provide for us a kind of Top-Down in high level, designing starting with from the system at first in these kind of design method, division and structure carrying on the function block-diagram on the top floor are designed. Carries on emulation , corrects error first classly in the block-diagram , and describe with the hardware that the language describes the high-level systematic behavior, prove in system one grade. Then by optimizing tools and produce the concrete netlist of pieces of circuit synthetically, it can be a printed circuit board or special-purpose integrated circuit that its corresponding physics is realized grade. Because the main emulation designed and debugging the course to finish on high level, this not merely helps to find the mistake on the structure design in early days, avoid the waste of the design work, and has reduced the work load of logic function emulation , has improved success rate designed.5.2 The designing of ASICThe complexity of the modern electronic product is strengthened day by day, a electronic system may be formed by integrated circuit on a small scale of several tens of thousands of, this has brought volume largly, the consumption is great, problem with bad dependability , the effective method to solve this problem is to adopt ASIC (Application Specific Integrated Circuits) chip to be designed. ASIC can be divided into according to the difference of design methods: Customize ASIC all, half customize ASIC, programmable ASIC (called and can programme the logic device too).When design and customize ASIC chip completely, the designer wants to define the geometric figure of all transistors and rule of craft on the chip, design result transfer to IC producer close membrane make and finish finally. The advantage is: The chip can obtain optimum performance, namely area utilization ratio high, fast, low power dissipation . The shortcoming is: Development period is long, costly, only suitable for the product development inenormous quantities.Half customize ASIC domain of chip design method to some extent different, divide into door array design law and standard unit design law, these two kinds of methods are both binding character design methods, its main purpose is simplified and designed, shorten construction period by sacrificing the performance of the chip as the cost. Can programme logic chip and above-mentioned difference of covering the membrane ASIC to lie in : The designer can fire out ones own chip in the laboratory after finishing the domain design, needn t have the participation of IC producer, has shortenned development period greatly .Can programme the logic device since the seventies , has gone through PAL, GAL, CPLD, FPGA several developing stages, among them CPLD/FPGA has belonged to the high density and can programme the logic device , the integrated level has already been up to 2 million doors slice at present, it close integrated level high advantage, ASIC of membrane, and can programme logic device design and produce convenient characteristic conbine together, especially suited to the sample developing short run product development, enable products and list at fastest speed, and when the market expands , it can very easy to transfer to and cover membrane ASIC realize, so develop the risk but greatlied reduced .5.3 The hardware describes languagesThe hardware describes that the language (HDL-Hardware Description Language) is a kind of computer language used for designing the electronic system of the hardware, it describe the logic function of the electronic system, circuit structure and connects the form in programming way of software, describe with traditional door grade that the way compares, it is more suitable for the design of the extensive system. Such as one addition device of 32, utilize figure input software need 500 introduction to 1000 door, and utilize VHDL language to only need to write a line of A =B +C, and VHDL language readability is strong, apt to revise and find the mistake.The early hardware described languages, was developed by different EDA manufacturers such as ABEL-HDL, AHDL, not compatible each other, and does not support designing at many levels , translation should be finished artificially among the levels. In order to overcome the above defect, the American Ministry of National Defence put out VHDL (Very High Speed IC Hardware Description Language) language formally in 1985, IEEE adopted VHDL and described the standard of languages (IEEE STD-1076) for the hardware in 1987.VHDL whether one omni-directional hardware describe language, including systematic behavior grade, register transmit grade and logic gate one magnitude of a lot of design levels, support the mixing and describing of three kinds of description forms of the structure, dataflow, behavior, so VHDL nearly covers the functions of describing the language of various kinds of hardwares in the past, whole top-down or the bottom-up circuit design process can be finished with VHDL. In addition, VHDL also has the following advantages :The wide range of VHDL describes the core that ability makes it become high level and is designed, has brought the designers focus of work up to the realization and debugging of the systematic function, less energy is used in physics to realize to only need flowersVHDL can describe with the succinct and clear code that controls the logic design complicatedly , flexible and convenient, but also easy to design the exchange, save of the result and put in an position.The design of VHDL does not depend on the specific device , has facilitated the conversion of the craft . VHDL is a standard language, support for numerous EDA manufacturers , so the transplanting is good.5.4 Systematic frame structureEDA systematic frame structure (Framework) is a set of norms of disposing and use EDA software package, present main EDA system all set up frame structure, for instance Design Framework of Cadence Company, Falcon Framework of Mentor Company,etc., these frame structure is all in accordance with the unified technical standard that international CFI organization (CAD Framework Initiative) make . Framework can carry on optimization grouping of the tool software from different EDA manufacturers , integrates it under a unified environment of easy management, and still support and realize the transmission and sharing of information in the course of whole product development between the tasks, between the designers, this is a realization foundation of a cocurrent engineering and Top-Down design method.6. ConclusionEDA technology whether electron design a revolution of field, at developing stage of high speed at present, there are new EDA tools every year to come out, the application level of EDA technology of our country lags behind the developed country for a long time, so, the masses of electronic engineering personnel should master this advanced technology as soon as possible , this improve design need of efficiency is of our country electronics industry survive at world market even more, strive and need that develop unexpectedly.EDA技术的发展与应用EDA(Electronics Design Automation电子设计自动化)技术是随着集成电路和计算机技术的飞速发展应运而生的一种高级、快速、有效的电子设计自动化工具。EDA工具是以计算机的硬件和软件为基本工作平台，集数据库、图形学、图论与拓扑逻辑、计算数学、优化理论等多学科最新成果研制的计算机辅助设计通用软件包。EDA是电子设计技术的发展趋势，利用EDA工具可以代替设计者完成电子系统设计中的大部分工作。数字系统的实现方法也经历了由分立元件、SSI、MSI到LSI、VLSI以及UVISI的飞速发展过程。为了提高系统的可靠性与通用性，微处理器和专用集成电路(ASIC)逐渐取代了通用全硬件LSI电路。可编程逻辑器件(PLD)，尤其是现场可编程逻辑器件(FPLD)被大量地应用在ASIC的制作中。在可编程集成电路的开发过程中，EDA技术的出现带来了电子系统设计的革命性变化。随着微电子技术和计算机技术的不断发展，在涉及通信、国防、航天、工业自动化、仪器仪表等领域的电子系统设计工作中，EDA技术的含量正以惊人的速度上升，它已成为当今电子技术发展的前沿之一。本文首先阐述了EDA技术的基本概念和发展过程，然后从几个不同的方面介绍ESDA的基本特征，最后着重分析EDA技术在两个不同层次上的工作流程，即电路级设计和系统级设计，引入了一种自顶向下的高层次电子设计方法。 1 前言 人类社会已进入到高度发达的信息化社会，信息社会的发展离不开电子产品的进步。现代电子产品在性能提高、复杂度增大的同时，价格却一直呈下降趋势，而且产品更新换代的步伐也越来越快，实现这种进步的主要原因就是生产制造技术和电子设计技术的发展。前者以微细加工技术为代表，目前已进展到深亚微米阶段，可以在几平方厘米的芯片上集成数千万个晶体管；后者的核心就是EDA技术。EDA是指以计算机为工作平台，融合了应用电子技术、计算机技术、智能化技术最新成果而研制成的电子CAD通用软件包，主要能辅助进行三方面的设计工作：IC设计,电子电路设计以及PCB设计。没有EDA技术的支持，想要完成上述
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