逻辑与计算机设计基础第4版第5章答案.pdf

60 CHAPTER 5 2008 Pearson Education Inc 5 1 5 2 5 3 5 4 0 ps20 ns40 ns60 ns80 ns S n R n Q Q n 0 ps50 ns100 ns150 ns200 ns C S R Q Q n 0 ps50 ns100 ns150 ns C D Q Q n 61 Problem Solutions Chapter 5 5 5 5 6 Unknown D C D C X Y A BZ Clock Clock X Present stateInputs Next stateOutput ABXYABZ 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 1 0 0 0 1 1 1 0 1 1 1 0 1 0 0 0 0 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 S0S1 S2S3 0X 0 X0 0 11 0 Format XY Z X unspecified 0X 0 10 1 11 1 0X 0 11 0 10 0 0X 0 11 1 10 1 S0 00 S1 01 S2 10 S3 11 62 Problem Solutions Chapter 5 5 7 5 8 5 9 5 10 000 001010 011100 101 110 111 X 1 X 0 000 001010 011 100101 110111 Present stateInputNext state ABCXABC 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 State diagram is the combination of the above two diagrams Present stateInputsNext stateOutput QXYQS 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 0 1 0 0 0 0 1 1 1 1 01 01 0 10 0 01 1 10 1 00 0 11 0 00 1 11 1 Format XY S Present State0001000001110001111010 Input10011011110 Output01000100001 Next State0100000111000111101000 Format XY Z 01 32 00 0 01 0 01 1 10 0 11 1 11 0 x0 1 01 0 x0 0 01 1 11 0 10 1 00 1 11 1 63 Problem Solutions Chapter 5 5 11 5 12 SA B RA B Present stateInputNext stateOutput ABXABY 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 0 0 1 SBXA RBXA 01 23 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 Format X Y a D C R S D C R S Clock A A Y B B X Reset b D C D C Clock A A Y B B X Reset 64 Problem Solutions Chapter 5 5 13 5 14 Present stateInputNext state ABXAB 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 1 0 0 0 1 0 0 1 1 1 A B X A B X DADB DA AX BX DB AX BX 1 111 1 111 Logic diagram not given Encoding StateCode Q1Q2 A0 0 B0 1 C1 0 D1 1 Present stateInputsNext stateOutput Q1Q2X1X2Q1 t 1 Q2 t 1 Z 0000000 0001010 0010011 0011000 0100000 0101000 0110111 0111111 1000001 1001000 1010101 1011100 1100101 1101011 1110010 1111101 For part a results replace codes in table below with state name e g 00 with A Q1 Q2 Q1 Q2 Q2 Q1 Q2 Q1 65 Problem Solutions Chapter 5 5 15 5 16 Encoding StateCode Q1Q2Q3 A010 B100 C110 D001 E011 F101 Unused states 000 111 The state assignment could be different E g states A B or C could be 000 and states D E or F could be 111 Next State Q t 1 Present stateFor InputOutput Q t X 0X 1Z ABD0 BDC0 CAF0 DFC1 ECE1 FEF1 X Q1 Q3 Q2 Next State Q t 1 Output Present stateFor Input Q t X 0X 1Z ACE0 BED1 CCE0 DFA1 EBD1 FCE0 Encoding StateCode Q1Q2Q3 A000 B001 C010 D011 101 F110 E 66 Problem Solutions Chapter 5 5 17 States A C F are equivalent and merged to get state M States B and E are equivalent and merged to get state N State D becomes state O Encoding Z is a state variable and an output and Y is a state variable StateCode Y Z M00 N01 O11 DY ZXYDZ ZYXZ Gate input cost of the original circuit 21 42 63 Gate input cost of the new circuit Next State Q t 1 Output Present stateFor Input Q t X 0X 1X MMN0 NNO1 OMM0 9 28 37 DA DXXCXBXA CBA DB A AX DC B BX DD C CX Present stateInputsNext stateOutput ABCDEXaXbXcXdABCDEU 100000 xxx100000 100001xxx010000 01000 x0 xx100000 01000 x1xx001000 00100 xx0 x100000 00100 xx1x000100 00010 xxx01000000 00010 xxx100001 0 00001xxxx000011 D DE D E DX Signal L is applied to the asynchronous set reset inputs on the flip flops to implement locking U E A E D C B U 67 Problem Solutions Chapter 5 5 18 5 19 01 10 1 x1 x 00 0 x1 x 00 1 10 0 Format XY Z x unspecified Present stateInputsNext stateOutput Q t XYQ t 1 Z 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 X 1 X 1 X 0 X 0 07 16 04 03 02 01 05 0 E 0 E 1 Present state Next State For InputOutput D2D1D0E 0E 1Z 000 001 010 011 100 101 110 111 001 010 011 100 101 110 111 111 001 010 011 100 101 110 111 000 0 0 0 0 0 0 0 1 D C D C D C CLK Z E S S S RESET The state assignment could be different E g state 7 could be 000 with state 0 001 This would permit use of R inputs on the D flip flops for RESET D0 D1 D2 68 Problem Solutions Chapter 5 5 20 5 21 0 07 06 14 13 12 11 15 1 E 0 E 1 Present state Next State For InputOutput D2D1D0E 0E 1Z 000 001 010 011 100 101 110 111 001 010 011 100 101 110 111 111 001 010 011 100 101 110 111 000 0 1 1 1 1 1 1 0 Assumes for E 0 the output remains at 0 D C D C D C CLK Z E S S S RESET 0 43 2 1 5 X 1 Z 1 S 0 X 1 X 1 Z 1 S 0 Z 1 S 0 X x Z 0 S 1 X 1 Z 1 S 0 X 1 Z 1 S 0 X 0 Z 0 S 0 X 0 Z 0 S 0 X 0 X 0 Z 0 S 0 Z 0 S 0 X 0 Z 0 S 0 Present stateInputNext stateOutput ABCXABCZS 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 69 Problem Solutions Chapter 5 5 22 5 23 D C D C D C CLK Z X S 01 X 0 Z 1 X 0 Z 0 X 1 Z 0X 1 Z 1 Present stateInput Next stateOutput AXAZ 0 0 1 1 0 1 0 1 1 0 0 1 0 1 1 0 D C CLK Z X R RESET 10 X 1 Z 0 X 0 Z 0 X 0 Z 1X 1 Z 1 Present stateInput Next stateOutput AXAZ 0 0 1 1 0 1 0 1 1 0 1 0 0 1 1 0 D C CLK Z X R RESET 70 Problem Solutions Chapter 5 5 24 5 25 000001010011 100 Reset 00 0 x1 1 xx 1 10 0 0 x 1 11 0 1x 1 01 0 x0 1 00 0 Format RA E x unspecified 10 0 11 0 01 0 Present stateInputsNext stateOutput BCDRABCDE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 1 1 1 0 0 1 0 1 0 Present stateInputsNext stateOutput BCDRABCDE 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 01 x1 0 10 1 11 1 0 x 0 x0 0 Present stateInputNext stateOutput AXYAZ 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 0 1 1 0 0 0 0 Format XY Z x unspecified 71 Problem Solutions Chapter 5 5 26 5 27 To use a one hot assignment the two flip flops A and B need to be replaced with four flip flops Y4 Y3 Y2 Y1 Present StateInputNext StateOutput A BY4 Y3 Y2 Y1XA B Y4 Y3 Y2 Y1Z 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 1 0 1 0 1 0 1 0 1 0 0 0 1 1 0 1 1 1 0 1 1 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 No Reset State Specified D1 Y1 X Y1 X Y4 D2 Y2 X Y1 X Y2 D3 Y3 X Y2 X Y3 D4 Y4 X Y3 X Y4 D C D C X Y1 Y2 Y Clock D C D C Y3 Y4 SRQ 00QNo Change 010Reset 101Set 111Set a 01 01 10 11 00 01 00 10 11 Format SRb 72 Problem Solutions Chapter 5 5 28 5 29 Present stateInputNext state QSRQ t 1 AB 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 1 0 1 1 0 0 1 1 x 0 x x x x 0 0 0 1 0 0 S R A Q S R c B Clock A S B SR Present StateNext State ABCABC 000 001 010 011 100 101 110 111 100 000 XXX 001 110 XXX 111 011 a DA C DB A DC B b Clear A Reset Clear B Reset Clear C Reset c d e f The circuit is suitable for child s toy but not for life criti cal applications In the case of the child s toy it is the cheapest implementation If an error occurs the child just needs to reset it In life critical applications the immedi ate detection of errors is critical The circuit above enters invalid states for some errors For a life critical applica tion additional circuitry is needed for immediate detec tion of the error Error ABC ABC This circuit using the design in a does return from the invalid states to a valid state automatically after one or two clock periods Specification Verification Present stateInputNext stateNext state QSRQ t 1 ABABQ t 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 1 0 1 1 0 0 1 1 x 0 x x x x 0 0 0 1 0 0 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 0 0 0 1 1 1 0 1 1 73 Problem Solutions Chapter 5 5 30 5 31 5 32 0 ps20 ns40 ns60 ns80 ns Clock Reset X Y A B Format XY Z 01 32 00 0 01 0 01 1 10 0 11 1 11 0 x0 1 01 0 x0 0 01 1 11 0 10 1 00 1 11 1 RESET 12 3 10 4 5 6 7 8 9 11 12 13 14 15 Reset 00 01 00 01 11 x0 x0 01 10 01 01 11 11 11 10 D C D C A B Z Clock Y X 0 ps20 ns40 ns60 ns80 ns Clock Reset X Y A B 74 Problem Solutions Chapter 5 5 33 5 34 5 35 0 ps50 ns100 ns150 ns Clock J K Y Q This simulation was performed without initializing the state of the latches of the flip flop beforehand Each gate in the flip flop implementation has a delay of 1 ns The interaction of these delays with the input change times produced a narrow pulse in Y at about 55 ns In this case the pulse is not harmful since it dies out well before the positive clock edge occurs Nevertheless a thorough examination of such a pulse to be sure that it does not represent a design error or important timing problem is critical Function table for the LH flip flop LHand SR latch in a master slave circuit CLDQ t 1 SR 0XXNo changeXX 10XNo change00 110001 111110 flip flop State table StateStateTransitionNextStateNon zero CodeConditionStateCodeOutputs A00XA00 XB01 B01X Z YA00 YC10 C10Y Z XD11 XA00 D11Z YX YXD11 XY YXC10 Y2 Y1 75 Problem Solutions Chapter 5 5 36 5 37 Constraint 1 checks on the transition conditions TC Init There is one pair of TCs to check TRA ST STOP START POTS 0 Fill 1 There are three pairs of TCs to check 1L POTS STOP 0 1L POTS L1 POTS 0 STOP L1 POTS 0 Fill 2 There are six pairs of TCs to check L2 IN POTS STOP 0 L2 IN POTS 2L POTS 0 L2 IN POTS L2 NI POTS 0 STOP 2L POTS 0 STOP L2 NI POTS 0 2L POTS L2 NI POTS 0 Fill 3 There are three pairs of TCs to check 3L POTS STOP 0 3L POTS L3 POTS 0 STOP L3 POTS 0 Mix There are three pairs of TCs to check ZT POTS STOP 0 ZT POTS TZ POTS 0 STOP TZ POTS 0 Empty There is one pair of TCs to check 0L POTS L0 STOP 0 Constraint 2 checks on the transition conditions TC Init TRATS STOP START POTS 1 Fill 1 1L POTS STOP L1 POTS 1 Fill 2 L2 IN POTS STOP 2L POTS L2 NI POTS 1 Fill 3 3L POTS STOP L3 POTS 1 Mix ZT POTS STOP TZ POTS 1 Empty 0L POTS L0 STOP 1 76 Problem Solutions Chapter 5 5 38 5 39 StateTransitionNextStateNon zero StateCodeConditionStateCodeOutputs Init1000000N5 0010000 D10 0001000 QDispense0000001 N D Q Init1000000 Coin ReturnRC 01000001Init1000000 5 0010000N10 0001000 D15 0000100 QDispense0000001 CRCoin Return0100000 RC N D Q 5 0010000 10 0001000N15 0000100 D20 0000010 QDispense0000001 CRCoin Return0100000 RC N D Q 10 0001000 15 0000100N20 0000010 D QDispense0000001 CRCoin Return0100000 RC N D Q 15 0000100 20 0000010N D QDispense0000001 CRCoin Return0100000 RC N D Q 20 0000010 DispenseDJ 00000011Init1000000 D flip flop inputs Init t 1 Init N D Q Coin Return Dispense Coin Return t 1 5 CR 10 CR 15 CR 20 CR 5 t 1 Init N 5 RC N D Q 10 t 1 Init D 5 N 10 RC N D Q 15 t 1 5 D 10 N 15 RC N D Q 20 t 1 10 D 15 N 20 RC N D Q Dispense t 1 Q 15 D 20 D 20 N Outputs RC Coin Return DJ Dispense Init25c 125c 100c 75c 50c NoCh Reset a QQQQQQ D Q D D C L O R D R D R D R D R D R D R C L O R D LT2Q No Change D R Return 2 Quarters Disp Cola Disp Lemon Disp Orange Disp Root Beer LED 150c200c 77 Problem Solutions Chapter 5 5 40 5 41 5 42 b Some possible changes to the specification follow 1 Provide appropriate change and dispense soda for the cases in which 75 cents and 125 cents followed by a dollar have been deposited Provide a coin return button for the event that the user is out of quarters and dollars before the 150c state is reached 3 Change the No Change warning to cover all added cases in 1 library IEEE use IEEE std logic 1164 all entity mux 4to1 is port S in STD LOGIC VECTOR 1 downto 0 D in STD LOGIC VECTOR 3 downto 0 Y out STD LOGIC end mux 4to1 continued in the next column architecture mux 4to1 arch of mux 4to1 is begin process S D begin case S is when 00 Y Y Y Y null end case end process end mux 4to1 arch architecture mux 4to1 arch of mux 4to1 is begin process S D begin if S 00 then Y D 0 elsif S 01 then Y D 1 elsif S 10 then Y D 2 elsif S 11 then Y D 3 else null end if end process end mux 4to1 arch library IEEE use IEEE std logic 1164 all entity mux 4to1 is port S in STD LOGIC VECTOR 1 downto 0 D in STD LOGIC VECTOR 3 downto 0 Y out STD LOGIC end mux 4to1 continued in the next column library IEEE use IEEE std logic 1164 all entity serial BCD Ex3 is port clk reset X in STD LOGIC Z out STD LOGIC end serial BCD Ex3 architecture process 3 of serial BCD Ex3 is type state type is Init B10 B11 B20 B21 B2X B3X0 B31 signal state next state state type begin Process 1 state register state register process clk reset begin if reset 1 then state Init else if CLK event and CLK 1 then state if X 0 then next state B10 else next state if X 0 then next state B20 else next state next state next state if X 0 then next state B3X0 78 Problem Solutions Chapter 5 5 43 else next state if X 0 then next state B3X0 else next state next state next state if X 0 then Z 1 else Z continued in the next column if X 0 then Z 1 else Z Z Z if X 0 then Z 1 else Z if X 0 then Z 1 else Z Z Z 1 end case end process end process 3 initb10b20b3x0initb10b20b3x0initb10b21b3x0init 050100150200250 clk reset x z state initb10b20b3x0 initb10b20b3x0initb10b21b3x0init initb10b21b31initb11b2xb3x0initb11b2xb31init 250300350400450500 clk reset x z state initb10b21b31init b11b2xb3x0initb11b2xb31init library IEEE use IEEE std logic 1164 all entity prob 5 43 is port clk reset in STD LOGIC X in STD LOGIC VECTOR 2 downto 1 Z out STD LOGIC end prob 5 43 architecture process 3 of prob 5 43 is type state type is A B C D signal next state state state type begin Continued in next column Process 1 state register state register process clk reset begin if reset 1 then state A elsif clk event and clk 1 then state case X is when 00 next state next state next state next state next state case X is when 00 next state next state next state next state next state case X is when 00 next state next state next state next state next state case X is when 00 next state next state next state next state next state case X is when 00 Z Z Z Z Z case X is when 00 Z Z Z Z Z case X is when 00 Z Z Z Z Z case X is when 00 Z Z Z Z Z X end case end case end process end process 3 80 Problem Solutions Chapter 5 5 44 5 45 library IEEE use IEEE std logic 1164 all entity prob 5 44 is port clk reset X in STD LOGIC Z out STD LOGIC end prob 5 44 architecture process 3 of prob 5 44 is type state type is A B C D E F signal state next state state type begin Process 1 state register state register process clk reset begin if reset 1 then state A else if CLK event and CLK 1 then state if X 0 then next state B else next state if X 0 then next state D else next state if X 0 then next state A Continued in next column else next state if X 0 then next state F else next state if X 0 then next state C else next state if X 0 then next state E else next state Z Z Z Z Z Z if K 1 then q out if K 0 then q out 1 else q out null end case end if end process Q q out end jkff arch 81 Problem Solutions Chapter 5 5 46 Errata Replace 5 10 with 5 11 library IEEE use IEEE std logic 1164 all entity prob 5 46 is port clk reset NI Start Stop L0 L1 L2 L3 TZ in STD LOGIC MX PST TM V1 V2 V3 VE out STD LOGIC end prob 5 46 architecture process 3 of prob 5 46 is type state type is Init Fill 1 Fill 2 Fill 3 Mix Empty signal state next state state type begin Process 1 state register state register process clk reset begin if reset 1 then state Init else if CLK event and CLK 1 then state next state end if end if end process Process 2 next state function next state func process NI Start Stop L0 L1 L2 L3 TZ state begin if Stop 1 then next state if Start 1 then next state Fill 1 else next state if L1 1 then next state Fill 2 else next state if L2 1 then if NI 1 then next state Fill 3 else next state Mix end if else next state if L3 1 then next state Mix else next state if TZ 1 then next state Empty else next state if L0 1 then next state Init else next state Empty end if end case end if end process Process 3 output function output func process L2 L3 NI TZ Stop state begin MX 0 PST 0 TM 0 V1 0 V2 0 V3 0 VE when Fill 1 V1 V2 1 if L2 and not NI and not Stop 1 then PST V3 1 if L3 and not Stop 1 then PST MX 1 if not TZ and not Stop 1 then TM VE 1 end case end process end process 3 82 Problem Solutions Chapter 5 5 47 library IEEE use IEEE std logic 1164 all entity prob 5 47 is port clk reset CR N D Q in STD LOGIC DJ RC out STD LOGIC end prob 5 47 architecture process 3 of prob 5 47 is type state type is S0 S5 S10 S15 S20 S25 RT signal state next state state type begin Process 1 state register state register process clk reset begin if reset 1 then state S0 else if CLK event and CLK 1 then state if N 1 then next state S5 elsif D 1 then next state S10 elsif Q 1 then next state S25 else next state if CR 1 then next state RT elsif N 1 then next state S10 elsif D 1 then next state S15 elsif Q 1 then next state S25 else next state if CR 1 then next state RT elsif N 1 then next state S15 elsif D 1 then next state S20 elsif Q 1 then next state S25 else next state if CR 1 then next state RT elsif N 1 then next state S20 elsif D 1 then next state S25 elsif Q 1 then next state S25 else next state if CR 1 then next state RT elsif N 1 then next state S25 elsif D 1 then next state S25 elsif Q 1 then next state S25 else next state next state next state S0 end case end process Process 3 output function output func process CR N D Q state begin DJ 0 RC DJ RC null end case end process end process 3 83 Problem Solutions Chapter 5 5 48 5 49 5 50 module problem 6 38 S D Y input 1 0 S input 3 0 D output Y reg Y continued in the next column always S or D begin case S 2 b00 Y D 0 2 b01 Y D 1 2 b10 Y D 2 2 b11 Y D 3 endcase end endmodule module problem 6 39 S D Y input 1 0 S input 3 0 D output Y reg Y continued in the next column always S or D begin if S 2 b00 Y D 0 else if S 2 b01 Y D 1 else if S 2 b10 Y D 2 else Y D 3 end endmodule Serial BCD to Excess 3 Converter module serial BCD Ex3 clk reset X Z input clk reset X output Z reg 2 0 state next state parameter Init 3 b000