FPGA警告大全.doc

一个高人写的Quartus警告分析大全Quartus警告分析！1.Found clock-sensitive change during active clock edge at time on register 原因：vector source file中时钟敏感信号（如：数据，允许端，清零，同步加载等）在时钟的边缘同时变化。而时钟敏感信号是不能在时钟边沿变化的。其后果为导致结果不正确。 措施：编辑vector source file 2.Verilog HDL assignment warning at : truncated with size to match size of target ( 原因:在HDL设计中对目标的位数进行了设定,如:reg4:0 a;而默认为32位,将位数裁定到合适的大小 措施:如果结果正确,无须加以修正,如果不想看到这个警告,可以改变设定的位数 3.All reachable assignments to data_out(10) assign 0, register removed by optimization 原因:经过综合器优化后，输出端口已经不起作用了 4.Following 9 pins have nothing, GND, or VCC driving datain port - changes to this connectivity may change fitting results 原因:第9脚，空或接地或接上了电源 措施:有时候定义了输出端口，但输出端直接赋0，便会被接地，赋1接电源。如果你的设计中这些端口就是这样用的，那便可以不理会这些warning 5.Found pins ing as undefined clocks and/or memory enables 原因:是你作为时钟的PIN没有约束信息。可以对相应的PIN做一下设定就行了。主要是指你的某些管脚在电路当中起到了时钟管脚的作用，比如flip-flop的clk管脚，而此管脚没有时钟约束，因此QuartusII把“clk”作为未定义的时钟。 措施:如果clk不是时钟，可以加“not clock”的约束；如果是，可以在clock setting当中加入；在某些对时钟要求不很高的情况下，可以忽略此警告或在这里修改:AssignmentsTiming analysis settings.Individual clocks. 6.Timing characteristics of device EPM570T144C5 are preliminary 原因:因为MAXII 是比較新的元件在 QuartusII 中的時序并不是正式版的,要等 Service Pack 措施:只影响 Quartus 的 Waveform 7.Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled 措施:将setting中的timing Requirements&Option-More Timing Setting-setting-Enable Clock Latency中的on改成OFF 8.Found clock high time violation at 14.8 ns on register |counter|lpm_counter:count1_rtl_0|dffs11 原因:违反了steup/hold时间，应该是后仿真，看看波形设置是否和时钟沿符合steup/hold时间 措施:在中间加个寄存器可能可以解决问题 9.warning: circuit may not operate.detected 46 non-operational paths clocked by clock clk44 with clock skew larger than data delay 原因:时钟抖动大于数据延时,当时钟很快，而if等类的层次过多就会出现这种问题,但这个问题多是在器件的最高频率中才会出现 措施：setting-timing Requirements&Options-Default required fmax 改小一些，如改到50MHZ 10.Design contains input pin(s) that do not drive logic 原因:输入引脚没有驱动逻辑(驱动其他引脚）,所有的输入引脚需要有输入逻辑 措施:如果这种情况是故意的,无须理会,如果非故意,输入逻辑驱动. 11.Warning：Found clock high time violation at 8.9ns on node TEST3.CLK 原因：FF中输入的PLS的保持时间过短 措施：在FF中设置较高的时钟频率 12.Warning: Found 10 node(s) in clock paths which may be acting as ripple and/or gated clocks - node(s) analyzed as buffer(s) resulting in clock skew 原因:如果你用的 CPLD 只有一组全局时钟时，用全局时钟分频产生的另一个时钟在布线中当作信号处理，不能保证低的时钟歪斜(SKEW)。会造成在这个时钟上工作的时序电路不可靠，甚至每次布线产生的问题都不一样。 措施:如果用有两组以上全局时钟的 FPGA 芯片，可以把第二个全局时钟作为另一个时钟用，可以解决这个问题。 13.Critical Warning: Timing requirements were not met. See Report window for details. 原因：时序要求未满足， 措施：双击Compilation Report-Time Analyzer-红色部分（如clock setup:clk等）-左键单击list path,查看fmax的SLACK REPORT再根据提示解决,有可能是程序的算法问题 14.Cant achieve minimum setup and hold requirement along path(s). See Report window for details. 原因：时序分析发现一定数量的路径违背了最小的建立和保持时间，与时钟歪斜有关,一般是由于多时钟引起的 措施：利用Compilation Report-Time Analyzer-红色部分（如clock hold:clk等），在slack中观察是hold time为负值还是setup time 为负值，然后在：Assignment-Assignment Editor-To中增加时钟名(from node finder)，Assignment Name中增加 和多时钟有关的Multicycle 和Multicycle Hold选项，如hold time为负，可使Multicycle hold的值multicycle,如设为2和1。 15: Cant analyze file - file E:/quartusii/*/*.v is missing 原因：试图编译一个不存在的文件，该文件可能被改名或者删除了 措施：不管他，没什么影响 16.Warning: Cant find signal in vector source file for input pin |whole|clk10m 原因：因为你的波形仿真文件（ vector source file ）中并没有把所有的输入信号(input pin)加进去，对于每一个输入都需要有激励源的 17.Error: Cant name logic scfifo0 of instance inst - has same name as current design file 原因：模块的名字和project的名字重名了 措施：把两个名字之一改一下，一般改模块的名字 18.Warning: Using design file lpm_fifo0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: lpm_fifo0 原因：模块不是在本项目生成的，而是直接copy了别的项目的原理图和源程序而生成的，而不是用QUARTUS将文件添加进本项目 措施：无须理会，不影响使用 19.Timing characteristics of device are preliminary 原因：目前版本的QuartusII只对该器件提供初步的时序特征分析 措施：如果坚持用目前的器件，无须理会该警告。关于进一步的时序特征分析会在后续版本的Quartus得到完善。 20.Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family 原因：用analyze_latches_as_synchronous_elements setting可以让Quaruts II来分析同步锁存，但目前的器件不支持这个特性 措施：无须理会。时序分析可能将锁存器分析成回路。但并不一定分析正确。其后果可能会导致显示提醒用户：改变设计来消除锁 存器 21.Warning:Found xx output pins without output pin load capacitance assignment（网友：gucheng82提供） 原因：没有给输出管教指定负载电容 措施：该功能用于估算TCO和功耗，可以不理会，也可以在Assignment Editor中为相应的输出管脚指定负载电容，以消除警告 22.Warning: Found 6 node(s) in clock paths which may be acting as ripple and/or gated clocks - node(s) analyzed as buffer(s) resulting in clock skew 原因：使用了行波时钟或门控时钟，把触发器的输出当时钟用就会报行波时钟，将组合逻辑的输出当时钟用就会报门控时钟 措施：不要把触发器的输出当时钟，不要将组合逻辑的输出当时钟，如果本身如此设计，则无须理会该警告 23.Warning (10268): Verilog HDL information at lcd7106.v(63): Always Construct contains both blocking and non-blocking assignments 原因： 一个always模块中同时有阻塞和非阻塞的赋值Quartus常见错误分析1 Warning: VHDL Process Statement warning at random.vhd(18): signal reset is in statement, but is not in sensitivity list-没把singal放到process（）中2 Warning: Found pins ing as undefined clocks and/or memory enablesInfo: Assuming node CLK is an undefined clock-=-可能是说设计中产生的触发器没有使能端3 Error: VHDL Interface Declaration error in clk_gen.vhd(29): interface object clk_scan of mode out cannot be read. Change object mode to buffer or inout. -信号类型设置不对，out当作buffer来定义4 Error: Node instance clk_gen1 instantiates undefined entity clk_gen -引用的例化元件未定义实体entity clk_gen5 Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks - node(s) analyzed as buffer(s) resulting in clock skewInfo: Detected ripple clock clk_gen:clk_gen1|clk_incr as bufferInfo: Detected ripple clock clk_gen:clk_gen1|clk_scan as buffer6 Warning: VHDL Process Statement warning at ledmux.vhd(15): signal or variable dataout may not be assigned a new in every possible path through the Process Statement. Signal or variable dataout holds its previous in every path with no new assignment, which may create a combinational loop in the current design.7 Warning: VHDL Process Statement warning at divider_10.vhd(17): signal cnt is read inside the Process Statement but isnt in the Process Statements sensivitity list -缺少敏感信号8 Warning: No clock transition on counter_bcd7:counter_counter_clk|q_sig3 register9 Warning: Reduced register counter_bcd7:counter_counter_clk|q_sig3 with stuck clock port to stuck GND10 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock class1 with clock skew larger than data delay. See Compilation Report for details.11 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock sign with clock skew larger than data delay. See Compilation Report for details.12 Error: VHDL error at counter_clk.vhd(90): actual port class of mode in cannot be associated with formal port class of mode out-两者不能连接起来13 Warning: Ignored node in vector source file. Cant find corresponding node name class_sig2 in design.-没有编写testbench文件，或者没有编辑输入变量的值 testbench里是元件申明和映射14 Error: VHDL Binding Indication error at freqdetect_top.vhd(19): port class in design entity does not have std_logic_vector type that is specified for the same generic in the associated component -在相关的元件里没有当前文件所定义的类型15 Error: VHDL error at tongbu.vhd(16): cant infer register for signal gate because signal does not hold its outside clock edge16 Warning: Found clock high time violation at 1000.0 ns on register |fcounter|lpm_counter:temp_rtl_0|dffs417 Warning: Compiler packed, optimized or synthesized away node temp19. Ignored vector source file node. -temp19被优化掉了18 Warning: Reduced register gatereg0 with stuck data_in port to stuck GND19 Warning: Design contains 2 input pin(s) that do not drive logicWarning: No output dependent on input pin clkWarning: No output dependent on input pin sign -输出信号与输入信号无关，20 Warning: Found clock high time violation at 16625.0 ns on register |impulcomp|gate121 Error: VHDL error at impulcomp.vhd(19): cant implement clock enable condition specified using binary operator or22 Error: VHDL Association List error at period_counter.vhd(38): actual parameter assigned to formal parameter alarm, but formal parameter is not declared-连接表错误，形参alarm赋值给实参，形参没定义，可能是形参与实参的位置颠倒了，规定形参在实参之前。23 Error: Ignored construct behavier at period_counter.vhd(15) because of previous errors因为前一个错误而导致的错误24 Error: VHDL error at period_counter.vhd(38): type of identifier alarm does not agree with its usage as std_logic typealarm的定义类型与使用的类型不一致25 Error: VHDL error at shift_reg.vhd(24): cant synthesize logic for statement with conditions that test for the edges of multiple clocks -同一进程中含有两个或多个if(edge)条件，（一个进程中之能有一个时钟沿）26 Error: Cant resolve multiple constant drivers for net datain_reg22 at shift_reg.vhd(19)27 cant infer register for signal num0 because signal does not hold its outside clock edge28Error: Cant elaborate top-level user hierarchy29 Error: Cant resolve multiple constant drivers for net cs_in at led_key.vhd(32) -有两个以上赋值语句，不能确定“cs_in”的值，30 Warning: Ignored node in vector source file. Cant find corresponding node name over in design.-在源文件中找不到对应的节点“over”。31 Error: Cant access JTAG chain 无法找到下载链32 Info: Assuming node clk is an undefined clock(原創) 如何解決warning：PLL output port feeds output pin via non-dedicated routing - jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance? (SOC) (Quartus II) (DE2-70) Abstract無論是自己開發的project，或者是DE2-70 CD上的範例，只要Quartus II編譯後，幾乎大家都會遇到這個warning，到底是什麼意思呢?該如何解決這個warning呢?Introduction使用環境：Quartus II 8.1+ DE2-70 (Cyclone II EP2C70F896C6N)小美與阿帥在(原創) 如何使用Pipeline Bridge增進Nios II系統的Fmax? (SOC) (Quartus II) (Nios II) (SOPC Builder) (DE2-70)成功解掉1個critical warning後，也開始對Quartus II其他warning感興趣，基本上大部分的warning的意義都很明確，也都能解掉，但對於以下這個warning，阿帥卡了很久還是解不掉：查了一下Quartus II 8.1的Help，這是Altera的官方回答並不是英文看不懂，只是看來看去，還是不知道該怎麼解決，最後小美與阿帥打算去請教無雙學長。小美與阿帥不錯喔，已經會開始注意Quartus II的warning了!哈哈哈，深入研究才發現，其實Quartus II warning很多都是蠻貼心的警告，就像寫Visual C+與gcc時，都會盡量讓warning不要出現，所以現在也希望盡量能解掉Quartus II的warning阿帥很自豪的回答。這樣的習慣不錯，這樣會讓你更了解Quartus II在做什麼。不過無雙學長話鋒一轉你問的這個問題，其實也困擾我很久，因為找不到解決方法，又暫時不影響結果，就先擱在一旁不管了，今天你又問起，我又仔細的研究了一番。在Altera Forum有人討論過這個問題/forum/showthread.php?t=1104，Ben與Brad講解的很清楚，你們兩個待會可以仔細閱讀他們的解釋，大至上的意思是說：由pll產生的clk，要ouput到專屬提供pll ouput的port，若output到非專屬pll output的port，Quartus II就會產生這個warning。這樣好抽像喔，學長可以講的更清楚些嗎?小美有聽沒有懂，還是滿臉疑惑。就用你們寫的code來講解好了.DE2_70.v / Verilog 1/* 2(C) OOMusou 2008 3 4Filename : DE2_70.v 5Compiler : Quartus II 8.1 6Description : Demo how to use TRDB-D5M with LTM on DE2-70 with Nios II 7Release : 12/18/2008 1.0 8*/ 910default_nettype none1112module DE2_70 (13 / Clock Input /14 input iCLK_28, / 28.63636 MHz15 input iCLK_50, / 50 MHz16 input iCLK_50_2, / 50 MHz17 input iCLK_50_3, / 50 MHz18 input iCLK_50_4, / 50 MHz19 input iEXT_CLOCK, / External Clock20 / Push Button /21 input 3:0 iKEY, / Pushbutton3:022 / DPDT Switch /23 input 17:0 iSW, / Toggle Switch17:024 / 7-SEG Dispaly /25 output 6:0 oHEX0_D, / Seven Segment Digit 026 output 6:0 oHEX1_D, / Seven Segment Digit 127 output 6:0 oHEX2_D, / Seven Segment Digit 228 output 6:0 oHEX3_D, / Seven Segment Digit 329 output 6:0 oHEX4_D, / Seven Segment Digit 430 output 6:0 oHEX5_D, / Seven Segment Digit 531 output 6:0 oHEX6_D, / Seven Segment Digit 632 output 6:0 oHEX7_D, / Seven Segment Digit 733 / LED /34 output 8:0 oLEDG, / LED Green8:035 output 17:0 oLEDR, / LED Red17:036 / SDRAM Interface /37 inout 31:0 DRAM_DQ, / SDRAM Data bus 32 Bits38 output 12:0 oDRAM0_A, / SDRAM0 Address bus 13 Bits39 output 12:0 oDRAM1_A, / SDRAM1 Address bus 13 Bits40 output oDRAM0_LDQM0, / SDRAM0 Low-byte Data Mask 41 output oDRAM1_LDQM0, / SDRAM1 Low-byte Data Mask 42 output oDRAM0_UDQM1, / SDRAM0 High-byte Data Mask43 output oDRAM1_UDQM1, / SDRAM1 High-byte Data Mask44 output oDRAM0_WE_N, / SDRAM0 Write Enable45 output oDRAM1_WE_N, / SDRAM1 Write Enable46 output oDRAM0_CAS_N, / SDRAM0 Column Address Strobe47 output oDRAM1_CAS_N, / SDRAM1 Column Address Strobe48 output oDRAM0_RAS_N, / SDRAM0 Row Address Strobe49 output oDRAM1_RAS_N, / SDRAM1 Row Address Strobe50 output oDRAM0_CS_N, / SDRAM0 Chip Select51 output oDRAM1_CS_N, / SDRAM1 Chip Select52 output 1:0 oDRAM0_BA, / SDRAM0 Bank Address53 output 1:0 oDRAM1_BA, / SDRAM1 Bank Address54 output oDRAM0_CLK, / SDRAM0 Clock55 output oDRAM1_CLK, / SDRAM1 Clock56 output oDRAM0_CKE, / SDRAM0 Clock Enable57 output oDRAM1_CKE, / SDRAM1 Clock Enable58 / Flash Interface /59 inout 14:0 FLASH_DQ, / FLASH Data bus 15 Bits (0 to 14)60 inout FLASH_DQ15_AM1, / FLASH Data bus Bit 15 or Address A-161 output 21:0 oFLASH_A, / FLASH Address bus 26 Bits62 output oFLASH_WE_N, / FLASH Write Enable63 output oFLASH_RST_N, / FLASH Reset64 output oFLASH_WP_N, / FLASH Write Protect /Programming Acceleration 65 input iFLASH_RY_N, / FLASH Ready/Busy output 66 output oFLASH_BYTE_N, / FLASH Byte/Word Mode Configuration67 output oFLASH_OE_N, / FLASH Output Enable68 output oFLASH_CE_N, / FLASH Chip Enable69 / SRAM Interface /70 inout 31:0 SRAM_DQ, / SRAM Data Bus 32 Bits71 inout 3:0 SRAM_DPA, / SRAM Parity Data Bus72 output 18:0 oSRAM_A, / SRAM Address bus 21 Bits73 output oSRAM_ADSC_N, / SRAM Controller Address Status 74 output oSRAM_ADSP_N, / SRAM Processor Address Status75 output oSRAM_ADV_N, / SRAM Burst Address Advance76 output 3:0 oSRAM_BE_N, / SRAM Byte Write Enable77 output oSRAM_CE1_N, / SRAM Chip Enable78 output oSRAM_CE2, / SRAM Chip Enable79 output oSRAM_CE3_N, / SRAM Chip Enable80 output oSRAM_CLK, / SRAM Clock81 output oSRAM_GW_N, / SRAM Global Write Enable82 output oSRAM_OE_N, / SRAM Output Enable83 output oSRAM_WE_N, / SRAM Write Enable84 / GPIO /85 inout 31:0 GPIO_0, / GPIO Connection 0 I/O86 input GPIO_CLKIN_N0, / GPIO Connection 0 Clock Input 087 input GPIO_CLKIN_P0, / GPIO Connection 0 Clock Input 188 inout GPIO_CLKOUT_N0, / GPIO Connection 0 Clock Output 089 inout GPIO_CLKOUT_P0, / GPIO Connection 0 Clock Output 190 inout 31:0 GPIO_1, / GPIO Connection 1 I/O91 input GPIO_CLKIN_N1, / GPIO Connection 1 Clock Input 092 input GPIO_CLKIN_P1, / GPIO Connection 1 Clock Input 193 inout GPIO_CLKOUT_N1, / GPIO Connection 1 Clock Output 094 inout GPIO_CLKOUT_P1, / GPIO Connection 1 Clock Output 195 / SD Card Interface /96 inout SD_DAT, / SD Card Data97 inout SD_DAT3, / SD Card Data 398 inout SD_CMD, / SD Card Command Signal99 output oSD_CLK / SD Card Clock100);101102/ ltm103wire 7:0 ltm_r; / ltm red data 8 bits104wire 7:0 ltm_g; / ltm green data 8 bits105wire 7:0 ltm_b; / ltm blue data 8 bits106wire ltm_nclk; / ltm clcok107wire ltm_hd; / ltm h.sync108wire ltm_vd; / ltm v.sync109wire ltm_den; / ltm data enable110111/ ltm config112wire ltm_sclk; / ltm I2S clk113wire ltm_scen; / ltm I2s clk enable114wire adc_ltm_sclk; / acd_ltm I2s clk enable115wire ltm_grst; / ltm reset116117assign ltm_grst = iKEY0; / ltm rest118assign adc_ltm_sclk = ltm_sclk; / ltm