CPLD课程设计代码.doc

附：程序代码注：译码器，分频，点阵，流水灯，步进电机五部分为源代码的功能拓展，带下划线部分为修改或添加的代码。交通灯，多路选择器为编写设计代码。1、译码器：LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY decoder3_8 IS PORT( A,B,C: IN STD_LOGIC; Y :OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -段选输出 en :OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); -位选输出 END decoder3_8; ARCHITECTURE fun OF decoder3_8 IS SIGNAL indata: STD_LOGIC_VECTOR(2 DOWNTO 0) ; BEGIN indata Y=01000000;enY=01111001;enY=00100100;enY=00110000;enY=00011001;enY=00010010;enY=00000010;enY=01111000;enY=11111111;en=00000000; END CASE; END PROCESS encoder; END fun;2、分频：library ieee;use ieee.std_logic_1164.all;entity div_f isport(clk :in std_logic; miao_out :out std_logic; f_miao_out:out std_logic; fourhz :out std_logic; - 4Hz 输出 halfhz :out std_logic; -0.5Hz输出 en :out std_logic);end div_f;architecture miao of div_f isbeginen=1;p1:process(clk)variable cnt:integer range 0 to 3999999;variable ff:std_logic;beginif clkevent and clk=1 thenif cnt3999999 thencnt:=cnt+1;elsecnt:=0;ff:=not ff;end if;end if;miao_out=ff;end process p1;p2:process(clk)variable cnn:integer range 0 to 1999999;variable dd:std_logic;beginif clkevent and clk=1 thenif cnn1999999 thencnn:=cnn+1;elsecnn:=0;dd:=not dd;end if;end if;f_miao_out=dd;end process p2;-p3：4Hz生成部分-p3:process(clk)variable cnt0:integer range 0 to 999999;variable aa:std_logic;beginif clkevent and clk=1 thenif cnt0999999 thencnt0:=cnt0+1;elsecnt0:=0;aa:=not aa;end if;end if;fourhz=aa;end process p3;-p4：0.5Hz生成部分-p4:process(clk)variable cnn0:integer range 0 to 7999999;variable bb:std_logic;beginif clkevent and clk=1 thenif cnn07999999 thencnn0:=cnn0+1;elsecnn0:=0;bb:=not bb;end if;end if;halfhz=bb;end process p4;end miao;3、 点阵library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY dianzhen ISPORT(clk:IN STD_LOGIC; l : out STD_LOGIC_VECTOR(7 downto 0); b : out STD_LOGIC_VECTOR(7 downto 0) );END dianzhen;ARCHITECTURE led OF dianzhen ISsignal clk_1k:std_logic;signal clk_1h:std_logic;signal p,c:integer range 0 to 7;BEGIN-与源代码分频方式不同，效果相同-process(clk)variable cnt0:integer range 0 to 24676;beginif clkevent and clk=1thenif cnt0=24676 thencnt0:=0;clk_1ksmg7:=X00;WHEN 1=smg7:=X1C;WHEN 2=smg7:=X14;WHEN 3=smg7:=XFF;WHEN 4=smg7:=X14;WHEN 5=smg7:=X1C;WHEN 6=smg7:=X00;WHEN 7=smg7:=X00;END CASE;RETURN smg7;END word;variable cnt:integer range 0 to 63;beginif clk_1kevent and clk_1k=1 thenp=p+1;if cnt=63 thencnt:=0;clk_1hb=11111110;lb=11111101;lb=11111011;lb=11110111;lb=11101111;lb=11011111;lb=10111111;lb=01111111;l=word(c+7);end case;end process;process(clk_1h)variable cnt:integer range 0 to 7;beginif clk_1hevent and clk_1h=1thenc=c+1;end if;end process;end led;4、流水灯：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY led_lsd ISPORT(clk:IN STD_LOGIC; - spd:in bit;-控制速度- con:in bit;-控制方向- r:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -点阵行控制 c:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -点阵列控制 -END led_lsd;ARCHITECTURE behav OF led_lsd ISSIGNAL SLIP :STD_LOGIC_VECTOR(5 DOWNTO 0);-SIGNAL miao_out:STD_LOGIC;begin-分出两个不同的频率- process(clk)variable cnt:integer range 0 to 399999;variable ff:std_logic;variable cnt0:integer range 0 to 1000000;variable ff0:std_logic;beginif clkevent and clk=1 then if cnt399999 then cnt:=cnt+1; else cnt:=0; ff:=not ff; end if; if cnt01000000 then cnt0:=cnt0+1; else cnt0:=0; ff0:=not ff0; end if;end if;-速度选择- if(spd=1)thenmiao_out=not ff;elsif(spd=0)thenmiao_out=not ff0;end if;end process;-PROCESS(miao_out)BEGINIF miao_outEVENT AND miao_out=1THEN-方向选择控制-if(con=1)then SLIP=SLIP+1;elsif(con=0)then SLIPr=00000011;cr=00000011;cr=00000011;cr=00000011;cr=00000011;cr=00000011;cr=00000011;cr=00000001;cr=00000010;cr=00000100;cr=00001000;cr=00010000;cr=00100000;cr=01000000;cr=10000000;cr=11000000;cr=11000000;cr=11000000;cr=11000000;cr=11000000;cr=11000000;cr=10000000;cr=01000000;cr=00100000;cr=00010000;cr=00001000;cr=00000100;cr=00000010;cr=00000001;cr=11011011;cr=00000000;cr=11011011;cr=00000001;cr=00000010;cr=00000100;cr=00001000;cr=00010000;cr=00100000;cr=01000000;cr=10000000;cr=11000000;cr=11000000;cr=11000000;cr=11000000;cr=11000000;cr=11000000;cr=10000000;cr=01000000;cr=00100000;cr=00010000;cr=00001000;cr=00000100;cr=00000010;cr=00000001;cr=00000011;cr=00000011;cr=00000011;cr=00000011;cr=00000011;cr=00000011;cr=00000011;cr=11100111;cr=00000000;cr=11100111;c=00011000;-END CASE;END PROCESS;END behav;5、 步进电机：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY state_machine IS PORT ( clk :IN std_logic; rst :IN std_logic; spd :in bit;-速度控制- con :in bit;-方向控制- c :OUT std_logic_vector(3DOWNTO 0);END state_machine;ARCHITECTURE arch OF state_machine ISCONSTANT state0 : std_logic_vector(2 DOWNTO 0):=000;CONSTANT state1 : std_logic_vector(2 DOWNTO 0):=001;CONSTANT state2 : std_logic_vector(2 DOWNTO 0):=010;CONSTANT state3 : std_logic_vector(2 DOWNTO 0):=011;CONSTANT state4 : std_logic_vector(2 DOWNTO 0):=100;CONSTANT state5 : std_logic_vector(2 DOWNTO 0):=101;CONSTANT state6 : std_logic_vector(2 DOWNTO 0):=110;CONSTANT state7 : std_logic_vector(2 DOWNTO 0):=111;SIGNAL state :std_logic_vector(2 DOWNTO 0);SIGNAL KEY :std_logic_vector(2 DOWNTO 0); BEGIN PROCESS(clk,rst) -实现两个分频- variable cnt:integer range 0 to 5999;- variable cnt0:integer range 0 to 9999;- variable ff:std_logic; BEGIN IF(NOT rst=1)THEN state state state state state state state state state state state state state state state state state c c c c c c c c NULL; END CASE; elsif(con=0)then CASE state IS WHEN state0= c c c c c c c c NULL; END CASE; end if; - END PROCESS;END arch; 6、 多路选择器（四选一）：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity selc isport( a,b,c,d:in bit;-四路信号- s:in std_logic_vector( 1 downto 0 );-选择信号- data:out std_logic_vector( 7 downto 0 );-数码管段选 en:out std_logic_vector( 3 downto 0 );-位选-end selc;architecture chose of selc issignal s0:bit;beginprocess(a,b,c,d,s)beginif(s=00)thens0data=11111001;endata=11000000;en=0001;end case;elsif(s=01)thens0data=11111001;endata=11000000;en=0010;end case;elsif(s=10)thens0data=11111001;endata=11000000;en=0100;end case;elsif(s=11)thens0data=11111001;endata=11000000;enclk1,rst=rst,clkout=b);u2:counter port map(clock=b,con=con1,countnum=c);u3:controller port map(Clock=b,con=con1,CountNum=c,NumA=d,r=r1,y=y1, g=g1,ryg1=ryg10,ryg2=ryg20,ryg3=ryg30,ryg4=ryg40);u4:fenwei port map(Numin=d,NumA=e,NumB=f);u5:scan port map(clk=clk1,NumA=e,NumB=f,segout1=segout2,led_sel=led_sel1);end behavioral;底层文件分频模块：library ieee;use ieee.std_logic_1164.all;entity div_f isport(clk :in std_logic; clkout :out std_logic; rst :in std_logic);end div_f;architecture miao of div_f isbeginprocess(clk)variable cnt:integer range 0 to 3999999;variable ff:std_logic;begin if rst=0 then cnt:=0; elsif clkevent and clk=1 then if cnt3999999 then cnt:=cnt+1; else cnt:=0; ff:=not ff; end if; end if;clkout=ff;end process;end miao;计数模块：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity counter isport(clock:in std_logic; con :in std_logic; countnum:buffer integer range 0 to 22);-15秒的主方向绿灯加8秒的次方向end counter;-的绿灯（包括黄灯时间）architecture behavioral of counter isbegin process(clock)beginif rising_edge(clock)thenif con=0 thencountnum=countnum;elseif countnum=22 thencountnum=0;else countnum=30 thenNumA=0;NumB=20 then NumA=2;NumB=10 then NumA=1;NumB=Numin-10;else NumA=0;NumB=Numin;end if;end process;end behavioral;控制模块：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity controller is port(Clock:in std_logic; con :in std_logic; CountNum:in integer range 0 to 22; NumA :out integer range 0 to 22; r,y,g,ryg1:out std_logic; ryg2,ryg3,ryg4:out std_logic );end controller;architecture behavioral of controller isbeginprocess(Clock)beginif falling_edge(Clock)then-紧急控制if con=0thenr=1;y=0;g=0;ryg1=0;ryg2=0;ryg3=0;ryg4=0;elsif CountNum=11 then-主向绿灯-NumA=15-CountNum;r=1;y=0;g=1;ryg1=1;ryg2=1;ryg3=0;ryg4=0;elsif CountNum=14 then-主向黄灯-NumA=15-CountNum;r=1;y=1;g=0;ryg1=1;ryg2=1;ryg3=0;ryg4=0;elsif CountNum=19 then-次向绿灯NumA=23-CountNum;r=1;y=0;g=1;ryg1=0;ryg2=0;ryg3=1;ryg4=1;elsif CountNum=22 then-次向黄灯-NumA=23-CountNum;r=1;y=1;g=0;ryg1=0;ryg2=0;ryg3=1;ryg4segoutsegoutsegoutseg