《微型计算机原理及应用技术》程序代码.doc

微型计算机原理及应用技术编程程序目录：2分频电路N分频电路（8选一为例）多进制加法计数器基本D触发器数据选择器（四选一）异步复位可逆计数器优先编码器2分频电路library ieee;use ieee.std_logic_1164.all;entity fredvider1 isport(clock:in std_logic;clkout:out std_logic);end;architecture behavior of fredvider1 issignal clk:std_logic;begin process(clock) begin if rising_edge(clock) then clk=not clk; end if; end process; clkout=clk;end;N分频电路（8选一为例）library ieee;use ieee.std_logic_1164.all;entity fredevider8 isport (clkin:in std_logic; clkout:out std_logic);end;architecture bhv of fredevider8 isconstant n:integer:=3;signal counter:integer range 0 to N;signal clk:std_logic;begin process(clkin) begin if rising_edge(clkin) then if counter = n then counter =0; clk = not clk; else counter = counter+1; end if; end if;end process;clkout = clk;end;多进制加法计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity count2 is port (cp,res:in std_logic; ql,qh:out std_logic_vector(3 downto 0);end;architecture bhv of count2 issignal qnl,qnh:std_logic_vector(3 downto 0);beginprocess(cp,res) begin if res = 1 then qnl=0000;qnh=0000; elsif rising_edge(cp) then if qnl=0011 and qnh=0010 then qnl=0000; qnh=0000; elsif qnl=1001 then qnl=0000;qnh=qnh+1; else qnl=qnl+1; end if; end if;end process; ql = qnl; qh = qnh;end;基本D触发器library ieee;use ieee.std_logic_1164.all;entity dff1 is port( d: in std_logic; clk: in std_logic; q: out std_logic);end;architecture bhv of dff1 is signal qn: std_logic;beginprocess(clk) begin if rising_edge(clk) then qn=d; end if;end process;q= qn;end;异步复位的D触发器library ieee;use ieee.std_logic_1164.all;entity dff2 isport(D,clk,clr: in std_logic; Q: out std_logic); 定义输入、输出端口end entity dff2;architecture one of dff2 isbegin process(clk,D,clr) 进程敏感信号 begin if clr=1 then Q=0; Elsif clkevent and clk=1 then 时钟触发状态 Q=D; end if; end process;end architecture one;同步复位的D触发器library ieee;use ieee.std_logic_1164.all;entity dff1 isport(D,clk,clr: in std_logic;Q: out std_logic); 定义输入、输出端口end entity dff1;architecture one of dff1 isbeginprocess(clk,D,clr) 进程敏感信号Beginif clkevent and clk=1 then 时钟控制优先 if clr=1 then Q=0; else Qclkoutclkoutclkoutclkoutclkout =0; end case; end process;end;异步复位可逆计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity count1 is port (cp,res,dir:in std_logic; q:out std_logic_vector(3 downto 0);end;architecture bhv of count1 issignal qn:std_logic_vector(3 downto 0);beginprocess(cp,res) begin if res = 1 then qn=0000; elsif rising_edge(cp) then if dir=0 then qn=qn+1; else qn=qn-1; end if; end if; q = qn;end process;end;优先编码器library ieee;use ieee.std_logic_1164.all;entity encoder isport(en:in std_logic;i:in std_logic_vector(7 downto 0);a:out std_logic_vector(2 downto 0);idle:out std_logic);end;architecture behacior of encoder isbegin process(en,i) begin if en = 1 then if i(7) = 1 then a=111; idle=0; elsif i(6) = 1 then a=110; idle=0; elsif i(5) = 1 then a=101; idle=0; elsif i(4) = 1 then a=100; idle=0; elsif i(3) = 1 then a=011; idle=0; elsif i(2) = 1 then