脚本学习记录总结.doc

脚本学习记录总结 脚本学习记录总结多参考一些DC的专业脚本.synopsys_dc.setup#Library Setup#set sh_enable_line_editing trueEnables themand lineediting capabilities.This variableis foruse inTcl modeonly.If setto trueit enablesadvanced UNIXlike shellcapabilities.This variableneeds tobe setin the.synopsys_dc.setup fileto takeeffect.set gui_autostart0set default_report_significant_digits4#上面这三条指令一般都放在.synopsys_dc.setup file中，而且一般的.synopsys_dc.setup file中都会有这三条指令；？这上面三个是干什么的？sourceechoverbose dc_setup.tcl Reada fileand evaluateit asa Tclscript;echo Echoeseach mandas it is executed.verbose Displaysthe resultof eachmand executed.Note thaterror messagesare displayedregardless.dc_setup.tcl sourceechoverbose mon_setup.tcl#Design CompilerTopDown ReferenceMethodology Setup#Script:dc_setup.tcl#Version:Bxx.09(Oct.3,xx)#Copyright(C)xx,xxSynopsys Allrights reserved.#set RTL_SOURCE_FILESclk_gen.vclk_div3.voc8051_a.voc8051_alu_src_sel.voc8051_alu.voc8051_b_register.voc8051_p.voc8051_cy_select.voc8051_decoder.voc8051_defines.voc8051_divide.voc8051_dptr.voc8051_indi_addr.voc8051_int.voc8051_mem_interface.voc8051_multiply.voc8051_p0.voc8051_p1.voc8051_p2.voc8051_p3.voc8051_psw.voc8051_ram_256x8_two_bist.voc8051_ram_sel_reg.voc8051_ram_sel.voc8051_ram_top.voc8051_sfr.voc8051_spi_ic.voc8051_spi_top.voc8051_sp.voc8051_tc2.voc8051_tc.voc8051_top_pad.voc8051_top_stardard.voc8051_uart.vrw_flash_defines.vrw_flash.vsadr_dat_inout.vspi_sfr.vset REPORTS_DIRreportsset RESULTS_DIRresultsfile mkdir$REPORTS_DIRfile mkdir$RESULTS_DIRset search_path.$ADDITIONAL_SEARCH_PATH$search_path#Milkyway variablesettings#Make sureto defihe followingMilkyway libraryvariables#mw_logic1_,mw_logic0_ andmw_design_library areneeded bywrite_milkyway set mw_logic1_$MW_POWER_NETset mw_logic0_$MW_GROUND_NETset mw_reference_library$MW_REFERENCE_LIB_DIRSset mw_design_library8051_4m？这个在哪？还是只是个定义？setmw_site_name_mappinglist COREunit Coreunit coreunit？这是干嘛的？#The remainderof thesetup belowshould onlybe performedin DesignCompiler#Include alllibraries formultiVth leakagepower optimizationset target_library$TARGET_LIBRARY_FILESset synthetic_library dw_foundation.sldb setlink_library*$target_library$ADDITIONAL_LINK_LIB_FILES$synthetic_library#Set minlibraries ifthey existforeachmax_library min_library$MIN_LIBRARY_FILESset_min_library$max_librarymin_version$min_library？这个循环下去到底用哪一个？#/？这下面是干嘛的？ifshell_is_in_topographical_mode#Only createnew MWdesign libraryif itdoesnt alreadyexist if!file isdirectory$mw_design_librarycreate_mw_libtechnology$TECH_FILEmw_reference_library$mw_reference_library$mw_design_libraryelse#If MWdesign libraryalready exists,ensure thatit isconsistent withspecified MWreference librariesset_mw_lib_reference$mw_design_librarymw_reference_library$mw_reference_libraryopen_mw_lib$mw_design_library check_library set_tlu_plus_filesmax_tluplus$TLUPLUS_MAX_FILEmin_tluplus$TLUPLUS_MIN_FILEtech2itf_map$MAP_FILE check_tlu_plus_files#/#Add anyICCILMs to the linklibrary#If youare usingICCILMs in DCWLM mode,you willneed#to useMilkyway library setup inDC WLM mode aswell.#In thatcase,remove theifshell_is_in_topographical_mode#to includethis MWlibrarysetupinDCWLMmode.#foreach ICC_ILM_NAME$ICC_ILM_HIER_DESIGNS#lappend link_library$ICC_ILM_NAME.ILM#Library Modifications#Apply librarymodifications hereafter thelibraries areloaded.#source dont_use.tclmon_setup.tcl#Variables monto allRM scripts#Script:mon_setup.tcl#Version:Bxx.09(Oct.3,xx)#Copyright(C)xx,xxSynopsys Allrights reserved.自定义的变量用大写字母来表示；#set DESIGN_NAMEfinal_top;#The nameof thetoplevel designset DESIGN_REF_DATA_PATH/home/winhshiw/work/OC8051_DC_Synthesis;#主目录#set ADDITIONAL_SEARCH_PATH$DESIGN_REF_DATA_PATH/rtl/8051_final_rtl_09_13$DESIGN_REF_DATA_PATH/scripts$DESIGN_REF_DATA_PATH/lib$DESIGN_REF_DATA_PATH/lib/db;#Additional searchpath tobe addedtothedefault searchpath setTARGET_LIBRARY_FILESslow.db;#Target technologylogical libraries,worst_case;set ADDITIONAL_LINK_LIB_FILEStpz973gvwc.db RA2SH_11x32_slow.db RA1SHD_10x8_slow.db;#Extra linklogical librariesnot includedin TARGET_LIBRARY_FILES,包括memory,IO等set MIN_LIBRARY_FILESslow.db fastcold.dbtpz973gvwc.db tpz973gvlt.dbRA2SH_11x32_slow.db RA2SH_11x32_fast40C.dbRA1SHD_10x8_slow.db RA1SHD_10x8_fast40C.db;#List ofmax minlibrary pairsmax1min1max2min2max3min3.set MW_REFERENCE_LIB_DIRS$DESIGN_REF_DATA_PATH/lib/mw_lib/SC$DESIGN_REF_DATA_PATH/lib/mw_lib/tpz973gv$DESIGN_REF_DATA_PATH/lib/mw_lib/RA2SH_11x32$DESIGN_REF_DATA_PATH/lib/mw_lib/RA1SHD_10x8;#Milkyway referencelibraries(include ICCILMs here)set TECH_FILElib/tf/tsmc18_4lm.tf;#Milkyway technologyfile setMAP_FILElib/t18.map;#Mapping filefor TLUplusset TLUPLUS_MAX_FILElib/t018s4ml.tluplus;#Max TLUplusfile setTLUPLUS_MIN_FILElib/t018s4ml.tluplus;#Min TLUplusfile set MW_POWER_NETVDD;#set MW_POWER_PORTVDD;#set MW_GROUND_NETVSS;#setMW_GROUND_PORTVSS;#set MIN_ROUTING_LAYER;#Min routinglayer setMAX_ROUTING_LAYER;#Max routinglayer dc.tcl#run all#set_svf$RESULTS_DIR/$DESIGN_NAME.mapped.dct.svf saif_mapstart？这上面三个是干什么的？define_design_lib WORKpath./WORK analyzeformat verilog$RTL_SOURCE_FILESelaborate$DESIGN_NAMElink set_dont_touchtest*clk*u*？是什么object oncells,s,references,and designsin thecurrent design？sourceechoverbose top_constraints.tcl#DTC physicalconstraint extraction#extract_physical_constraints results/floorplan_final.def#set_utilization0.99#report_physical_constraints#set_congestion_optionslayer METAL4availability0.96#set_congestion_optionslayer METAL3availability0.96#set_congestion_optionslayer METAL1availability0.5#report_congestion_optionsall#read_saifauto_map_namesinput lib/soc.saifinstance_name tbverbose#set_max_leakage_power0#set_max_dynamic_power0#set high_fanout_threshold60#set high_fanout_pin_capacitance0.01pile_ultrascannum_cpus4#Specifies thenumber ofCPUs touse duringpile.这个是说电脑的cpu使用率吗？#timing_high_effort_scriptcongestion#congestion writeformat ddchierarchyoutput results/$DESIGN_NAME.pre_dft.ddc#dft#sourceechoverbose dft.tcl？DFT部分set_ideal_workno_propagateall_high_fanouts?#pile_ultrascannum_cpus4timing_high_effort_scriptcongestion pile_ultrascannum_cpus4incremental#congestion#write thefinal info#remove_attributeP*dont_touch uniquifyforce change_namesrules veriloghierarchy write_sdcnosplit results/$DESIGN_NAME.mapped.sdc write_scan_defoutput results/$DESIGN_NAME.mapped.scandef write_test_protocolnames verilogoutput results/$DESIGN_NAME.mapped.spf set_svfoff writeformat ddchierarchyoutput results/$DESIGN_NAME.mapped.ddc writef veriloghierarchyoutput results/$DESIGN_NAME.mapped.v write_saifoutput results/dc_133_sdram.saif top_constraints.tcl#TOP Constraintsfor designCore#set all_in_ex_clkremove_from_collectionall_inputsget_portslist XTAL1#create_generated_clockname DIV_CLKsourceget_ports clk_paddivide_by3get_pins oc8051_oc8051_clk_div/clk_out#create_generated_clockname DIV_CLKsourceget_ports clk_paddivide_by3get_pins oc8051_oc8051_clk_div_q2_reg/Q#create_generated_clockname DIV_CLKsourceget_ports clk_paddivide_by3get_pins oc8051_oc8051_clk_div/clk_out#create_generated_clockname DIV_CLKsourceget_ports XTAL1divide_by3get_pins oc8051/oc8051_clk_div/q2_reg/Qinvert create_generated_clockname DIV_CLKsourceget_ports XTAL1divide_by3get_pins oc8051/oc8051_clk_div_q2_reg/Qinvert?这个到底是dont touch还是1/3？这种设置是因为硬件上已经是1/3才能这样设，而不是说这样设置就会产生1/3的时钟？invert具体是干什么的啊？翻转？即相位相差180？create_clockget_ports XTAL1period20#即就当可以运行50MHz#create_clockget_ports clk_padperiod20set_clock_uncertaintysetup0.1get_clocks XTAL1#set_max_delayfrom XTAL1to oc8051/oc8051_clk_div_q2_reg/CKN4#additional constraints#set ports_clock_rootget_portsall_fanoutflatclock_treelevel0?all_fanout到底干什么的？group_pathname REGOUTtoall_outputsgroup_pathname REGINfromremove_from_collectionall_inputs$ports_clock_rootgroup_pathname FEEDTHROUGHfromremove_from_collectionall_inputs$ports_clock_roottoall_outputs#Make clocks,scan_en,and constantsDRC freeset_auto_disable_drc_sall;？#itismean this donot repairthe drcerrorall includethe clocksa_en andconstants signals#Set clocksas idealworks set_ideal_workget_portsXTAL1;#this meanthe s transitionand capasityboth is0;？这个与dont touch有什么区别呢？#Make allreset signalsideal？这个注释有些不妥吧？set_ideal_workno_propagateget_s rst_pad#Leave optimizationof thescan_en buffertree tothe physicaltools set_false_pathfromget_portstest_en_pad;#for tristate bus,test_en_pad mustconsiderto？#set_ideal_workno_propagateall_high_fanouts;#its importent#set_app_var timing_enable_multiple_clocks_per_reg true#set_app_var case_analysis_with_logic_constants trueset_fix_multiple_port_sallbuffer_constants?这是干嘛的？set_wire_load_modelname tsmc18_wl10set_wire_load_mode top#Set t