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高频
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高频电路实训装置资料,高频,电路,装置,资料
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Tianjin University of Technology and Education毕 业 论 文专 业： 应用电子技术教育 班级学号： 0201 - 14 学生姓名： 何锦荣 指导教师： 李杰 副教授 二七年六月天津工程师范学院本科生毕业设计（论文）高频电路实训装置High Frequency Circuit Training Device专业班级：应教 0201学生姓名：何锦荣指导教师：李杰 副教授系 别：电子工程系2007 年 6 月摘 要本高频电路实训装置结合了经典的高频实用电路，把多个高频电子线路模块集成在一个实训箱里面，应用多种抗干扰技术，使模块各自独立工作而不互相干扰。实验箱分别由晶体管振荡电路，AM 发射机电路，AM 接收机电路，FM 发射机电路，FM 接收机电路，FSK 调制电路，FSK 解调电路， CPLD 频率计电路，系统电源电路模块等组成。每个模块电路的主要信号都引出相应得测试端子，学生可通过观测测试端子的信号参数来近一步理解和学习高频电子线路，每个模块都贴近于实践，具有很强的实践性和应用。每个模块的单元电路都使用跳线的短路端子断开相应功能的单元，以便能更好的减少后极对前极单元的影响，使学生能更好的理解和掌握高频电子线路的信号流程。该实训装置可为无线电调试技术工种提供职业技能训练和职业技能鉴定使用的教学仪器。关键词：高频电子线路 实训箱 模块化设计 测试端子 ABSTRACTThe high frequency circuit practical equipment which integrates multi high frequency circuitry combines with classical high frequency practical circuit, and applies multi anti-molestation technology, which makes every module works independently. This high frequency circuits, which made up of crystal oscillator circuit, FM transmitter circuit, FSK modulation and demodulation circuits, frequency meter circuit and system power. The main signal of every module has a testing terminal; Students can use the parameter by observing the testing terminal to make more study. Every module has strong practice and application ability. The cell circuit of every module use jumping line of shot circuit terminal to cut the relevant function, so that reduce the infection of former distinction from latter distinction, and then students can understand the signal flow of high frequency nicely. This equipment can be used as a teaching equipment of professional technology training and appraisal of wireless debugging technology.Keywords: high frequency circuit communication design jumping line of shot circuit classical high frequency practical circuit 天津工程师范学院 2007 届本科生毕业设计1英文资料S3C2442B 32-BIT RISC APPLICATION PROCESSORUSERS MANUALINTRODUCTION This users manual describes SAMSUNGs SC32442B 16/32-bit RISC microprocessor. SAMSUNGs SC32442B is designed to provide hand-held devices and general applications with low-power, and high-performance micro-controller solution in small die size. To reduce total system cost, the SC32442B includes the following components. The SC32442B is developed with ARM920T core, 0.13um CMOS standard cells and a memory complier. Its low-power, simple, elegant and fully static design is particularly suitable for cost- and power-sensitive applications. It adopts a new bus architecture known as Advanced Micro controller Bus Architecture (AMBA). The SC32442B offers outstanding features with its CPU core, a 16/32-bit ARM920T RISC processor designed by Advanced RISC Machines, Ltd. The ARM920T implements MMU, AMBA BUS, and Harvard cache architecture with separate 16KB instruction and 16KB data caches, each with an 8-word line length. By providing a complete set of common system peripherals, the SC32442B minimizes overall system costs and eliminates the need to configure additional components. The integrated on-chip functions that are described in this document include: Around 400MHz1.5V arm and 1.5V internal, 300MHz1.35V arm and 1.35V internal, 1.8Vmemory, 3.3V external I/O microprocessor with 16KB I-Cache/16KB D-Cache/MMU External memory controller (SDRAM Control and Chip Select logic) LCD controller (up to 4K color STN and 256K color TFT) with LCD-dedicated DMA 4-ch DMA controllers with external request pins 3-ch UARTs (IrDA1.0, 64-Byte Tx FIFO, and 64-Byte Rx FIFO) 2-ch SPls IIC bus interface (multi-master support) IIS Audio CODEC interface SD Host interface version 1.0 & MMC Protocol version 2.11 compatible 2-ch USB Host controller / 1-ch USB Device controller (ver 1.1) 4-ch PWM timers / 1-ch Internal timer / Watch Dog Timer 8-ch 10-bit ADC and Touch screen interface RTC with calendar function Camera interface (Max. 4096 x 4096 pixels input support. 2048 x 2048 pixel input support for scaling) 130 General Purpose I/O ports / 24-ch external interrupt source 天津工程师范学院 2007 届本科生毕业设计2 Power control: Normal, Slow, Idle, stop and Sleep mode On-chip clock generator with PLL FEATURES Architecture Integrated system for hand-held devices and general embedded applications. 16/32-Bit RISC architecture and powerful instruction set with ARM920T CPU core. Enhanced ARM architecture MMU to support WinCE, EPOC 32 and Linux. Instruction cache, data cache, write buffer and Physical address TAG RAM to reduce the effect of main memory bandwidth and latency on performance. ARM920T CPU core supports the ARM debug architecture. Internal Advanced Microcontroller Bus Architecture (AMBA) (AMBA2.0, AHB/APB). System Manager Little/Big Endian support. Support Fast bus mode and Asynchronous bus mode. Address space: 128M bytes for each bank (total 1G bytes). Supports programmable 8/16/32-bit data bus width for each bank. Fixed bank start address from bank 0 to bank 6. Programmable bank start address and bank size for bank 7. Eight memory banks: Six memory banks for ROM, SRAM, Two memory banks for ROM/SRAM/ Synchronous DRAM. Complete Programmable access cycles for all memory banks. Supports external wait signals to expand the bus cycle. Supports self-refresh mode in SDRAM for power-down. Supports various types of ROM for booting (NOR/NAND Flash, EEPROM, and others). NAND Flash Boot Loader Supports booting from NAND flash memory. 4KB internal buffer for booting. Supports storage memory for NAND flash memory after booting. Supports Advanced NAND flash Cache Memory 64-way set-associative cache with I-Cache (16KB) and D-Cache (16KB). 8words length per line with one valid bit and two dirty bits per line. Pseudo random or round robin replacement algorithm. Write-through or write-back cache operation to update the main memory. The write buffer can hold 16 words of data and four addresses. Clock & Power Manager On-chip MPLL and UPLL: UPLL generates the clock to operate USB Host/Device. MPLL generates the clock to operate MCU at maximum 400MHz1.5V arm and 1.5V internal, 天津工程师范学院 2007 届本科生毕业设计3300MHz1.35V arm and 1.35V internal,. Clock can be fed selectively to each function block by software. Power mode: Normal, Slow, Idle, Deep-stop and Sleep mode Normal mode: Normal operating mode Slow mode: Low frequency clock without PLL Idle mode: The clock for only CPU is stopped. Stop mode: All clocks are stopped. Deep-Stop mode: Arm power off internal clocks are stopped. Sleep mode: The Core power including all peripherals is shut down. Woken up by EINT15:0 or RTC alarm interrupt from Sleep mode Stacked Memory 256Mbit or 512Mbit mSDR x32, VDD=1.8V 512Mbit or 1Gbit Nand Flash x8, VDD=1.8V Interrupt controller 59 Interrupt sources (One Watch dog timer, 5 timers, 9 UARTs, 24 external interrupts, 4 DMA, 2 RTC, 2 ADC, 1 IIC, 2 SPI, 1 SDI, 2 USB, 1 LCD, 1 Battery Fault, 1 NAND and 2 Camera) Level/Edge mode on external interrupt source Programmable polarity of edge and level Supports Fast Interrupt request (FIQ) for very urgent interrupt request Timer with Pulse Width Modulation (PWM) 4-ch 16-bit Timer with PWM / 1-ch 16-bit internal timer with DMA-based or interrupt-based operation Programmable duty cycle, frequency, and polarity Dead-zone generation Supports external clock sources RTC (Real Time Clock) Full clock feature: msec, second, minute, hour, date, day, month, and year 32.768 KHz operation Alarm interrupt Time tick interrupt RTC Low Battery Check General Purpose Input/Output Ports 24 external interrupt ports 130 Multiplexed input/output ports DMA Controller 4-ch DMA controller Supports memory to memory, IO to memory, memory to IO, and IO to IO transfers Burst transfer mode to enhance the transfer rate 天津工程师范学院 2007 届本科生毕业设计4 LCD Controller STN LCD Displays Feature Supports 3 types of STN LCD panels: 4-bit dual scan, 4-bit single scan, 8-bit single scan display type Supports monochrome mode, 4 gray levels, 16 gray levels, 256 colors and 4096 colors for STN LCD Supports multiple screen size Typical actual screen size: 640x480, 320x240, 160x160, and others. Maximum frame buffer size is 4 Mbytes. Maximum virtual screen size in 256 color mode: 4096x1024, 2048x2048, 1024x4096 and others TFT(Thin Film Transistor) Color Displays Feature Supports 1, 2, 4 or 8 bpp (bit-per-pixel) palette color displays for color TFT Supports 16, 24 bpp non-palette true-color displays for color TFT Supports maximum 16M color TFT at 24 bpp mode LPC3600 Timing controller embedded for LTS350Q1-PD1/2(SAMSUNG 3.5” Portrait / 256K-color/ Reflective a-Si TFT LCD) LCC3600 Timing controller embedded for LTS350Q1-PE1/2(SAMSUNG 3.5” Portrait / 256K-color/ Transflective a-Si TFT LCD) Supports multiple screen size Typical actual screen size: 640x480, 320x240, 160x160, and others. Maximum frame buffer size is 4Mbytes. Maximum virtual screen size in 64K color mode : 2048x1024, and others UART 3-channel UART with DMA-based or interrupt-based operation Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data transmit/receive (Tx/Rx) Supports external clocks for the UART operation (UEXTCLK) Programmable baud rate Supports IrDA 1.0 Loopback mode for testing Each channel has internal 64-byte Tx FIFO and 64-byte Rx FIFO. A/D Converter & Touch Screen Interface 8-ch multiplexed ADC Max. 500KSPS and 10-bit Resolution Internal FET for direct Touch screen interface Watchdog Timer 16-bit Watchdog Timer Interrupt request or system reset at time-out IIC-Bus Interface 天津工程师范学院 2007 届本科生毕业设计5 1-ch Multi-Master IIC-Bus Serial, 8-bit oriented and bi-directional data transfers can be made at up to 100 Kbit/s in Standard mode or up to 400 Kbit/s in Fast mode. IIS-Bus Interface 1-ch IIS-bus for audio interface with DMA-based operation Serial, 8-/16-bit per channel data transfers 128 Bytes (64-Byte + 64-Byte) FIFO for Tx/Rx Supports IIS format and MSB-justified data format USB Host 2-port USB Host Complies with OHCI Rev. 1.0 Compatible with USB Specification version 1.1 USB Device 1-port USB Device 5 Endpoints for USB Device Compatible with USB Specification version 1.1 SD Host Interface Normal, Interrupt and DMA data transfer mode(byte, halfword, word transfer) DMA burst4 access support(only word transfer) Compatible with SD Memory Card Protocol version 1.0 Compatible with SDIO Card Protocol version 1.0 64 Bytes FIFO for Tx/Rx Compatible with Multimedia Card Protocol version 2.11 SPI Interface Compatible with 2-ch Serial Peripheral Interface Protocol version 2.11 2x8 bits Shift register for Tx/Rx DMA-based or interrupt-based operation Camera Interface ITU-R BT 601/656 8-bit mode support DZI (Digital Zoom In) capability Programmable polarity of video sync signals Max. 4096 x 4096 pixels input support ( 2048 x 2048 pixel input support for scaling) Image mirror and rotation (X-axis mirror, Y-axis mirror, and 180 rotation) Camera output format (RGB 16/24-bit and YCbCr 4:2:0/4:2:2 format) Operating Voltage Range Core : 1.5V for 400MHz, 1.35V for 300MHz Internal : 1.5V for 400MHz and 1.35V for 300MHz Memory:1.8V for 100MHz or 133MHz 天津工程师范学院 2007 届本科生毕业设计6 I/O : 3.3V / 2.5V Operating Frequency Fclk Up to 400MHz or 300MHz Hclk Up to 133MHz or 100MHz Pclk Up to 66MHz or 50MHz Package 332-FBGA Block Diagram天津工程师范学院 2007 届本科生毕业设计7 Pin Assignments天津工程师范学院 2007 届本科生毕业设计8译文三星 S3C2442B 32 位精简指令应用处理器用户手册绪言该用户手册描述了三星电子公司生产的 SC32442B 16/32 位精简指令结构的微处理器。三星电子的 SC32442B 是设计成用于手持式设备和仅用极小的体积便为手持设备和一般类型应用提供了低功耗、高性能微处理器解决方案。 外部存储器控制器 LCD 控制器（）专门 LCD DMA 控制器 4 通道 DMA 控制器关于外部请求管脚 3 通道 UART（红外 1.0，64 字节 T FIFO，和 64 字节 R FIFO） 2 路 SPI 总线 IIC 总线接口 IIS 音频 CODEC 接口 SD 主机接口 1.0 版本及兼容 MMC2.11 版本协议 2 通道 USB 主机控制/1 通道 USB 驱动控制器 4 通道 PWM 定时器/1 通道内部定时器/看门狗定时器 8 通道 10 位 ADC 和触摸屏接口 RTC 的日历功能 照相机接口（最大支持 4096 4096 像素输入，支持 2048 2048 像素浏览输入） 130 个通用 I/O 端口和 24 通道外部中断源 电源控制：正常模式，低速模式，空闲模式，睡眠模式 单芯片时钟发生器用于锁相环特性 体系结构 结合系统 和内嵌通用的应用程序 16/32 位 RISC 结构和强大的指令设置 ARM920T CPU core 内嵌 ARM 体系结构 MMU 去支持 WinCE， 指令 cache、数据 cache、读写缓冲. ARM920T 内核支持 ARMdebug 体系. 内建 AMBA 总线结构 2.0 版，包括 AHB 和 APB 两种总线. System Manager 系统管理 Little/Big Endian support. 天津工程师范学院 2007 届本科生毕业设计9 支持快速总线模式和异步总线模式 地址空间：每个模块提供 128M 字节（全部有 1G 字节） 支持每个模块数据总线可编程 8/16/32 位 固定模块开始地址从 0 模块到第 6 模块 第 7 模块的开始地址和模块尺寸是可编程的 八个存储器单元：6 个存储模块采用 ROM，RAM，两个存储单元用于ROM/SRAM/同步 DRAM。 完善的可编程访问周期用于所有存储器单元。 支持外部等待信号去延长总线周期 支持自刷新模式在 SDRAM 用于电源关闭时 支持多种类型的 ROM 用于导入 与非（NAND）闪存导入设备 支持来自与非（ NAND）闪存导入存储器 4KB 内部缓冲导入 支持存储存储器用于 NAND 闪存导入之后 支持高级的 NAND 闪存 高速缓冲存储器 64 路 高速缓存有 I-Cache(16K)和 D-Cache(16K) 每排 8 字长有一个有效位和两个无效位每排 Pseudo random or round robin replacement algorithm. Write-through or write-back cache operation to update the main memory. The write buffer can hold 16 words of data and four addresses. 时钟及电源管理 单芯片 MPLL 和 UPLL 发生器：UPLL 产生的时钟去供 USB 主机/驱动。MPLL 产生的时钟去提供 MCU 工作， 最大 400MHz1.5V 每个功能模块可通过软件来选择时钟 电源模式：正常模式，低速模式，空闲模式和睡眠模式 正常模式：正常工作模式 低速模式：低时钟频率没有锁相环 空闲模式：只有 CPU 时钟被关闭 关闭模式：所有的时钟都关闭 深睡眠模式：ARM 电源关闭内部时钟停止 睡眠模式：Core 电源包括所有外围是关闭。 启动通过 EINT15:0或 RTC 警告中断来唤醒睡眠模式 堆栈存储器天津工程师范学院 2007 届本科生毕业设计10 256Mbit or 512Mbit mSDR x32, VDD=1.8V 256Mbit 或 512Mbit mSDR x32, 512Mbit or 1Gbit Nand Flash x8, VDD=1.8V 中断控制器 59 个中断源（1 个是看门狗中断源，5 个定时中断源，9 个串口中断源，24 个中断源，4 路 DMA 中断，2 个 RTC 中断，2 个 ADC 中断，1 个 IIC 中断，2 个 SPI中断，2USB 中断，1 个 SDI 中断，1 个 LCD 中断，1 个电池检测中断，1 个 NAND中断和 2 相机中断） 。 可选电平触发或者边沿触发方式的外部中断源。 可编程边沿触发或电平触发优先级。 支持 FIQ 中断模式响应紧急事件。 脉冲调制（PWM）定时器 4 通道 16 位定时器为 PWM/每通道 16 位内部定时器是基于 DMA 或基于中断工作 可编程工作周期，频率和极性 死区的产生 支持外部时钟源 （实时时钟） 全时钟特性：微秒，秒，分，时，日，月，年 32.768KHz 工作频率 中断警告 定时中断应答 RTC 电池电压检测 通用输入/输出端口 24 个外部中断端口 130 多用途输入 /输出端口 DMA 控制器 4 个通道 DMA 控制器 支持存储器到存储器，IO 到存储器，存储器到 IO，IO 到 IO 的传送。 支持脉冲传送模式提高传送速率 LCD 控制器及 STN LCD 显示特点 支持 3 种类型的 STN LCD 面板：4 位扫描信号，8 位扫描信号显示模式 支持单色模式， 4 灰度级和 16 灰度级，256 色和 4096 色用于 STN LCD 支持多种屏幕尺寸 现有典型的屏幕尺寸：640x480,320x240,160x160 等等 最大缓存结构尺寸是 4M 字节天津工程师范学院 2007 届本科生毕业设计11 最大有效屏幕尺寸， （细薄膜晶体管）彩色显示器特点 支
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